1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `EDBG`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum EDBGR {
48 #[doc = "When in debug mode, the DMA continues to operate."]
49 _0,
50 #[doc = "When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared."]
51 _1,
52}
53impl EDBGR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 EDBGR::_0 => false,
69 EDBGR::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> EDBGR {
76 match value {
77 false => EDBGR::_0,
78 true => EDBGR::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == EDBGR::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == EDBGR::_1
90 }
91}
92#[doc = "Possible values of the field `ERCA`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum ERCAR {
95 #[doc = "Fixed priority arbitration is used for channel selection."]
96 _0,
97 #[doc = "Round robin arbitration is used for channel selection."]
98 _1,
99}
100impl ERCAR {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 ERCAR::_0 => false,
116 ERCAR::_1 => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> ERCAR {
123 match value {
124 false => ERCAR::_0,
125 true => ERCAR::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline]
130 pub fn is_0(&self) -> bool {
131 *self == ERCAR::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline]
135 pub fn is_1(&self) -> bool {
136 *self == ERCAR::_1
137 }
138}
139#[doc = "Possible values of the field `HOE`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum HOER {
142 #[doc = "Normal operation"]
143 _0,
144 #[doc = "Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared."]
145 _1,
146}
147impl HOER {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 HOER::_0 => false,
163 HOER::_1 => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> HOER {
170 match value {
171 false => HOER::_0,
172 true => HOER::_1,
173 }
174 }
175 #[doc = "Checks if the value of the field is `_0`"]
176 #[inline]
177 pub fn is_0(&self) -> bool {
178 *self == HOER::_0
179 }
180 #[doc = "Checks if the value of the field is `_1`"]
181 #[inline]
182 pub fn is_1(&self) -> bool {
183 *self == HOER::_1
184 }
185}
186#[doc = "Possible values of the field `HALT`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum HALTR {
189 #[doc = "Normal operation"]
190 _0,
191 #[doc = "Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared."]
192 _1,
193}
194impl HALTR {
195 #[doc = r" Returns `true` if the bit is clear (0)"]
196 #[inline]
197 pub fn bit_is_clear(&self) -> bool {
198 !self.bit()
199 }
200 #[doc = r" Returns `true` if the bit is set (1)"]
201 #[inline]
202 pub fn bit_is_set(&self) -> bool {
203 self.bit()
204 }
205 #[doc = r" Value of the field as raw bits"]
206 #[inline]
207 pub fn bit(&self) -> bool {
208 match *self {
209 HALTR::_0 => false,
210 HALTR::_1 => true,
211 }
212 }
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _from(value: bool) -> HALTR {
217 match value {
218 false => HALTR::_0,
219 true => HALTR::_1,
220 }
221 }
222 #[doc = "Checks if the value of the field is `_0`"]
223 #[inline]
224 pub fn is_0(&self) -> bool {
225 *self == HALTR::_0
226 }
227 #[doc = "Checks if the value of the field is `_1`"]
228 #[inline]
229 pub fn is_1(&self) -> bool {
230 *self == HALTR::_1
231 }
232}
233#[doc = "Possible values of the field `CLM`"]
234#[derive(Clone, Copy, Debug, PartialEq)]
235pub enum CLMR {
236 #[doc = "A minor loop channel link made to itself goes through channel arbitration before being activated again."]
237 _0,
238 #[doc = "A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop."]
239 _1,
240}
241impl CLMR {
242 #[doc = r" Returns `true` if the bit is clear (0)"]
243 #[inline]
244 pub fn bit_is_clear(&self) -> bool {
245 !self.bit()
246 }
247 #[doc = r" Returns `true` if the bit is set (1)"]
248 #[inline]
249 pub fn bit_is_set(&self) -> bool {
250 self.bit()
251 }
252 #[doc = r" Value of the field as raw bits"]
253 #[inline]
254 pub fn bit(&self) -> bool {
255 match *self {
256 CLMR::_0 => false,
257 CLMR::_1 => true,
258 }
259 }
260 #[allow(missing_docs)]
261 #[doc(hidden)]
262 #[inline]
263 pub fn _from(value: bool) -> CLMR {
264 match value {
265 false => CLMR::_0,
266 true => CLMR::_1,
267 }
268 }
269 #[doc = "Checks if the value of the field is `_0`"]
270 #[inline]
271 pub fn is_0(&self) -> bool {
272 *self == CLMR::_0
273 }
274 #[doc = "Checks if the value of the field is `_1`"]
275 #[inline]
276 pub fn is_1(&self) -> bool {
277 *self == CLMR::_1
278 }
279}
280#[doc = "Possible values of the field `EMLM`"]
281#[derive(Clone, Copy, Debug, PartialEq)]
282pub enum EMLMR {
283 #[doc = "Disabled. TCDn.word2 is defined as a 32-bit NBYTES field."]
284 _0,
285 #[doc = "Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled."]
286 _1,
287}
288impl EMLMR {
289 #[doc = r" Returns `true` if the bit is clear (0)"]
290 #[inline]
291 pub fn bit_is_clear(&self) -> bool {
292 !self.bit()
293 }
294 #[doc = r" Returns `true` if the bit is set (1)"]
295 #[inline]
296 pub fn bit_is_set(&self) -> bool {
297 self.bit()
298 }
299 #[doc = r" Value of the field as raw bits"]
300 #[inline]
301 pub fn bit(&self) -> bool {
302 match *self {
303 EMLMR::_0 => false,
304 EMLMR::_1 => true,
305 }
306 }
307 #[allow(missing_docs)]
308 #[doc(hidden)]
309 #[inline]
310 pub fn _from(value: bool) -> EMLMR {
311 match value {
312 false => EMLMR::_0,
313 true => EMLMR::_1,
314 }
315 }
316 #[doc = "Checks if the value of the field is `_0`"]
317 #[inline]
318 pub fn is_0(&self) -> bool {
319 *self == EMLMR::_0
320 }
321 #[doc = "Checks if the value of the field is `_1`"]
322 #[inline]
323 pub fn is_1(&self) -> bool {
324 *self == EMLMR::_1
325 }
326}
327#[doc = "Possible values of the field `ECX`"]
328#[derive(Clone, Copy, Debug, PartialEq)]
329pub enum ECXR {
330 #[doc = "Normal operation"]
331 _0,
332 #[doc = "Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the ES register and generating an optional error interrupt."]
333 _1,
334}
335impl ECXR {
336 #[doc = r" Returns `true` if the bit is clear (0)"]
337 #[inline]
338 pub fn bit_is_clear(&self) -> bool {
339 !self.bit()
340 }
341 #[doc = r" Returns `true` if the bit is set (1)"]
342 #[inline]
343 pub fn bit_is_set(&self) -> bool {
344 self.bit()
345 }
346 #[doc = r" Value of the field as raw bits"]
347 #[inline]
348 pub fn bit(&self) -> bool {
349 match *self {
350 ECXR::_0 => false,
351 ECXR::_1 => true,
352 }
353 }
354 #[allow(missing_docs)]
355 #[doc(hidden)]
356 #[inline]
357 pub fn _from(value: bool) -> ECXR {
358 match value {
359 false => ECXR::_0,
360 true => ECXR::_1,
361 }
362 }
363 #[doc = "Checks if the value of the field is `_0`"]
364 #[inline]
365 pub fn is_0(&self) -> bool {
366 *self == ECXR::_0
367 }
368 #[doc = "Checks if the value of the field is `_1`"]
369 #[inline]
370 pub fn is_1(&self) -> bool {
371 *self == ECXR::_1
372 }
373}
374#[doc = "Possible values of the field `CX`"]
375#[derive(Clone, Copy, Debug, PartialEq)]
376pub enum CXR {
377 #[doc = "Normal operation"]
378 _0,
379 #[doc = "Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed."]
380 _1,
381}
382impl CXR {
383 #[doc = r" Returns `true` if the bit is clear (0)"]
384 #[inline]
385 pub fn bit_is_clear(&self) -> bool {
386 !self.bit()
387 }
388 #[doc = r" Returns `true` if the bit is set (1)"]
389 #[inline]
390 pub fn bit_is_set(&self) -> bool {
391 self.bit()
392 }
393 #[doc = r" Value of the field as raw bits"]
394 #[inline]
395 pub fn bit(&self) -> bool {
396 match *self {
397 CXR::_0 => false,
398 CXR::_1 => true,
399 }
400 }
401 #[allow(missing_docs)]
402 #[doc(hidden)]
403 #[inline]
404 pub fn _from(value: bool) -> CXR {
405 match value {
406 false => CXR::_0,
407 true => CXR::_1,
408 }
409 }
410 #[doc = "Checks if the value of the field is `_0`"]
411 #[inline]
412 pub fn is_0(&self) -> bool {
413 *self == CXR::_0
414 }
415 #[doc = "Checks if the value of the field is `_1`"]
416 #[inline]
417 pub fn is_1(&self) -> bool {
418 *self == CXR::_1
419 }
420}
421#[doc = "Values that can be written to the field `EDBG`"]
422pub enum EDBGW {
423 #[doc = "When in debug mode, the DMA continues to operate."]
424 _0,
425 #[doc = "When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared."]
426 _1,
427}
428impl EDBGW {
429 #[allow(missing_docs)]
430 #[doc(hidden)]
431 #[inline]
432 pub fn _bits(&self) -> bool {
433 match *self {
434 EDBGW::_0 => false,
435 EDBGW::_1 => true,
436 }
437 }
438}
439#[doc = r" Proxy"]
440pub struct _EDBGW<'a> {
441 w: &'a mut W,
442}
443impl<'a> _EDBGW<'a> {
444 #[doc = r" Writes `variant` to the field"]
445 #[inline]
446 pub fn variant(self, variant: EDBGW) -> &'a mut W {
447 {
448 self.bit(variant._bits())
449 }
450 }
451 #[doc = "When in debug mode, the DMA continues to operate."]
452 #[inline]
453 pub fn _0(self) -> &'a mut W {
454 self.variant(EDBGW::_0)
455 }
456 #[doc = "When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared."]
457 #[inline]
458 pub fn _1(self) -> &'a mut W {
459 self.variant(EDBGW::_1)
460 }
461 #[doc = r" Sets the field bit"]
462 pub fn set_bit(self) -> &'a mut W {
463 self.bit(true)
464 }
465 #[doc = r" Clears the field bit"]
466 pub fn clear_bit(self) -> &'a mut W {
467 self.bit(false)
468 }
469 #[doc = r" Writes raw bits to the field"]
470 #[inline]
471 pub fn bit(self, value: bool) -> &'a mut W {
472 const MASK: bool = true;
473 const OFFSET: u8 = 1;
474 self.w.bits &= !((MASK as u32) << OFFSET);
475 self.w.bits |= ((value & MASK) as u32) << OFFSET;
476 self.w
477 }
478}
479#[doc = "Values that can be written to the field `ERCA`"]
480pub enum ERCAW {
481 #[doc = "Fixed priority arbitration is used for channel selection."]
482 _0,
483 #[doc = "Round robin arbitration is used for channel selection."]
484 _1,
485}
486impl ERCAW {
487 #[allow(missing_docs)]
488 #[doc(hidden)]
489 #[inline]
490 pub fn _bits(&self) -> bool {
491 match *self {
492 ERCAW::_0 => false,
493 ERCAW::_1 => true,
494 }
495 }
496}
497#[doc = r" Proxy"]
498pub struct _ERCAW<'a> {
499 w: &'a mut W,
500}
501impl<'a> _ERCAW<'a> {
502 #[doc = r" Writes `variant` to the field"]
503 #[inline]
504 pub fn variant(self, variant: ERCAW) -> &'a mut W {
505 {
506 self.bit(variant._bits())
507 }
508 }
509 #[doc = "Fixed priority arbitration is used for channel selection."]
510 #[inline]
511 pub fn _0(self) -> &'a mut W {
512 self.variant(ERCAW::_0)
513 }
514 #[doc = "Round robin arbitration is used for channel selection."]
515 #[inline]
516 pub fn _1(self) -> &'a mut W {
517 self.variant(ERCAW::_1)
518 }
519 #[doc = r" Sets the field bit"]
520 pub fn set_bit(self) -> &'a mut W {
521 self.bit(true)
522 }
523 #[doc = r" Clears the field bit"]
524 pub fn clear_bit(self) -> &'a mut W {
525 self.bit(false)
526 }
527 #[doc = r" Writes raw bits to the field"]
528 #[inline]
529 pub fn bit(self, value: bool) -> &'a mut W {
530 const MASK: bool = true;
531 const OFFSET: u8 = 2;
532 self.w.bits &= !((MASK as u32) << OFFSET);
533 self.w.bits |= ((value & MASK) as u32) << OFFSET;
534 self.w
535 }
536}
537#[doc = "Values that can be written to the field `HOE`"]
538pub enum HOEW {
539 #[doc = "Normal operation"]
540 _0,
541 #[doc = "Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared."]
542 _1,
543}
544impl HOEW {
545 #[allow(missing_docs)]
546 #[doc(hidden)]
547 #[inline]
548 pub fn _bits(&self) -> bool {
549 match *self {
550 HOEW::_0 => false,
551 HOEW::_1 => true,
552 }
553 }
554}
555#[doc = r" Proxy"]
556pub struct _HOEW<'a> {
557 w: &'a mut W,
558}
559impl<'a> _HOEW<'a> {
560 #[doc = r" Writes `variant` to the field"]
561 #[inline]
562 pub fn variant(self, variant: HOEW) -> &'a mut W {
563 {
564 self.bit(variant._bits())
565 }
566 }
567 #[doc = "Normal operation"]
568 #[inline]
569 pub fn _0(self) -> &'a mut W {
570 self.variant(HOEW::_0)
571 }
572 #[doc = "Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared."]
573 #[inline]
574 pub fn _1(self) -> &'a mut W {
575 self.variant(HOEW::_1)
576 }
577 #[doc = r" Sets the field bit"]
578 pub fn set_bit(self) -> &'a mut W {
579 self.bit(true)
580 }
581 #[doc = r" Clears the field bit"]
582 pub fn clear_bit(self) -> &'a mut W {
583 self.bit(false)
584 }
585 #[doc = r" Writes raw bits to the field"]
586 #[inline]
587 pub fn bit(self, value: bool) -> &'a mut W {
588 const MASK: bool = true;
589 const OFFSET: u8 = 4;
590 self.w.bits &= !((MASK as u32) << OFFSET);
591 self.w.bits |= ((value & MASK) as u32) << OFFSET;
592 self.w
593 }
594}
595#[doc = "Values that can be written to the field `HALT`"]
596pub enum HALTW {
597 #[doc = "Normal operation"]
598 _0,
599 #[doc = "Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared."]
600 _1,
601}
602impl HALTW {
603 #[allow(missing_docs)]
604 #[doc(hidden)]
605 #[inline]
606 pub fn _bits(&self) -> bool {
607 match *self {
608 HALTW::_0 => false,
609 HALTW::_1 => true,
610 }
611 }
612}
613#[doc = r" Proxy"]
614pub struct _HALTW<'a> {
615 w: &'a mut W,
616}
617impl<'a> _HALTW<'a> {
618 #[doc = r" Writes `variant` to the field"]
619 #[inline]
620 pub fn variant(self, variant: HALTW) -> &'a mut W {
621 {
622 self.bit(variant._bits())
623 }
624 }
625 #[doc = "Normal operation"]
626 #[inline]
627 pub fn _0(self) -> &'a mut W {
628 self.variant(HALTW::_0)
629 }
630 #[doc = "Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared."]
631 #[inline]
632 pub fn _1(self) -> &'a mut W {
633 self.variant(HALTW::_1)
634 }
635 #[doc = r" Sets the field bit"]
636 pub fn set_bit(self) -> &'a mut W {
637 self.bit(true)
638 }
639 #[doc = r" Clears the field bit"]
640 pub fn clear_bit(self) -> &'a mut W {
641 self.bit(false)
642 }
643 #[doc = r" Writes raw bits to the field"]
644 #[inline]
645 pub fn bit(self, value: bool) -> &'a mut W {
646 const MASK: bool = true;
647 const OFFSET: u8 = 5;
648 self.w.bits &= !((MASK as u32) << OFFSET);
649 self.w.bits |= ((value & MASK) as u32) << OFFSET;
650 self.w
651 }
652}
653#[doc = "Values that can be written to the field `CLM`"]
654pub enum CLMW {
655 #[doc = "A minor loop channel link made to itself goes through channel arbitration before being activated again."]
656 _0,
657 #[doc = "A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop."]
658 _1,
659}
660impl CLMW {
661 #[allow(missing_docs)]
662 #[doc(hidden)]
663 #[inline]
664 pub fn _bits(&self) -> bool {
665 match *self {
666 CLMW::_0 => false,
667 CLMW::_1 => true,
668 }
669 }
670}
671#[doc = r" Proxy"]
672pub struct _CLMW<'a> {
673 w: &'a mut W,
674}
675impl<'a> _CLMW<'a> {
676 #[doc = r" Writes `variant` to the field"]
677 #[inline]
678 pub fn variant(self, variant: CLMW) -> &'a mut W {
679 {
680 self.bit(variant._bits())
681 }
682 }
683 #[doc = "A minor loop channel link made to itself goes through channel arbitration before being activated again."]
684 #[inline]
685 pub fn _0(self) -> &'a mut W {
686 self.variant(CLMW::_0)
687 }
688 #[doc = "A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop."]
689 #[inline]
690 pub fn _1(self) -> &'a mut W {
691 self.variant(CLMW::_1)
692 }
693 #[doc = r" Sets the field bit"]
694 pub fn set_bit(self) -> &'a mut W {
695 self.bit(true)
696 }
697 #[doc = r" Clears the field bit"]
698 pub fn clear_bit(self) -> &'a mut W {
699 self.bit(false)
700 }
701 #[doc = r" Writes raw bits to the field"]
702 #[inline]
703 pub fn bit(self, value: bool) -> &'a mut W {
704 const MASK: bool = true;
705 const OFFSET: u8 = 6;
706 self.w.bits &= !((MASK as u32) << OFFSET);
707 self.w.bits |= ((value & MASK) as u32) << OFFSET;
708 self.w
709 }
710}
711#[doc = "Values that can be written to the field `EMLM`"]
712pub enum EMLMW {
713 #[doc = "Disabled. TCDn.word2 is defined as a 32-bit NBYTES field."]
714 _0,
715 #[doc = "Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled."]
716 _1,
717}
718impl EMLMW {
719 #[allow(missing_docs)]
720 #[doc(hidden)]
721 #[inline]
722 pub fn _bits(&self) -> bool {
723 match *self {
724 EMLMW::_0 => false,
725 EMLMW::_1 => true,
726 }
727 }
728}
729#[doc = r" Proxy"]
730pub struct _EMLMW<'a> {
731 w: &'a mut W,
732}
733impl<'a> _EMLMW<'a> {
734 #[doc = r" Writes `variant` to the field"]
735 #[inline]
736 pub fn variant(self, variant: EMLMW) -> &'a mut W {
737 {
738 self.bit(variant._bits())
739 }
740 }
741 #[doc = "Disabled. TCDn.word2 is defined as a 32-bit NBYTES field."]
742 #[inline]
743 pub fn _0(self) -> &'a mut W {
744 self.variant(EMLMW::_0)
745 }
746 #[doc = "Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled."]
747 #[inline]
748 pub fn _1(self) -> &'a mut W {
749 self.variant(EMLMW::_1)
750 }
751 #[doc = r" Sets the field bit"]
752 pub fn set_bit(self) -> &'a mut W {
753 self.bit(true)
754 }
755 #[doc = r" Clears the field bit"]
756 pub fn clear_bit(self) -> &'a mut W {
757 self.bit(false)
758 }
759 #[doc = r" Writes raw bits to the field"]
760 #[inline]
761 pub fn bit(self, value: bool) -> &'a mut W {
762 const MASK: bool = true;
763 const OFFSET: u8 = 7;
764 self.w.bits &= !((MASK as u32) << OFFSET);
765 self.w.bits |= ((value & MASK) as u32) << OFFSET;
766 self.w
767 }
768}
769#[doc = "Values that can be written to the field `ECX`"]
770pub enum ECXW {
771 #[doc = "Normal operation"]
772 _0,
773 #[doc = "Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the ES register and generating an optional error interrupt."]
774 _1,
775}
776impl ECXW {
777 #[allow(missing_docs)]
778 #[doc(hidden)]
779 #[inline]
780 pub fn _bits(&self) -> bool {
781 match *self {
782 ECXW::_0 => false,
783 ECXW::_1 => true,
784 }
785 }
786}
787#[doc = r" Proxy"]
788pub struct _ECXW<'a> {
789 w: &'a mut W,
790}
791impl<'a> _ECXW<'a> {
792 #[doc = r" Writes `variant` to the field"]
793 #[inline]
794 pub fn variant(self, variant: ECXW) -> &'a mut W {
795 {
796 self.bit(variant._bits())
797 }
798 }
799 #[doc = "Normal operation"]
800 #[inline]
801 pub fn _0(self) -> &'a mut W {
802 self.variant(ECXW::_0)
803 }
804 #[doc = "Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the ES register and generating an optional error interrupt."]
805 #[inline]
806 pub fn _1(self) -> &'a mut W {
807 self.variant(ECXW::_1)
808 }
809 #[doc = r" Sets the field bit"]
810 pub fn set_bit(self) -> &'a mut W {
811 self.bit(true)
812 }
813 #[doc = r" Clears the field bit"]
814 pub fn clear_bit(self) -> &'a mut W {
815 self.bit(false)
816 }
817 #[doc = r" Writes raw bits to the field"]
818 #[inline]
819 pub fn bit(self, value: bool) -> &'a mut W {
820 const MASK: bool = true;
821 const OFFSET: u8 = 16;
822 self.w.bits &= !((MASK as u32) << OFFSET);
823 self.w.bits |= ((value & MASK) as u32) << OFFSET;
824 self.w
825 }
826}
827#[doc = "Values that can be written to the field `CX`"]
828pub enum CXW {
829 #[doc = "Normal operation"]
830 _0,
831 #[doc = "Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed."]
832 _1,
833}
834impl CXW {
835 #[allow(missing_docs)]
836 #[doc(hidden)]
837 #[inline]
838 pub fn _bits(&self) -> bool {
839 match *self {
840 CXW::_0 => false,
841 CXW::_1 => true,
842 }
843 }
844}
845#[doc = r" Proxy"]
846pub struct _CXW<'a> {
847 w: &'a mut W,
848}
849impl<'a> _CXW<'a> {
850 #[doc = r" Writes `variant` to the field"]
851 #[inline]
852 pub fn variant(self, variant: CXW) -> &'a mut W {
853 {
854 self.bit(variant._bits())
855 }
856 }
857 #[doc = "Normal operation"]
858 #[inline]
859 pub fn _0(self) -> &'a mut W {
860 self.variant(CXW::_0)
861 }
862 #[doc = "Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed."]
863 #[inline]
864 pub fn _1(self) -> &'a mut W {
865 self.variant(CXW::_1)
866 }
867 #[doc = r" Sets the field bit"]
868 pub fn set_bit(self) -> &'a mut W {
869 self.bit(true)
870 }
871 #[doc = r" Clears the field bit"]
872 pub fn clear_bit(self) -> &'a mut W {
873 self.bit(false)
874 }
875 #[doc = r" Writes raw bits to the field"]
876 #[inline]
877 pub fn bit(self, value: bool) -> &'a mut W {
878 const MASK: bool = true;
879 const OFFSET: u8 = 17;
880 self.w.bits &= !((MASK as u32) << OFFSET);
881 self.w.bits |= ((value & MASK) as u32) << OFFSET;
882 self.w
883 }
884}
885impl R {
886 #[doc = r" Value of the register as raw bits"]
887 #[inline]
888 pub fn bits(&self) -> u32 {
889 self.bits
890 }
891 #[doc = "Bit 1 - Enable Debug"]
892 #[inline]
893 pub fn edbg(&self) -> EDBGR {
894 EDBGR::_from({
895 const MASK: bool = true;
896 const OFFSET: u8 = 1;
897 ((self.bits >> OFFSET) & MASK as u32) != 0
898 })
899 }
900 #[doc = "Bit 2 - Enable Round Robin Channel Arbitration"]
901 #[inline]
902 pub fn erca(&self) -> ERCAR {
903 ERCAR::_from({
904 const MASK: bool = true;
905 const OFFSET: u8 = 2;
906 ((self.bits >> OFFSET) & MASK as u32) != 0
907 })
908 }
909 #[doc = "Bit 4 - Halt On Error"]
910 #[inline]
911 pub fn hoe(&self) -> HOER {
912 HOER::_from({
913 const MASK: bool = true;
914 const OFFSET: u8 = 4;
915 ((self.bits >> OFFSET) & MASK as u32) != 0
916 })
917 }
918 #[doc = "Bit 5 - Halt DMA Operations"]
919 #[inline]
920 pub fn halt(&self) -> HALTR {
921 HALTR::_from({
922 const MASK: bool = true;
923 const OFFSET: u8 = 5;
924 ((self.bits >> OFFSET) & MASK as u32) != 0
925 })
926 }
927 #[doc = "Bit 6 - Continuous Link Mode"]
928 #[inline]
929 pub fn clm(&self) -> CLMR {
930 CLMR::_from({
931 const MASK: bool = true;
932 const OFFSET: u8 = 6;
933 ((self.bits >> OFFSET) & MASK as u32) != 0
934 })
935 }
936 #[doc = "Bit 7 - Enable Minor Loop Mapping"]
937 #[inline]
938 pub fn emlm(&self) -> EMLMR {
939 EMLMR::_from({
940 const MASK: bool = true;
941 const OFFSET: u8 = 7;
942 ((self.bits >> OFFSET) & MASK as u32) != 0
943 })
944 }
945 #[doc = "Bit 16 - Error Cancel Transfer"]
946 #[inline]
947 pub fn ecx(&self) -> ECXR {
948 ECXR::_from({
949 const MASK: bool = true;
950 const OFFSET: u8 = 16;
951 ((self.bits >> OFFSET) & MASK as u32) != 0
952 })
953 }
954 #[doc = "Bit 17 - Cancel Transfer"]
955 #[inline]
956 pub fn cx(&self) -> CXR {
957 CXR::_from({
958 const MASK: bool = true;
959 const OFFSET: u8 = 17;
960 ((self.bits >> OFFSET) & MASK as u32) != 0
961 })
962 }
963}
964impl W {
965 #[doc = r" Reset value of the register"]
966 #[inline]
967 pub fn reset_value() -> W {
968 W { bits: 0 }
969 }
970 #[doc = r" Writes raw bits to the register"]
971 #[inline]
972 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
973 self.bits = bits;
974 self
975 }
976 #[doc = "Bit 1 - Enable Debug"]
977 #[inline]
978 pub fn edbg(&mut self) -> _EDBGW {
979 _EDBGW { w: self }
980 }
981 #[doc = "Bit 2 - Enable Round Robin Channel Arbitration"]
982 #[inline]
983 pub fn erca(&mut self) -> _ERCAW {
984 _ERCAW { w: self }
985 }
986 #[doc = "Bit 4 - Halt On Error"]
987 #[inline]
988 pub fn hoe(&mut self) -> _HOEW {
989 _HOEW { w: self }
990 }
991 #[doc = "Bit 5 - Halt DMA Operations"]
992 #[inline]
993 pub fn halt(&mut self) -> _HALTW {
994 _HALTW { w: self }
995 }
996 #[doc = "Bit 6 - Continuous Link Mode"]
997 #[inline]
998 pub fn clm(&mut self) -> _CLMW {
999 _CLMW { w: self }
1000 }
1001 #[doc = "Bit 7 - Enable Minor Loop Mapping"]
1002 #[inline]
1003 pub fn emlm(&mut self) -> _EMLMW {
1004 _EMLMW { w: self }
1005 }
1006 #[doc = "Bit 16 - Error Cancel Transfer"]
1007 #[inline]
1008 pub fn ecx(&mut self) -> _ECXW {
1009 _ECXW { w: self }
1010 }
1011 #[doc = "Bit 17 - Cancel Transfer"]
1012 #[inline]
1013 pub fn cx(&mut self) -> _CXW {
1014 _CXW { w: self }
1015 }
1016}