mk20d7/i2c1/c2/
mod.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u8,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u8,
8}
9impl super::C2 {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct ADR {
47    bits: u8,
48}
49impl ADR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bits(&self) -> u8 {
53        self.bits
54    }
55}
56#[doc = "Possible values of the field `RMEN`"]
57#[derive(Clone, Copy, Debug, PartialEq)]
58pub enum RMENR {
59    #[doc = "Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers."]
60    _0,
61    #[doc = "Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers."]
62    _1,
63}
64impl RMENR {
65    #[doc = r" Returns `true` if the bit is clear (0)"]
66    #[inline]
67    pub fn bit_is_clear(&self) -> bool {
68        !self.bit()
69    }
70    #[doc = r" Returns `true` if the bit is set (1)"]
71    #[inline]
72    pub fn bit_is_set(&self) -> bool {
73        self.bit()
74    }
75    #[doc = r" Value of the field as raw bits"]
76    #[inline]
77    pub fn bit(&self) -> bool {
78        match *self {
79            RMENR::_0 => false,
80            RMENR::_1 => true,
81        }
82    }
83    #[allow(missing_docs)]
84    #[doc(hidden)]
85    #[inline]
86    pub fn _from(value: bool) -> RMENR {
87        match value {
88            false => RMENR::_0,
89            true => RMENR::_1,
90        }
91    }
92    #[doc = "Checks if the value of the field is `_0`"]
93    #[inline]
94    pub fn is_0(&self) -> bool {
95        *self == RMENR::_0
96    }
97    #[doc = "Checks if the value of the field is `_1`"]
98    #[inline]
99    pub fn is_1(&self) -> bool {
100        *self == RMENR::_1
101    }
102}
103#[doc = "Possible values of the field `SBRC`"]
104#[derive(Clone, Copy, Debug, PartialEq)]
105pub enum SBRCR {
106    #[doc = "The slave baud rate follows the master baud rate and clock stretching may occur"]
107    _0,
108    #[doc = "Slave baud rate is independent of the master baud rate"]
109    _1,
110}
111impl SBRCR {
112    #[doc = r" Returns `true` if the bit is clear (0)"]
113    #[inline]
114    pub fn bit_is_clear(&self) -> bool {
115        !self.bit()
116    }
117    #[doc = r" Returns `true` if the bit is set (1)"]
118    #[inline]
119    pub fn bit_is_set(&self) -> bool {
120        self.bit()
121    }
122    #[doc = r" Value of the field as raw bits"]
123    #[inline]
124    pub fn bit(&self) -> bool {
125        match *self {
126            SBRCR::_0 => false,
127            SBRCR::_1 => true,
128        }
129    }
130    #[allow(missing_docs)]
131    #[doc(hidden)]
132    #[inline]
133    pub fn _from(value: bool) -> SBRCR {
134        match value {
135            false => SBRCR::_0,
136            true => SBRCR::_1,
137        }
138    }
139    #[doc = "Checks if the value of the field is `_0`"]
140    #[inline]
141    pub fn is_0(&self) -> bool {
142        *self == SBRCR::_0
143    }
144    #[doc = "Checks if the value of the field is `_1`"]
145    #[inline]
146    pub fn is_1(&self) -> bool {
147        *self == SBRCR::_1
148    }
149}
150#[doc = "Possible values of the field `HDRS`"]
151#[derive(Clone, Copy, Debug, PartialEq)]
152pub enum HDRSR {
153    #[doc = "Normal drive mode"]
154    _0,
155    #[doc = "High drive mode"]
156    _1,
157}
158impl HDRSR {
159    #[doc = r" Returns `true` if the bit is clear (0)"]
160    #[inline]
161    pub fn bit_is_clear(&self) -> bool {
162        !self.bit()
163    }
164    #[doc = r" Returns `true` if the bit is set (1)"]
165    #[inline]
166    pub fn bit_is_set(&self) -> bool {
167        self.bit()
168    }
169    #[doc = r" Value of the field as raw bits"]
170    #[inline]
171    pub fn bit(&self) -> bool {
172        match *self {
173            HDRSR::_0 => false,
174            HDRSR::_1 => true,
175        }
176    }
177    #[allow(missing_docs)]
178    #[doc(hidden)]
179    #[inline]
180    pub fn _from(value: bool) -> HDRSR {
181        match value {
182            false => HDRSR::_0,
183            true => HDRSR::_1,
184        }
185    }
186    #[doc = "Checks if the value of the field is `_0`"]
187    #[inline]
188    pub fn is_0(&self) -> bool {
189        *self == HDRSR::_0
190    }
191    #[doc = "Checks if the value of the field is `_1`"]
192    #[inline]
193    pub fn is_1(&self) -> bool {
194        *self == HDRSR::_1
195    }
196}
197#[doc = "Possible values of the field `ADEXT`"]
198#[derive(Clone, Copy, Debug, PartialEq)]
199pub enum ADEXTR {
200    #[doc = "7-bit address scheme"]
201    _0,
202    #[doc = "10-bit address scheme"]
203    _1,
204}
205impl ADEXTR {
206    #[doc = r" Returns `true` if the bit is clear (0)"]
207    #[inline]
208    pub fn bit_is_clear(&self) -> bool {
209        !self.bit()
210    }
211    #[doc = r" Returns `true` if the bit is set (1)"]
212    #[inline]
213    pub fn bit_is_set(&self) -> bool {
214        self.bit()
215    }
216    #[doc = r" Value of the field as raw bits"]
217    #[inline]
218    pub fn bit(&self) -> bool {
219        match *self {
220            ADEXTR::_0 => false,
221            ADEXTR::_1 => true,
222        }
223    }
224    #[allow(missing_docs)]
225    #[doc(hidden)]
226    #[inline]
227    pub fn _from(value: bool) -> ADEXTR {
228        match value {
229            false => ADEXTR::_0,
230            true => ADEXTR::_1,
231        }
232    }
233    #[doc = "Checks if the value of the field is `_0`"]
234    #[inline]
235    pub fn is_0(&self) -> bool {
236        *self == ADEXTR::_0
237    }
238    #[doc = "Checks if the value of the field is `_1`"]
239    #[inline]
240    pub fn is_1(&self) -> bool {
241        *self == ADEXTR::_1
242    }
243}
244#[doc = "Possible values of the field `GCAEN`"]
245#[derive(Clone, Copy, Debug, PartialEq)]
246pub enum GCAENR {
247    #[doc = "Disabled"]
248    _0,
249    #[doc = "Enabled"]
250    _1,
251}
252impl GCAENR {
253    #[doc = r" Returns `true` if the bit is clear (0)"]
254    #[inline]
255    pub fn bit_is_clear(&self) -> bool {
256        !self.bit()
257    }
258    #[doc = r" Returns `true` if the bit is set (1)"]
259    #[inline]
260    pub fn bit_is_set(&self) -> bool {
261        self.bit()
262    }
263    #[doc = r" Value of the field as raw bits"]
264    #[inline]
265    pub fn bit(&self) -> bool {
266        match *self {
267            GCAENR::_0 => false,
268            GCAENR::_1 => true,
269        }
270    }
271    #[allow(missing_docs)]
272    #[doc(hidden)]
273    #[inline]
274    pub fn _from(value: bool) -> GCAENR {
275        match value {
276            false => GCAENR::_0,
277            true => GCAENR::_1,
278        }
279    }
280    #[doc = "Checks if the value of the field is `_0`"]
281    #[inline]
282    pub fn is_0(&self) -> bool {
283        *self == GCAENR::_0
284    }
285    #[doc = "Checks if the value of the field is `_1`"]
286    #[inline]
287    pub fn is_1(&self) -> bool {
288        *self == GCAENR::_1
289    }
290}
291#[doc = r" Proxy"]
292pub struct _ADW<'a> {
293    w: &'a mut W,
294}
295impl<'a> _ADW<'a> {
296    #[doc = r" Writes raw bits to the field"]
297    #[inline]
298    pub unsafe fn bits(self, value: u8) -> &'a mut W {
299        const MASK: u8 = 7;
300        const OFFSET: u8 = 0;
301        self.w.bits &= !((MASK as u8) << OFFSET);
302        self.w.bits |= ((value & MASK) as u8) << OFFSET;
303        self.w
304    }
305}
306#[doc = "Values that can be written to the field `RMEN`"]
307pub enum RMENW {
308    #[doc = "Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers."]
309    _0,
310    #[doc = "Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers."]
311    _1,
312}
313impl RMENW {
314    #[allow(missing_docs)]
315    #[doc(hidden)]
316    #[inline]
317    pub fn _bits(&self) -> bool {
318        match *self {
319            RMENW::_0 => false,
320            RMENW::_1 => true,
321        }
322    }
323}
324#[doc = r" Proxy"]
325pub struct _RMENW<'a> {
326    w: &'a mut W,
327}
328impl<'a> _RMENW<'a> {
329    #[doc = r" Writes `variant` to the field"]
330    #[inline]
331    pub fn variant(self, variant: RMENW) -> &'a mut W {
332        {
333            self.bit(variant._bits())
334        }
335    }
336    #[doc = "Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers."]
337    #[inline]
338    pub fn _0(self) -> &'a mut W {
339        self.variant(RMENW::_0)
340    }
341    #[doc = "Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers."]
342    #[inline]
343    pub fn _1(self) -> &'a mut W {
344        self.variant(RMENW::_1)
345    }
346    #[doc = r" Sets the field bit"]
347    pub fn set_bit(self) -> &'a mut W {
348        self.bit(true)
349    }
350    #[doc = r" Clears the field bit"]
351    pub fn clear_bit(self) -> &'a mut W {
352        self.bit(false)
353    }
354    #[doc = r" Writes raw bits to the field"]
355    #[inline]
356    pub fn bit(self, value: bool) -> &'a mut W {
357        const MASK: bool = true;
358        const OFFSET: u8 = 3;
359        self.w.bits &= !((MASK as u8) << OFFSET);
360        self.w.bits |= ((value & MASK) as u8) << OFFSET;
361        self.w
362    }
363}
364#[doc = "Values that can be written to the field `SBRC`"]
365pub enum SBRCW {
366    #[doc = "The slave baud rate follows the master baud rate and clock stretching may occur"]
367    _0,
368    #[doc = "Slave baud rate is independent of the master baud rate"]
369    _1,
370}
371impl SBRCW {
372    #[allow(missing_docs)]
373    #[doc(hidden)]
374    #[inline]
375    pub fn _bits(&self) -> bool {
376        match *self {
377            SBRCW::_0 => false,
378            SBRCW::_1 => true,
379        }
380    }
381}
382#[doc = r" Proxy"]
383pub struct _SBRCW<'a> {
384    w: &'a mut W,
385}
386impl<'a> _SBRCW<'a> {
387    #[doc = r" Writes `variant` to the field"]
388    #[inline]
389    pub fn variant(self, variant: SBRCW) -> &'a mut W {
390        {
391            self.bit(variant._bits())
392        }
393    }
394    #[doc = "The slave baud rate follows the master baud rate and clock stretching may occur"]
395    #[inline]
396    pub fn _0(self) -> &'a mut W {
397        self.variant(SBRCW::_0)
398    }
399    #[doc = "Slave baud rate is independent of the master baud rate"]
400    #[inline]
401    pub fn _1(self) -> &'a mut W {
402        self.variant(SBRCW::_1)
403    }
404    #[doc = r" Sets the field bit"]
405    pub fn set_bit(self) -> &'a mut W {
406        self.bit(true)
407    }
408    #[doc = r" Clears the field bit"]
409    pub fn clear_bit(self) -> &'a mut W {
410        self.bit(false)
411    }
412    #[doc = r" Writes raw bits to the field"]
413    #[inline]
414    pub fn bit(self, value: bool) -> &'a mut W {
415        const MASK: bool = true;
416        const OFFSET: u8 = 4;
417        self.w.bits &= !((MASK as u8) << OFFSET);
418        self.w.bits |= ((value & MASK) as u8) << OFFSET;
419        self.w
420    }
421}
422#[doc = "Values that can be written to the field `HDRS`"]
423pub enum HDRSW {
424    #[doc = "Normal drive mode"]
425    _0,
426    #[doc = "High drive mode"]
427    _1,
428}
429impl HDRSW {
430    #[allow(missing_docs)]
431    #[doc(hidden)]
432    #[inline]
433    pub fn _bits(&self) -> bool {
434        match *self {
435            HDRSW::_0 => false,
436            HDRSW::_1 => true,
437        }
438    }
439}
440#[doc = r" Proxy"]
441pub struct _HDRSW<'a> {
442    w: &'a mut W,
443}
444impl<'a> _HDRSW<'a> {
445    #[doc = r" Writes `variant` to the field"]
446    #[inline]
447    pub fn variant(self, variant: HDRSW) -> &'a mut W {
448        {
449            self.bit(variant._bits())
450        }
451    }
452    #[doc = "Normal drive mode"]
453    #[inline]
454    pub fn _0(self) -> &'a mut W {
455        self.variant(HDRSW::_0)
456    }
457    #[doc = "High drive mode"]
458    #[inline]
459    pub fn _1(self) -> &'a mut W {
460        self.variant(HDRSW::_1)
461    }
462    #[doc = r" Sets the field bit"]
463    pub fn set_bit(self) -> &'a mut W {
464        self.bit(true)
465    }
466    #[doc = r" Clears the field bit"]
467    pub fn clear_bit(self) -> &'a mut W {
468        self.bit(false)
469    }
470    #[doc = r" Writes raw bits to the field"]
471    #[inline]
472    pub fn bit(self, value: bool) -> &'a mut W {
473        const MASK: bool = true;
474        const OFFSET: u8 = 5;
475        self.w.bits &= !((MASK as u8) << OFFSET);
476        self.w.bits |= ((value & MASK) as u8) << OFFSET;
477        self.w
478    }
479}
480#[doc = "Values that can be written to the field `ADEXT`"]
481pub enum ADEXTW {
482    #[doc = "7-bit address scheme"]
483    _0,
484    #[doc = "10-bit address scheme"]
485    _1,
486}
487impl ADEXTW {
488    #[allow(missing_docs)]
489    #[doc(hidden)]
490    #[inline]
491    pub fn _bits(&self) -> bool {
492        match *self {
493            ADEXTW::_0 => false,
494            ADEXTW::_1 => true,
495        }
496    }
497}
498#[doc = r" Proxy"]
499pub struct _ADEXTW<'a> {
500    w: &'a mut W,
501}
502impl<'a> _ADEXTW<'a> {
503    #[doc = r" Writes `variant` to the field"]
504    #[inline]
505    pub fn variant(self, variant: ADEXTW) -> &'a mut W {
506        {
507            self.bit(variant._bits())
508        }
509    }
510    #[doc = "7-bit address scheme"]
511    #[inline]
512    pub fn _0(self) -> &'a mut W {
513        self.variant(ADEXTW::_0)
514    }
515    #[doc = "10-bit address scheme"]
516    #[inline]
517    pub fn _1(self) -> &'a mut W {
518        self.variant(ADEXTW::_1)
519    }
520    #[doc = r" Sets the field bit"]
521    pub fn set_bit(self) -> &'a mut W {
522        self.bit(true)
523    }
524    #[doc = r" Clears the field bit"]
525    pub fn clear_bit(self) -> &'a mut W {
526        self.bit(false)
527    }
528    #[doc = r" Writes raw bits to the field"]
529    #[inline]
530    pub fn bit(self, value: bool) -> &'a mut W {
531        const MASK: bool = true;
532        const OFFSET: u8 = 6;
533        self.w.bits &= !((MASK as u8) << OFFSET);
534        self.w.bits |= ((value & MASK) as u8) << OFFSET;
535        self.w
536    }
537}
538#[doc = "Values that can be written to the field `GCAEN`"]
539pub enum GCAENW {
540    #[doc = "Disabled"]
541    _0,
542    #[doc = "Enabled"]
543    _1,
544}
545impl GCAENW {
546    #[allow(missing_docs)]
547    #[doc(hidden)]
548    #[inline]
549    pub fn _bits(&self) -> bool {
550        match *self {
551            GCAENW::_0 => false,
552            GCAENW::_1 => true,
553        }
554    }
555}
556#[doc = r" Proxy"]
557pub struct _GCAENW<'a> {
558    w: &'a mut W,
559}
560impl<'a> _GCAENW<'a> {
561    #[doc = r" Writes `variant` to the field"]
562    #[inline]
563    pub fn variant(self, variant: GCAENW) -> &'a mut W {
564        {
565            self.bit(variant._bits())
566        }
567    }
568    #[doc = "Disabled"]
569    #[inline]
570    pub fn _0(self) -> &'a mut W {
571        self.variant(GCAENW::_0)
572    }
573    #[doc = "Enabled"]
574    #[inline]
575    pub fn _1(self) -> &'a mut W {
576        self.variant(GCAENW::_1)
577    }
578    #[doc = r" Sets the field bit"]
579    pub fn set_bit(self) -> &'a mut W {
580        self.bit(true)
581    }
582    #[doc = r" Clears the field bit"]
583    pub fn clear_bit(self) -> &'a mut W {
584        self.bit(false)
585    }
586    #[doc = r" Writes raw bits to the field"]
587    #[inline]
588    pub fn bit(self, value: bool) -> &'a mut W {
589        const MASK: bool = true;
590        const OFFSET: u8 = 7;
591        self.w.bits &= !((MASK as u8) << OFFSET);
592        self.w.bits |= ((value & MASK) as u8) << OFFSET;
593        self.w
594    }
595}
596impl R {
597    #[doc = r" Value of the register as raw bits"]
598    #[inline]
599    pub fn bits(&self) -> u8 {
600        self.bits
601    }
602    #[doc = "Bits 0:2 - Slave address"]
603    #[inline]
604    pub fn ad(&self) -> ADR {
605        let bits = {
606            const MASK: u8 = 7;
607            const OFFSET: u8 = 0;
608            ((self.bits >> OFFSET) & MASK as u8) as u8
609        };
610        ADR { bits }
611    }
612    #[doc = "Bit 3 - Range address matching enable"]
613    #[inline]
614    pub fn rmen(&self) -> RMENR {
615        RMENR::_from({
616            const MASK: bool = true;
617            const OFFSET: u8 = 3;
618            ((self.bits >> OFFSET) & MASK as u8) != 0
619        })
620    }
621    #[doc = "Bit 4 - Slave baud rate control"]
622    #[inline]
623    pub fn sbrc(&self) -> SBRCR {
624        SBRCR::_from({
625            const MASK: bool = true;
626            const OFFSET: u8 = 4;
627            ((self.bits >> OFFSET) & MASK as u8) != 0
628        })
629    }
630    #[doc = "Bit 5 - High drive select"]
631    #[inline]
632    pub fn hdrs(&self) -> HDRSR {
633        HDRSR::_from({
634            const MASK: bool = true;
635            const OFFSET: u8 = 5;
636            ((self.bits >> OFFSET) & MASK as u8) != 0
637        })
638    }
639    #[doc = "Bit 6 - Address extension"]
640    #[inline]
641    pub fn adext(&self) -> ADEXTR {
642        ADEXTR::_from({
643            const MASK: bool = true;
644            const OFFSET: u8 = 6;
645            ((self.bits >> OFFSET) & MASK as u8) != 0
646        })
647    }
648    #[doc = "Bit 7 - General call address enable"]
649    #[inline]
650    pub fn gcaen(&self) -> GCAENR {
651        GCAENR::_from({
652            const MASK: bool = true;
653            const OFFSET: u8 = 7;
654            ((self.bits >> OFFSET) & MASK as u8) != 0
655        })
656    }
657}
658impl W {
659    #[doc = r" Reset value of the register"]
660    #[inline]
661    pub fn reset_value() -> W {
662        W { bits: 0 }
663    }
664    #[doc = r" Writes raw bits to the register"]
665    #[inline]
666    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
667        self.bits = bits;
668        self
669    }
670    #[doc = "Bits 0:2 - Slave address"]
671    #[inline]
672    pub fn ad(&mut self) -> _ADW {
673        _ADW { w: self }
674    }
675    #[doc = "Bit 3 - Range address matching enable"]
676    #[inline]
677    pub fn rmen(&mut self) -> _RMENW {
678        _RMENW { w: self }
679    }
680    #[doc = "Bit 4 - Slave baud rate control"]
681    #[inline]
682    pub fn sbrc(&mut self) -> _SBRCW {
683        _SBRCW { w: self }
684    }
685    #[doc = "Bit 5 - High drive select"]
686    #[inline]
687    pub fn hdrs(&mut self) -> _HDRSW {
688        _HDRSW { w: self }
689    }
690    #[doc = "Bit 6 - Address extension"]
691    #[inline]
692    pub fn adext(&mut self) -> _ADEXTW {
693        _ADEXTW { w: self }
694    }
695    #[doc = "Bit 7 - General call address enable"]
696    #[inline]
697    pub fn gcaen(&mut self) -> _GCAENW {
698        _GCAENW { w: self }
699    }
700}
mk20d7/i2c1/c2/mod.rs

mk20d7/i2c1/c2/
mod.rs
