mk20d7/uart1/cfifo/
mod.rs1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u8,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u8,
8}
9impl super::CFIFO {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `RXUFE`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum RXUFER {
48 #[doc = "RXUF flag does not generate an interrupt to the host."]
49 _0,
50 #[doc = "RXUF flag generates an interrupt to the host."]
51 _1,
52}
53impl RXUFER {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 RXUFER::_0 => false,
69 RXUFER::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> RXUFER {
76 match value {
77 false => RXUFER::_0,
78 true => RXUFER::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == RXUFER::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == RXUFER::_1
90 }
91}
92#[doc = "Possible values of the field `TXOFE`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum TXOFER {
95 #[doc = "TXOF flag does not generate an interrupt to the host."]
96 _0,
97 #[doc = "TXOF flag generates an interrupt to the host."]
98 _1,
99}
100impl TXOFER {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 TXOFER::_0 => false,
116 TXOFER::_1 => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> TXOFER {
123 match value {
124 false => TXOFER::_0,
125 true => TXOFER::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline]
130 pub fn is_0(&self) -> bool {
131 *self == TXOFER::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline]
135 pub fn is_1(&self) -> bool {
136 *self == TXOFER::_1
137 }
138}
139#[doc = "Values that can be written to the field `RXUFE`"]
140pub enum RXUFEW {
141 #[doc = "RXUF flag does not generate an interrupt to the host."]
142 _0,
143 #[doc = "RXUF flag generates an interrupt to the host."]
144 _1,
145}
146impl RXUFEW {
147 #[allow(missing_docs)]
148 #[doc(hidden)]
149 #[inline]
150 pub fn _bits(&self) -> bool {
151 match *self {
152 RXUFEW::_0 => false,
153 RXUFEW::_1 => true,
154 }
155 }
156}
157#[doc = r" Proxy"]
158pub struct _RXUFEW<'a> {
159 w: &'a mut W,
160}
161impl<'a> _RXUFEW<'a> {
162 #[doc = r" Writes `variant` to the field"]
163 #[inline]
164 pub fn variant(self, variant: RXUFEW) -> &'a mut W {
165 {
166 self.bit(variant._bits())
167 }
168 }
169 #[doc = "RXUF flag does not generate an interrupt to the host."]
170 #[inline]
171 pub fn _0(self) -> &'a mut W {
172 self.variant(RXUFEW::_0)
173 }
174 #[doc = "RXUF flag generates an interrupt to the host."]
175 #[inline]
176 pub fn _1(self) -> &'a mut W {
177 self.variant(RXUFEW::_1)
178 }
179 #[doc = r" Sets the field bit"]
180 pub fn set_bit(self) -> &'a mut W {
181 self.bit(true)
182 }
183 #[doc = r" Clears the field bit"]
184 pub fn clear_bit(self) -> &'a mut W {
185 self.bit(false)
186 }
187 #[doc = r" Writes raw bits to the field"]
188 #[inline]
189 pub fn bit(self, value: bool) -> &'a mut W {
190 const MASK: bool = true;
191 const OFFSET: u8 = 0;
192 self.w.bits &= !((MASK as u8) << OFFSET);
193 self.w.bits |= ((value & MASK) as u8) << OFFSET;
194 self.w
195 }
196}
197#[doc = "Values that can be written to the field `TXOFE`"]
198pub enum TXOFEW {
199 #[doc = "TXOF flag does not generate an interrupt to the host."]
200 _0,
201 #[doc = "TXOF flag generates an interrupt to the host."]
202 _1,
203}
204impl TXOFEW {
205 #[allow(missing_docs)]
206 #[doc(hidden)]
207 #[inline]
208 pub fn _bits(&self) -> bool {
209 match *self {
210 TXOFEW::_0 => false,
211 TXOFEW::_1 => true,
212 }
213 }
214}
215#[doc = r" Proxy"]
216pub struct _TXOFEW<'a> {
217 w: &'a mut W,
218}
219impl<'a> _TXOFEW<'a> {
220 #[doc = r" Writes `variant` to the field"]
221 #[inline]
222 pub fn variant(self, variant: TXOFEW) -> &'a mut W {
223 {
224 self.bit(variant._bits())
225 }
226 }
227 #[doc = "TXOF flag does not generate an interrupt to the host."]
228 #[inline]
229 pub fn _0(self) -> &'a mut W {
230 self.variant(TXOFEW::_0)
231 }
232 #[doc = "TXOF flag generates an interrupt to the host."]
233 #[inline]
234 pub fn _1(self) -> &'a mut W {
235 self.variant(TXOFEW::_1)
236 }
237 #[doc = r" Sets the field bit"]
238 pub fn set_bit(self) -> &'a mut W {
239 self.bit(true)
240 }
241 #[doc = r" Clears the field bit"]
242 pub fn clear_bit(self) -> &'a mut W {
243 self.bit(false)
244 }
245 #[doc = r" Writes raw bits to the field"]
246 #[inline]
247 pub fn bit(self, value: bool) -> &'a mut W {
248 const MASK: bool = true;
249 const OFFSET: u8 = 1;
250 self.w.bits &= !((MASK as u8) << OFFSET);
251 self.w.bits |= ((value & MASK) as u8) << OFFSET;
252 self.w
253 }
254}
255#[doc = "Values that can be written to the field `RXFLUSH`"]
256pub enum RXFLUSHW {
257 #[doc = "No flush operation occurs."]
258 _0,
259 #[doc = "All data in the receive FIFO/buffer is cleared out."]
260 _1,
261}
262impl RXFLUSHW {
263 #[allow(missing_docs)]
264 #[doc(hidden)]
265 #[inline]
266 pub fn _bits(&self) -> bool {
267 match *self {
268 RXFLUSHW::_0 => false,
269 RXFLUSHW::_1 => true,
270 }
271 }
272}
273#[doc = r" Proxy"]
274pub struct _RXFLUSHW<'a> {
275 w: &'a mut W,
276}
277impl<'a> _RXFLUSHW<'a> {
278 #[doc = r" Writes `variant` to the field"]
279 #[inline]
280 pub fn variant(self, variant: RXFLUSHW) -> &'a mut W {
281 {
282 self.bit(variant._bits())
283 }
284 }
285 #[doc = "No flush operation occurs."]
286 #[inline]
287 pub fn _0(self) -> &'a mut W {
288 self.variant(RXFLUSHW::_0)
289 }
290 #[doc = "All data in the receive FIFO/buffer is cleared out."]
291 #[inline]
292 pub fn _1(self) -> &'a mut W {
293 self.variant(RXFLUSHW::_1)
294 }
295 #[doc = r" Sets the field bit"]
296 pub fn set_bit(self) -> &'a mut W {
297 self.bit(true)
298 }
299 #[doc = r" Clears the field bit"]
300 pub fn clear_bit(self) -> &'a mut W {
301 self.bit(false)
302 }
303 #[doc = r" Writes raw bits to the field"]
304 #[inline]
305 pub fn bit(self, value: bool) -> &'a mut W {
306 const MASK: bool = true;
307 const OFFSET: u8 = 6;
308 self.w.bits &= !((MASK as u8) << OFFSET);
309 self.w.bits |= ((value & MASK) as u8) << OFFSET;
310 self.w
311 }
312}
313#[doc = "Values that can be written to the field `TXFLUSH`"]
314pub enum TXFLUSHW {
315 #[doc = "No flush operation occurs."]
316 _0,
317 #[doc = "All data in the transmit FIFO/Buffer is cleared out."]
318 _1,
319}
320impl TXFLUSHW {
321 #[allow(missing_docs)]
322 #[doc(hidden)]
323 #[inline]
324 pub fn _bits(&self) -> bool {
325 match *self {
326 TXFLUSHW::_0 => false,
327 TXFLUSHW::_1 => true,
328 }
329 }
330}
331#[doc = r" Proxy"]
332pub struct _TXFLUSHW<'a> {
333 w: &'a mut W,
334}
335impl<'a> _TXFLUSHW<'a> {
336 #[doc = r" Writes `variant` to the field"]
337 #[inline]
338 pub fn variant(self, variant: TXFLUSHW) -> &'a mut W {
339 {
340 self.bit(variant._bits())
341 }
342 }
343 #[doc = "No flush operation occurs."]
344 #[inline]
345 pub fn _0(self) -> &'a mut W {
346 self.variant(TXFLUSHW::_0)
347 }
348 #[doc = "All data in the transmit FIFO/Buffer is cleared out."]
349 #[inline]
350 pub fn _1(self) -> &'a mut W {
351 self.variant(TXFLUSHW::_1)
352 }
353 #[doc = r" Sets the field bit"]
354 pub fn set_bit(self) -> &'a mut W {
355 self.bit(true)
356 }
357 #[doc = r" Clears the field bit"]
358 pub fn clear_bit(self) -> &'a mut W {
359 self.bit(false)
360 }
361 #[doc = r" Writes raw bits to the field"]
362 #[inline]
363 pub fn bit(self, value: bool) -> &'a mut W {
364 const MASK: bool = true;
365 const OFFSET: u8 = 7;
366 self.w.bits &= !((MASK as u8) << OFFSET);
367 self.w.bits |= ((value & MASK) as u8) << OFFSET;
368 self.w
369 }
370}
371impl R {
372 #[doc = r" Value of the register as raw bits"]
373 #[inline]
374 pub fn bits(&self) -> u8 {
375 self.bits
376 }
377 #[doc = "Bit 0 - Receive FIFO Underflow Interrupt Enable"]
378 #[inline]
379 pub fn rxufe(&self) -> RXUFER {
380 RXUFER::_from({
381 const MASK: bool = true;
382 const OFFSET: u8 = 0;
383 ((self.bits >> OFFSET) & MASK as u8) != 0
384 })
385 }
386 #[doc = "Bit 1 - Transmit FIFO Overflow Interrupt Enable"]
387 #[inline]
388 pub fn txofe(&self) -> TXOFER {
389 TXOFER::_from({
390 const MASK: bool = true;
391 const OFFSET: u8 = 1;
392 ((self.bits >> OFFSET) & MASK as u8) != 0
393 })
394 }
395}
396impl W {
397 #[doc = r" Reset value of the register"]
398 #[inline]
399 pub fn reset_value() -> W {
400 W { bits: 0 }
401 }
402 #[doc = r" Writes raw bits to the register"]
403 #[inline]
404 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
405 self.bits = bits;
406 self
407 }
408 #[doc = "Bit 0 - Receive FIFO Underflow Interrupt Enable"]
409 #[inline]
410 pub fn rxufe(&mut self) -> _RXUFEW {
411 _RXUFEW { w: self }
412 }
413 #[doc = "Bit 1 - Transmit FIFO Overflow Interrupt Enable"]
414 #[inline]
415 pub fn txofe(&mut self) -> _TXOFEW {
416 _TXOFEW { w: self }
417 }
418 #[doc = "Bit 6 - Receive FIFO/Buffer Flush"]
419 #[inline]
420 pub fn rxflush(&mut self) -> _RXFLUSHW {
421 _RXFLUSHW { w: self }
422 }
423 #[doc = "Bit 7 - Transmit FIFO/Buffer Flush"]
424 #[inline]
425 pub fn txflush(&mut self) -> _TXFLUSHW {
426 _TXFLUSHW { w: self }
427 }
428}