1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CHS {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `ERR`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum ERRR {
48 #[doc = "Sequence error not detected on PDB channel's corresponding pre-trigger."]
49 _0,
50 #[doc = "Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags."]
51 _1,
52 #[doc = r" Reserved"]
53 _Reserved(u8),
54}
55impl ERRR {
56 #[doc = r" Value of the field as raw bits"]
57 #[inline]
58 pub fn bits(&self) -> u8 {
59 match *self {
60 ERRR::_0 => 0,
61 ERRR::_1 => 1,
62 ERRR::_Reserved(bits) => bits,
63 }
64 }
65 #[allow(missing_docs)]
66 #[doc(hidden)]
67 #[inline]
68 pub fn _from(value: u8) -> ERRR {
69 match value {
70 0 => ERRR::_0,
71 1 => ERRR::_1,
72 i => ERRR::_Reserved(i),
73 }
74 }
75 #[doc = "Checks if the value of the field is `_0`"]
76 #[inline]
77 pub fn is_0(&self) -> bool {
78 *self == ERRR::_0
79 }
80 #[doc = "Checks if the value of the field is `_1`"]
81 #[inline]
82 pub fn is_1(&self) -> bool {
83 *self == ERRR::_1
84 }
85}
86#[doc = r" Value of the field"]
87pub struct CFR {
88 bits: u8,
89}
90impl CFR {
91 #[doc = r" Value of the field as raw bits"]
92 #[inline]
93 pub fn bits(&self) -> u8 {
94 self.bits
95 }
96}
97#[doc = "Values that can be written to the field `ERR`"]
98pub enum ERRW {
99 #[doc = "Sequence error not detected on PDB channel's corresponding pre-trigger."]
100 _0,
101 #[doc = "Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags."]
102 _1,
103}
104impl ERRW {
105 #[allow(missing_docs)]
106 #[doc(hidden)]
107 #[inline]
108 pub fn _bits(&self) -> u8 {
109 match *self {
110 ERRW::_0 => 0,
111 ERRW::_1 => 1,
112 }
113 }
114}
115#[doc = r" Proxy"]
116pub struct _ERRW<'a> {
117 w: &'a mut W,
118}
119impl<'a> _ERRW<'a> {
120 #[doc = r" Writes `variant` to the field"]
121 #[inline]
122 pub fn variant(self, variant: ERRW) -> &'a mut W {
123 unsafe { self.bits(variant._bits()) }
124 }
125 #[doc = "Sequence error not detected on PDB channel's corresponding pre-trigger."]
126 #[inline]
127 pub fn _0(self) -> &'a mut W {
128 self.variant(ERRW::_0)
129 }
130 #[doc = "Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags."]
131 #[inline]
132 pub fn _1(self) -> &'a mut W {
133 self.variant(ERRW::_1)
134 }
135 #[doc = r" Writes raw bits to the field"]
136 #[inline]
137 pub unsafe fn bits(self, value: u8) -> &'a mut W {
138 const MASK: u8 = 255;
139 const OFFSET: u8 = 0;
140 self.w.bits &= !((MASK as u32) << OFFSET);
141 self.w.bits |= ((value & MASK) as u32) << OFFSET;
142 self.w
143 }
144}
145#[doc = r" Proxy"]
146pub struct _CFW<'a> {
147 w: &'a mut W,
148}
149impl<'a> _CFW<'a> {
150 #[doc = r" Writes raw bits to the field"]
151 #[inline]
152 pub unsafe fn bits(self, value: u8) -> &'a mut W {
153 const MASK: u8 = 255;
154 const OFFSET: u8 = 16;
155 self.w.bits &= !((MASK as u32) << OFFSET);
156 self.w.bits |= ((value & MASK) as u32) << OFFSET;
157 self.w
158 }
159}
160impl R {
161 #[doc = r" Value of the register as raw bits"]
162 #[inline]
163 pub fn bits(&self) -> u32 {
164 self.bits
165 }
166 #[doc = "Bits 0:7 - PDB Channel Sequence Error Flags"]
167 #[inline]
168 pub fn err(&self) -> ERRR {
169 ERRR::_from({
170 const MASK: u8 = 255;
171 const OFFSET: u8 = 0;
172 ((self.bits >> OFFSET) & MASK as u32) as u8
173 })
174 }
175 #[doc = "Bits 16:23 - PDB Channel Flags"]
176 #[inline]
177 pub fn cf(&self) -> CFR {
178 let bits = {
179 const MASK: u8 = 255;
180 const OFFSET: u8 = 16;
181 ((self.bits >> OFFSET) & MASK as u32) as u8
182 };
183 CFR { bits }
184 }
185}
186impl W {
187 #[doc = r" Reset value of the register"]
188 #[inline]
189 pub fn reset_value() -> W {
190 W { bits: 0 }
191 }
192 #[doc = r" Writes raw bits to the register"]
193 #[inline]
194 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
195 self.bits = bits;
196 self
197 }
198 #[doc = "Bits 0:7 - PDB Channel Sequence Error Flags"]
199 #[inline]
200 pub fn err(&mut self) -> _ERRW {
201 _ERRW { w: self }
202 }
203 #[doc = "Bits 16:23 - PDB Channel Flags"]
204 #[inline]
205 pub fn cf(&mut self) -> _CFW {
206 _CFW { w: self }
207 }
208}