mk20d7/sim/scgc5/
mod.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::SCGC5 {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = "Possible values of the field `LPTIMER`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum LPTIMERR {
48    #[doc = "Access disabled"]
49    _0,
50    #[doc = "Access enabled"]
51    _1,
52}
53impl LPTIMERR {
54    #[doc = r" Returns `true` if the bit is clear (0)"]
55    #[inline]
56    pub fn bit_is_clear(&self) -> bool {
57        !self.bit()
58    }
59    #[doc = r" Returns `true` if the bit is set (1)"]
60    #[inline]
61    pub fn bit_is_set(&self) -> bool {
62        self.bit()
63    }
64    #[doc = r" Value of the field as raw bits"]
65    #[inline]
66    pub fn bit(&self) -> bool {
67        match *self {
68            LPTIMERR::_0 => false,
69            LPTIMERR::_1 => true,
70        }
71    }
72    #[allow(missing_docs)]
73    #[doc(hidden)]
74    #[inline]
75    pub fn _from(value: bool) -> LPTIMERR {
76        match value {
77            false => LPTIMERR::_0,
78            true => LPTIMERR::_1,
79        }
80    }
81    #[doc = "Checks if the value of the field is `_0`"]
82    #[inline]
83    pub fn is_0(&self) -> bool {
84        *self == LPTIMERR::_0
85    }
86    #[doc = "Checks if the value of the field is `_1`"]
87    #[inline]
88    pub fn is_1(&self) -> bool {
89        *self == LPTIMERR::_1
90    }
91}
92#[doc = "Possible values of the field `TSI`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum TSIR {
95    #[doc = "Clock disabled"]
96    _0,
97    #[doc = "Clock enabled"]
98    _1,
99}
100impl TSIR {
101    #[doc = r" Returns `true` if the bit is clear (0)"]
102    #[inline]
103    pub fn bit_is_clear(&self) -> bool {
104        !self.bit()
105    }
106    #[doc = r" Returns `true` if the bit is set (1)"]
107    #[inline]
108    pub fn bit_is_set(&self) -> bool {
109        self.bit()
110    }
111    #[doc = r" Value of the field as raw bits"]
112    #[inline]
113    pub fn bit(&self) -> bool {
114        match *self {
115            TSIR::_0 => false,
116            TSIR::_1 => true,
117        }
118    }
119    #[allow(missing_docs)]
120    #[doc(hidden)]
121    #[inline]
122    pub fn _from(value: bool) -> TSIR {
123        match value {
124            false => TSIR::_0,
125            true => TSIR::_1,
126        }
127    }
128    #[doc = "Checks if the value of the field is `_0`"]
129    #[inline]
130    pub fn is_0(&self) -> bool {
131        *self == TSIR::_0
132    }
133    #[doc = "Checks if the value of the field is `_1`"]
134    #[inline]
135    pub fn is_1(&self) -> bool {
136        *self == TSIR::_1
137    }
138}
139#[doc = "Possible values of the field `PORTA`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum PORTAR {
142    #[doc = "Clock disabled"]
143    _0,
144    #[doc = "Clock enabled"]
145    _1,
146}
147impl PORTAR {
148    #[doc = r" Returns `true` if the bit is clear (0)"]
149    #[inline]
150    pub fn bit_is_clear(&self) -> bool {
151        !self.bit()
152    }
153    #[doc = r" Returns `true` if the bit is set (1)"]
154    #[inline]
155    pub fn bit_is_set(&self) -> bool {
156        self.bit()
157    }
158    #[doc = r" Value of the field as raw bits"]
159    #[inline]
160    pub fn bit(&self) -> bool {
161        match *self {
162            PORTAR::_0 => false,
163            PORTAR::_1 => true,
164        }
165    }
166    #[allow(missing_docs)]
167    #[doc(hidden)]
168    #[inline]
169    pub fn _from(value: bool) -> PORTAR {
170        match value {
171            false => PORTAR::_0,
172            true => PORTAR::_1,
173        }
174    }
175    #[doc = "Checks if the value of the field is `_0`"]
176    #[inline]
177    pub fn is_0(&self) -> bool {
178        *self == PORTAR::_0
179    }
180    #[doc = "Checks if the value of the field is `_1`"]
181    #[inline]
182    pub fn is_1(&self) -> bool {
183        *self == PORTAR::_1
184    }
185}
186#[doc = "Possible values of the field `PORTB`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum PORTBR {
189    #[doc = "Clock disabled"]
190    _0,
191    #[doc = "Clock enabled"]
192    _1,
193}
194impl PORTBR {
195    #[doc = r" Returns `true` if the bit is clear (0)"]
196    #[inline]
197    pub fn bit_is_clear(&self) -> bool {
198        !self.bit()
199    }
200    #[doc = r" Returns `true` if the bit is set (1)"]
201    #[inline]
202    pub fn bit_is_set(&self) -> bool {
203        self.bit()
204    }
205    #[doc = r" Value of the field as raw bits"]
206    #[inline]
207    pub fn bit(&self) -> bool {
208        match *self {
209            PORTBR::_0 => false,
210            PORTBR::_1 => true,
211        }
212    }
213    #[allow(missing_docs)]
214    #[doc(hidden)]
215    #[inline]
216    pub fn _from(value: bool) -> PORTBR {
217        match value {
218            false => PORTBR::_0,
219            true => PORTBR::_1,
220        }
221    }
222    #[doc = "Checks if the value of the field is `_0`"]
223    #[inline]
224    pub fn is_0(&self) -> bool {
225        *self == PORTBR::_0
226    }
227    #[doc = "Checks if the value of the field is `_1`"]
228    #[inline]
229    pub fn is_1(&self) -> bool {
230        *self == PORTBR::_1
231    }
232}
233#[doc = "Possible values of the field `PORTC`"]
234#[derive(Clone, Copy, Debug, PartialEq)]
235pub enum PORTCR {
236    #[doc = "Clock disabled"]
237    _0,
238    #[doc = "Clock enabled"]
239    _1,
240}
241impl PORTCR {
242    #[doc = r" Returns `true` if the bit is clear (0)"]
243    #[inline]
244    pub fn bit_is_clear(&self) -> bool {
245        !self.bit()
246    }
247    #[doc = r" Returns `true` if the bit is set (1)"]
248    #[inline]
249    pub fn bit_is_set(&self) -> bool {
250        self.bit()
251    }
252    #[doc = r" Value of the field as raw bits"]
253    #[inline]
254    pub fn bit(&self) -> bool {
255        match *self {
256            PORTCR::_0 => false,
257            PORTCR::_1 => true,
258        }
259    }
260    #[allow(missing_docs)]
261    #[doc(hidden)]
262    #[inline]
263    pub fn _from(value: bool) -> PORTCR {
264        match value {
265            false => PORTCR::_0,
266            true => PORTCR::_1,
267        }
268    }
269    #[doc = "Checks if the value of the field is `_0`"]
270    #[inline]
271    pub fn is_0(&self) -> bool {
272        *self == PORTCR::_0
273    }
274    #[doc = "Checks if the value of the field is `_1`"]
275    #[inline]
276    pub fn is_1(&self) -> bool {
277        *self == PORTCR::_1
278    }
279}
280#[doc = "Possible values of the field `PORTD`"]
281#[derive(Clone, Copy, Debug, PartialEq)]
282pub enum PORTDR {
283    #[doc = "Clock disabled"]
284    _0,
285    #[doc = "Clock enabled"]
286    _1,
287}
288impl PORTDR {
289    #[doc = r" Returns `true` if the bit is clear (0)"]
290    #[inline]
291    pub fn bit_is_clear(&self) -> bool {
292        !self.bit()
293    }
294    #[doc = r" Returns `true` if the bit is set (1)"]
295    #[inline]
296    pub fn bit_is_set(&self) -> bool {
297        self.bit()
298    }
299    #[doc = r" Value of the field as raw bits"]
300    #[inline]
301    pub fn bit(&self) -> bool {
302        match *self {
303            PORTDR::_0 => false,
304            PORTDR::_1 => true,
305        }
306    }
307    #[allow(missing_docs)]
308    #[doc(hidden)]
309    #[inline]
310    pub fn _from(value: bool) -> PORTDR {
311        match value {
312            false => PORTDR::_0,
313            true => PORTDR::_1,
314        }
315    }
316    #[doc = "Checks if the value of the field is `_0`"]
317    #[inline]
318    pub fn is_0(&self) -> bool {
319        *self == PORTDR::_0
320    }
321    #[doc = "Checks if the value of the field is `_1`"]
322    #[inline]
323    pub fn is_1(&self) -> bool {
324        *self == PORTDR::_1
325    }
326}
327#[doc = "Possible values of the field `PORTE`"]
328#[derive(Clone, Copy, Debug, PartialEq)]
329pub enum PORTER {
330    #[doc = "Clock disabled"]
331    _0,
332    #[doc = "Clock enabled"]
333    _1,
334}
335impl PORTER {
336    #[doc = r" Returns `true` if the bit is clear (0)"]
337    #[inline]
338    pub fn bit_is_clear(&self) -> bool {
339        !self.bit()
340    }
341    #[doc = r" Returns `true` if the bit is set (1)"]
342    #[inline]
343    pub fn bit_is_set(&self) -> bool {
344        self.bit()
345    }
346    #[doc = r" Value of the field as raw bits"]
347    #[inline]
348    pub fn bit(&self) -> bool {
349        match *self {
350            PORTER::_0 => false,
351            PORTER::_1 => true,
352        }
353    }
354    #[allow(missing_docs)]
355    #[doc(hidden)]
356    #[inline]
357    pub fn _from(value: bool) -> PORTER {
358        match value {
359            false => PORTER::_0,
360            true => PORTER::_1,
361        }
362    }
363    #[doc = "Checks if the value of the field is `_0`"]
364    #[inline]
365    pub fn is_0(&self) -> bool {
366        *self == PORTER::_0
367    }
368    #[doc = "Checks if the value of the field is `_1`"]
369    #[inline]
370    pub fn is_1(&self) -> bool {
371        *self == PORTER::_1
372    }
373}
374#[doc = "Values that can be written to the field `LPTIMER`"]
375pub enum LPTIMERW {
376    #[doc = "Access disabled"]
377    _0,
378    #[doc = "Access enabled"]
379    _1,
380}
381impl LPTIMERW {
382    #[allow(missing_docs)]
383    #[doc(hidden)]
384    #[inline]
385    pub fn _bits(&self) -> bool {
386        match *self {
387            LPTIMERW::_0 => false,
388            LPTIMERW::_1 => true,
389        }
390    }
391}
392#[doc = r" Proxy"]
393pub struct _LPTIMERW<'a> {
394    w: &'a mut W,
395}
396impl<'a> _LPTIMERW<'a> {
397    #[doc = r" Writes `variant` to the field"]
398    #[inline]
399    pub fn variant(self, variant: LPTIMERW) -> &'a mut W {
400        {
401            self.bit(variant._bits())
402        }
403    }
404    #[doc = "Access disabled"]
405    #[inline]
406    pub fn _0(self) -> &'a mut W {
407        self.variant(LPTIMERW::_0)
408    }
409    #[doc = "Access enabled"]
410    #[inline]
411    pub fn _1(self) -> &'a mut W {
412        self.variant(LPTIMERW::_1)
413    }
414    #[doc = r" Sets the field bit"]
415    pub fn set_bit(self) -> &'a mut W {
416        self.bit(true)
417    }
418    #[doc = r" Clears the field bit"]
419    pub fn clear_bit(self) -> &'a mut W {
420        self.bit(false)
421    }
422    #[doc = r" Writes raw bits to the field"]
423    #[inline]
424    pub fn bit(self, value: bool) -> &'a mut W {
425        const MASK: bool = true;
426        const OFFSET: u8 = 0;
427        self.w.bits &= !((MASK as u32) << OFFSET);
428        self.w.bits |= ((value & MASK) as u32) << OFFSET;
429        self.w
430    }
431}
432#[doc = "Values that can be written to the field `TSI`"]
433pub enum TSIW {
434    #[doc = "Clock disabled"]
435    _0,
436    #[doc = "Clock enabled"]
437    _1,
438}
439impl TSIW {
440    #[allow(missing_docs)]
441    #[doc(hidden)]
442    #[inline]
443    pub fn _bits(&self) -> bool {
444        match *self {
445            TSIW::_0 => false,
446            TSIW::_1 => true,
447        }
448    }
449}
450#[doc = r" Proxy"]
451pub struct _TSIW<'a> {
452    w: &'a mut W,
453}
454impl<'a> _TSIW<'a> {
455    #[doc = r" Writes `variant` to the field"]
456    #[inline]
457    pub fn variant(self, variant: TSIW) -> &'a mut W {
458        {
459            self.bit(variant._bits())
460        }
461    }
462    #[doc = "Clock disabled"]
463    #[inline]
464    pub fn _0(self) -> &'a mut W {
465        self.variant(TSIW::_0)
466    }
467    #[doc = "Clock enabled"]
468    #[inline]
469    pub fn _1(self) -> &'a mut W {
470        self.variant(TSIW::_1)
471    }
472    #[doc = r" Sets the field bit"]
473    pub fn set_bit(self) -> &'a mut W {
474        self.bit(true)
475    }
476    #[doc = r" Clears the field bit"]
477    pub fn clear_bit(self) -> &'a mut W {
478        self.bit(false)
479    }
480    #[doc = r" Writes raw bits to the field"]
481    #[inline]
482    pub fn bit(self, value: bool) -> &'a mut W {
483        const MASK: bool = true;
484        const OFFSET: u8 = 5;
485        self.w.bits &= !((MASK as u32) << OFFSET);
486        self.w.bits |= ((value & MASK) as u32) << OFFSET;
487        self.w
488    }
489}
490#[doc = "Values that can be written to the field `PORTA`"]
491pub enum PORTAW {
492    #[doc = "Clock disabled"]
493    _0,
494    #[doc = "Clock enabled"]
495    _1,
496}
497impl PORTAW {
498    #[allow(missing_docs)]
499    #[doc(hidden)]
500    #[inline]
501    pub fn _bits(&self) -> bool {
502        match *self {
503            PORTAW::_0 => false,
504            PORTAW::_1 => true,
505        }
506    }
507}
508#[doc = r" Proxy"]
509pub struct _PORTAW<'a> {
510    w: &'a mut W,
511}
512impl<'a> _PORTAW<'a> {
513    #[doc = r" Writes `variant` to the field"]
514    #[inline]
515    pub fn variant(self, variant: PORTAW) -> &'a mut W {
516        {
517            self.bit(variant._bits())
518        }
519    }
520    #[doc = "Clock disabled"]
521    #[inline]
522    pub fn _0(self) -> &'a mut W {
523        self.variant(PORTAW::_0)
524    }
525    #[doc = "Clock enabled"]
526    #[inline]
527    pub fn _1(self) -> &'a mut W {
528        self.variant(PORTAW::_1)
529    }
530    #[doc = r" Sets the field bit"]
531    pub fn set_bit(self) -> &'a mut W {
532        self.bit(true)
533    }
534    #[doc = r" Clears the field bit"]
535    pub fn clear_bit(self) -> &'a mut W {
536        self.bit(false)
537    }
538    #[doc = r" Writes raw bits to the field"]
539    #[inline]
540    pub fn bit(self, value: bool) -> &'a mut W {
541        const MASK: bool = true;
542        const OFFSET: u8 = 9;
543        self.w.bits &= !((MASK as u32) << OFFSET);
544        self.w.bits |= ((value & MASK) as u32) << OFFSET;
545        self.w
546    }
547}
548#[doc = "Values that can be written to the field `PORTB`"]
549pub enum PORTBW {
550    #[doc = "Clock disabled"]
551    _0,
552    #[doc = "Clock enabled"]
553    _1,
554}
555impl PORTBW {
556    #[allow(missing_docs)]
557    #[doc(hidden)]
558    #[inline]
559    pub fn _bits(&self) -> bool {
560        match *self {
561            PORTBW::_0 => false,
562            PORTBW::_1 => true,
563        }
564    }
565}
566#[doc = r" Proxy"]
567pub struct _PORTBW<'a> {
568    w: &'a mut W,
569}
570impl<'a> _PORTBW<'a> {
571    #[doc = r" Writes `variant` to the field"]
572    #[inline]
573    pub fn variant(self, variant: PORTBW) -> &'a mut W {
574        {
575            self.bit(variant._bits())
576        }
577    }
578    #[doc = "Clock disabled"]
579    #[inline]
580    pub fn _0(self) -> &'a mut W {
581        self.variant(PORTBW::_0)
582    }
583    #[doc = "Clock enabled"]
584    #[inline]
585    pub fn _1(self) -> &'a mut W {
586        self.variant(PORTBW::_1)
587    }
588    #[doc = r" Sets the field bit"]
589    pub fn set_bit(self) -> &'a mut W {
590        self.bit(true)
591    }
592    #[doc = r" Clears the field bit"]
593    pub fn clear_bit(self) -> &'a mut W {
594        self.bit(false)
595    }
596    #[doc = r" Writes raw bits to the field"]
597    #[inline]
598    pub fn bit(self, value: bool) -> &'a mut W {
599        const MASK: bool = true;
600        const OFFSET: u8 = 10;
601        self.w.bits &= !((MASK as u32) << OFFSET);
602        self.w.bits |= ((value & MASK) as u32) << OFFSET;
603        self.w
604    }
605}
606#[doc = "Values that can be written to the field `PORTC`"]
607pub enum PORTCW {
608    #[doc = "Clock disabled"]
609    _0,
610    #[doc = "Clock enabled"]
611    _1,
612}
613impl PORTCW {
614    #[allow(missing_docs)]
615    #[doc(hidden)]
616    #[inline]
617    pub fn _bits(&self) -> bool {
618        match *self {
619            PORTCW::_0 => false,
620            PORTCW::_1 => true,
621        }
622    }
623}
624#[doc = r" Proxy"]
625pub struct _PORTCW<'a> {
626    w: &'a mut W,
627}
628impl<'a> _PORTCW<'a> {
629    #[doc = r" Writes `variant` to the field"]
630    #[inline]
631    pub fn variant(self, variant: PORTCW) -> &'a mut W {
632        {
633            self.bit(variant._bits())
634        }
635    }
636    #[doc = "Clock disabled"]
637    #[inline]
638    pub fn _0(self) -> &'a mut W {
639        self.variant(PORTCW::_0)
640    }
641    #[doc = "Clock enabled"]
642    #[inline]
643    pub fn _1(self) -> &'a mut W {
644        self.variant(PORTCW::_1)
645    }
646    #[doc = r" Sets the field bit"]
647    pub fn set_bit(self) -> &'a mut W {
648        self.bit(true)
649    }
650    #[doc = r" Clears the field bit"]
651    pub fn clear_bit(self) -> &'a mut W {
652        self.bit(false)
653    }
654    #[doc = r" Writes raw bits to the field"]
655    #[inline]
656    pub fn bit(self, value: bool) -> &'a mut W {
657        const MASK: bool = true;
658        const OFFSET: u8 = 11;
659        self.w.bits &= !((MASK as u32) << OFFSET);
660        self.w.bits |= ((value & MASK) as u32) << OFFSET;
661        self.w
662    }
663}
664#[doc = "Values that can be written to the field `PORTD`"]
665pub enum PORTDW {
666    #[doc = "Clock disabled"]
667    _0,
668    #[doc = "Clock enabled"]
669    _1,
670}
671impl PORTDW {
672    #[allow(missing_docs)]
673    #[doc(hidden)]
674    #[inline]
675    pub fn _bits(&self) -> bool {
676        match *self {
677            PORTDW::_0 => false,
678            PORTDW::_1 => true,
679        }
680    }
681}
682#[doc = r" Proxy"]
683pub struct _PORTDW<'a> {
684    w: &'a mut W,
685}
686impl<'a> _PORTDW<'a> {
687    #[doc = r" Writes `variant` to the field"]
688    #[inline]
689    pub fn variant(self, variant: PORTDW) -> &'a mut W {
690        {
691            self.bit(variant._bits())
692        }
693    }
694    #[doc = "Clock disabled"]
695    #[inline]
696    pub fn _0(self) -> &'a mut W {
697        self.variant(PORTDW::_0)
698    }
699    #[doc = "Clock enabled"]
700    #[inline]
701    pub fn _1(self) -> &'a mut W {
702        self.variant(PORTDW::_1)
703    }
704    #[doc = r" Sets the field bit"]
705    pub fn set_bit(self) -> &'a mut W {
706        self.bit(true)
707    }
708    #[doc = r" Clears the field bit"]
709    pub fn clear_bit(self) -> &'a mut W {
710        self.bit(false)
711    }
712    #[doc = r" Writes raw bits to the field"]
713    #[inline]
714    pub fn bit(self, value: bool) -> &'a mut W {
715        const MASK: bool = true;
716        const OFFSET: u8 = 12;
717        self.w.bits &= !((MASK as u32) << OFFSET);
718        self.w.bits |= ((value & MASK) as u32) << OFFSET;
719        self.w
720    }
721}
722#[doc = "Values that can be written to the field `PORTE`"]
723pub enum PORTEW {
724    #[doc = "Clock disabled"]
725    _0,
726    #[doc = "Clock enabled"]
727    _1,
728}
729impl PORTEW {
730    #[allow(missing_docs)]
731    #[doc(hidden)]
732    #[inline]
733    pub fn _bits(&self) -> bool {
734        match *self {
735            PORTEW::_0 => false,
736            PORTEW::_1 => true,
737        }
738    }
739}
740#[doc = r" Proxy"]
741pub struct _PORTEW<'a> {
742    w: &'a mut W,
743}
744impl<'a> _PORTEW<'a> {
745    #[doc = r" Writes `variant` to the field"]
746    #[inline]
747    pub fn variant(self, variant: PORTEW) -> &'a mut W {
748        {
749            self.bit(variant._bits())
750        }
751    }
752    #[doc = "Clock disabled"]
753    #[inline]
754    pub fn _0(self) -> &'a mut W {
755        self.variant(PORTEW::_0)
756    }
757    #[doc = "Clock enabled"]
758    #[inline]
759    pub fn _1(self) -> &'a mut W {
760        self.variant(PORTEW::_1)
761    }
762    #[doc = r" Sets the field bit"]
763    pub fn set_bit(self) -> &'a mut W {
764        self.bit(true)
765    }
766    #[doc = r" Clears the field bit"]
767    pub fn clear_bit(self) -> &'a mut W {
768        self.bit(false)
769    }
770    #[doc = r" Writes raw bits to the field"]
771    #[inline]
772    pub fn bit(self, value: bool) -> &'a mut W {
773        const MASK: bool = true;
774        const OFFSET: u8 = 13;
775        self.w.bits &= !((MASK as u32) << OFFSET);
776        self.w.bits |= ((value & MASK) as u32) << OFFSET;
777        self.w
778    }
779}
780impl R {
781    #[doc = r" Value of the register as raw bits"]
782    #[inline]
783    pub fn bits(&self) -> u32 {
784        self.bits
785    }
786    #[doc = "Bit 0 - Low Power Timer Access Control"]
787    #[inline]
788    pub fn lptimer(&self) -> LPTIMERR {
789        LPTIMERR::_from({
790            const MASK: bool = true;
791            const OFFSET: u8 = 0;
792            ((self.bits >> OFFSET) & MASK as u32) != 0
793        })
794    }
795    #[doc = "Bit 5 - TSI Clock Gate Control"]
796    #[inline]
797    pub fn tsi(&self) -> TSIR {
798        TSIR::_from({
799            const MASK: bool = true;
800            const OFFSET: u8 = 5;
801            ((self.bits >> OFFSET) & MASK as u32) != 0
802        })
803    }
804    #[doc = "Bit 9 - Port A Clock Gate Control"]
805    #[inline]
806    pub fn porta(&self) -> PORTAR {
807        PORTAR::_from({
808            const MASK: bool = true;
809            const OFFSET: u8 = 9;
810            ((self.bits >> OFFSET) & MASK as u32) != 0
811        })
812    }
813    #[doc = "Bit 10 - Port B Clock Gate Control"]
814    #[inline]
815    pub fn portb(&self) -> PORTBR {
816        PORTBR::_from({
817            const MASK: bool = true;
818            const OFFSET: u8 = 10;
819            ((self.bits >> OFFSET) & MASK as u32) != 0
820        })
821    }
822    #[doc = "Bit 11 - Port C Clock Gate Control"]
823    #[inline]
824    pub fn portc(&self) -> PORTCR {
825        PORTCR::_from({
826            const MASK: bool = true;
827            const OFFSET: u8 = 11;
828            ((self.bits >> OFFSET) & MASK as u32) != 0
829        })
830    }
831    #[doc = "Bit 12 - Port D Clock Gate Control"]
832    #[inline]
833    pub fn portd(&self) -> PORTDR {
834        PORTDR::_from({
835            const MASK: bool = true;
836            const OFFSET: u8 = 12;
837            ((self.bits >> OFFSET) & MASK as u32) != 0
838        })
839    }
840    #[doc = "Bit 13 - Port E Clock Gate Control"]
841    #[inline]
842    pub fn porte(&self) -> PORTER {
843        PORTER::_from({
844            const MASK: bool = true;
845            const OFFSET: u8 = 13;
846            ((self.bits >> OFFSET) & MASK as u32) != 0
847        })
848    }
849}
850impl W {
851    #[doc = r" Reset value of the register"]
852    #[inline]
853    pub fn reset_value() -> W {
854        W { bits: 262530 }
855    }
856    #[doc = r" Writes raw bits to the register"]
857    #[inline]
858    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
859        self.bits = bits;
860        self
861    }
862    #[doc = "Bit 0 - Low Power Timer Access Control"]
863    #[inline]
864    pub fn lptimer(&mut self) -> _LPTIMERW {
865        _LPTIMERW { w: self }
866    }
867    #[doc = "Bit 5 - TSI Clock Gate Control"]
868    #[inline]
869    pub fn tsi(&mut self) -> _TSIW {
870        _TSIW { w: self }
871    }
872    #[doc = "Bit 9 - Port A Clock Gate Control"]
873    #[inline]
874    pub fn porta(&mut self) -> _PORTAW {
875        _PORTAW { w: self }
876    }
877    #[doc = "Bit 10 - Port B Clock Gate Control"]
878    #[inline]
879    pub fn portb(&mut self) -> _PORTBW {
880        _PORTBW { w: self }
881    }
882    #[doc = "Bit 11 - Port C Clock Gate Control"]
883    #[inline]
884    pub fn portc(&mut self) -> _PORTCW {
885        _PORTCW { w: self }
886    }
887    #[doc = "Bit 12 - Port D Clock Gate Control"]
888    #[inline]
889    pub fn portd(&mut self) -> _PORTDW {
890        _PORTDW { w: self }
891    }
892    #[doc = "Bit 13 - Port E Clock Gate Control"]
893    #[inline]
894    pub fn porte(&mut self) -> _PORTEW {
895        _PORTEW { w: self }
896    }
897}
mk20d7/sim/scgc5/mod.rs

mk20d7/sim/scgc5/
mod.rs
