1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::PSR {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `PCS`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum PCSR {
48 #[doc = "Prescaler/glitch filter clock 0 selected"]
49 _00,
50 #[doc = "Prescaler/glitch filter clock 1 selected"]
51 _01,
52 #[doc = "Prescaler/glitch filter clock 2 selected"]
53 _10,
54 #[doc = "Prescaler/glitch filter clock 3 selected"]
55 _11,
56}
57impl PCSR {
58 #[doc = r" Value of the field as raw bits"]
59 #[inline]
60 pub fn bits(&self) -> u8 {
61 match *self {
62 PCSR::_00 => 0,
63 PCSR::_01 => 1,
64 PCSR::_10 => 2,
65 PCSR::_11 => 3,
66 }
67 }
68 #[allow(missing_docs)]
69 #[doc(hidden)]
70 #[inline]
71 pub fn _from(value: u8) -> PCSR {
72 match value {
73 0 => PCSR::_00,
74 1 => PCSR::_01,
75 2 => PCSR::_10,
76 3 => PCSR::_11,
77 _ => unreachable!(),
78 }
79 }
80 #[doc = "Checks if the value of the field is `_00`"]
81 #[inline]
82 pub fn is_00(&self) -> bool {
83 *self == PCSR::_00
84 }
85 #[doc = "Checks if the value of the field is `_01`"]
86 #[inline]
87 pub fn is_01(&self) -> bool {
88 *self == PCSR::_01
89 }
90 #[doc = "Checks if the value of the field is `_10`"]
91 #[inline]
92 pub fn is_10(&self) -> bool {
93 *self == PCSR::_10
94 }
95 #[doc = "Checks if the value of the field is `_11`"]
96 #[inline]
97 pub fn is_11(&self) -> bool {
98 *self == PCSR::_11
99 }
100}
101#[doc = "Possible values of the field `PBYP`"]
102#[derive(Clone, Copy, Debug, PartialEq)]
103pub enum PBYPR {
104 #[doc = "Prescaler/Glitch Filter is enabled."]
105 _0,
106 #[doc = "Prescaler/Glitch Filter is bypassed."]
107 _1,
108}
109impl PBYPR {
110 #[doc = r" Returns `true` if the bit is clear (0)"]
111 #[inline]
112 pub fn bit_is_clear(&self) -> bool {
113 !self.bit()
114 }
115 #[doc = r" Returns `true` if the bit is set (1)"]
116 #[inline]
117 pub fn bit_is_set(&self) -> bool {
118 self.bit()
119 }
120 #[doc = r" Value of the field as raw bits"]
121 #[inline]
122 pub fn bit(&self) -> bool {
123 match *self {
124 PBYPR::_0 => false,
125 PBYPR::_1 => true,
126 }
127 }
128 #[allow(missing_docs)]
129 #[doc(hidden)]
130 #[inline]
131 pub fn _from(value: bool) -> PBYPR {
132 match value {
133 false => PBYPR::_0,
134 true => PBYPR::_1,
135 }
136 }
137 #[doc = "Checks if the value of the field is `_0`"]
138 #[inline]
139 pub fn is_0(&self) -> bool {
140 *self == PBYPR::_0
141 }
142 #[doc = "Checks if the value of the field is `_1`"]
143 #[inline]
144 pub fn is_1(&self) -> bool {
145 *self == PBYPR::_1
146 }
147}
148#[doc = "Possible values of the field `PRESCALE`"]
149#[derive(Clone, Copy, Debug, PartialEq)]
150pub enum PRESCALER {
151 #[doc = "Prescaler divides the prescaler clock by 2; Glitch Filter does not support this configuration."]
152 _0000,
153 #[doc = "Prescaler divides the prescaler clock by 4; Glitch Filter recognizes change on input pin after 2 rising clock edges."]
154 _0001,
155 #[doc = "Prescaler divides the prescaler clock by 8; Glitch Filter recognizes change on input pin after 4 rising clock edges."]
156 _0010,
157 #[doc = "Prescaler divides the prescaler clock by 16; Glitch Filter recognizes change on input pin after 8 rising clock edges."]
158 _0011,
159 #[doc = "Prescaler divides the prescaler clock by 32; Glitch Filter recognizes change on input pin after 16 rising clock edges."]
160 _0100,
161 #[doc = "Prescaler divides the prescaler clock by 64; Glitch Filter recognizes change on input pin after 32 rising clock edges."]
162 _0101,
163 #[doc = "Prescaler divides the prescaler clock by 128; Glitch Filter recognizes change on input pin after 64 rising clock edges."]
164 _0110,
165 #[doc = "Prescaler divides the prescaler clock by 256; Glitch Filter recognizes change on input pin after 128 rising clock edges."]
166 _0111,
167 #[doc = "Prescaler divides the prescaler clock by 512; Glitch Filter recognizes change on input pin after 256 rising clock edges."]
168 _1000,
169 #[doc = "Prescaler divides the prescaler clock by 1024; Glitch Filter recognizes change on input pin after 512 rising clock edges."]
170 _1001,
171 #[doc = "Prescaler divides the prescaler clock by 2048; Glitch Filter recognizes change on input pin after 1024 rising clock edges."]
172 _1010,
173 #[doc = "Prescaler divides the prescaler clock by 4096; Glitch Filter recognizes change on input pin after 2048 rising clock edges."]
174 _1011,
175 #[doc = "Prescaler divides the prescaler clock by 8192; Glitch Filter recognizes change on input pin after 4096 rising clock edges."]
176 _1100,
177 #[doc = "Prescaler divides the prescaler clock by 16384; Glitch Filter recognizes change on input pin after 8192 rising clock edges."]
178 _1101,
179 #[doc = "Prescaler divides the prescaler clock by 32768; Glitch Filter recognizes change on input pin after 16384 rising clock edges."]
180 _1110,
181 #[doc = "Prescaler divides the prescaler clock by 65536; Glitch Filter recognizes change on input pin after 32768 rising clock edges."]
182 _1111,
183}
184impl PRESCALER {
185 #[doc = r" Value of the field as raw bits"]
186 #[inline]
187 pub fn bits(&self) -> u8 {
188 match *self {
189 PRESCALER::_0000 => 0,
190 PRESCALER::_0001 => 1,
191 PRESCALER::_0010 => 2,
192 PRESCALER::_0011 => 3,
193 PRESCALER::_0100 => 4,
194 PRESCALER::_0101 => 5,
195 PRESCALER::_0110 => 6,
196 PRESCALER::_0111 => 7,
197 PRESCALER::_1000 => 8,
198 PRESCALER::_1001 => 9,
199 PRESCALER::_1010 => 10,
200 PRESCALER::_1011 => 11,
201 PRESCALER::_1100 => 12,
202 PRESCALER::_1101 => 13,
203 PRESCALER::_1110 => 14,
204 PRESCALER::_1111 => 15,
205 }
206 }
207 #[allow(missing_docs)]
208 #[doc(hidden)]
209 #[inline]
210 pub fn _from(value: u8) -> PRESCALER {
211 match value {
212 0 => PRESCALER::_0000,
213 1 => PRESCALER::_0001,
214 2 => PRESCALER::_0010,
215 3 => PRESCALER::_0011,
216 4 => PRESCALER::_0100,
217 5 => PRESCALER::_0101,
218 6 => PRESCALER::_0110,
219 7 => PRESCALER::_0111,
220 8 => PRESCALER::_1000,
221 9 => PRESCALER::_1001,
222 10 => PRESCALER::_1010,
223 11 => PRESCALER::_1011,
224 12 => PRESCALER::_1100,
225 13 => PRESCALER::_1101,
226 14 => PRESCALER::_1110,
227 15 => PRESCALER::_1111,
228 _ => unreachable!(),
229 }
230 }
231 #[doc = "Checks if the value of the field is `_0000`"]
232 #[inline]
233 pub fn is_0000(&self) -> bool {
234 *self == PRESCALER::_0000
235 }
236 #[doc = "Checks if the value of the field is `_0001`"]
237 #[inline]
238 pub fn is_0001(&self) -> bool {
239 *self == PRESCALER::_0001
240 }
241 #[doc = "Checks if the value of the field is `_0010`"]
242 #[inline]
243 pub fn is_0010(&self) -> bool {
244 *self == PRESCALER::_0010
245 }
246 #[doc = "Checks if the value of the field is `_0011`"]
247 #[inline]
248 pub fn is_0011(&self) -> bool {
249 *self == PRESCALER::_0011
250 }
251 #[doc = "Checks if the value of the field is `_0100`"]
252 #[inline]
253 pub fn is_0100(&self) -> bool {
254 *self == PRESCALER::_0100
255 }
256 #[doc = "Checks if the value of the field is `_0101`"]
257 #[inline]
258 pub fn is_0101(&self) -> bool {
259 *self == PRESCALER::_0101
260 }
261 #[doc = "Checks if the value of the field is `_0110`"]
262 #[inline]
263 pub fn is_0110(&self) -> bool {
264 *self == PRESCALER::_0110
265 }
266 #[doc = "Checks if the value of the field is `_0111`"]
267 #[inline]
268 pub fn is_0111(&self) -> bool {
269 *self == PRESCALER::_0111
270 }
271 #[doc = "Checks if the value of the field is `_1000`"]
272 #[inline]
273 pub fn is_1000(&self) -> bool {
274 *self == PRESCALER::_1000
275 }
276 #[doc = "Checks if the value of the field is `_1001`"]
277 #[inline]
278 pub fn is_1001(&self) -> bool {
279 *self == PRESCALER::_1001
280 }
281 #[doc = "Checks if the value of the field is `_1010`"]
282 #[inline]
283 pub fn is_1010(&self) -> bool {
284 *self == PRESCALER::_1010
285 }
286 #[doc = "Checks if the value of the field is `_1011`"]
287 #[inline]
288 pub fn is_1011(&self) -> bool {
289 *self == PRESCALER::_1011
290 }
291 #[doc = "Checks if the value of the field is `_1100`"]
292 #[inline]
293 pub fn is_1100(&self) -> bool {
294 *self == PRESCALER::_1100
295 }
296 #[doc = "Checks if the value of the field is `_1101`"]
297 #[inline]
298 pub fn is_1101(&self) -> bool {
299 *self == PRESCALER::_1101
300 }
301 #[doc = "Checks if the value of the field is `_1110`"]
302 #[inline]
303 pub fn is_1110(&self) -> bool {
304 *self == PRESCALER::_1110
305 }
306 #[doc = "Checks if the value of the field is `_1111`"]
307 #[inline]
308 pub fn is_1111(&self) -> bool {
309 *self == PRESCALER::_1111
310 }
311}
312#[doc = "Values that can be written to the field `PCS`"]
313pub enum PCSW {
314 #[doc = "Prescaler/glitch filter clock 0 selected"]
315 _00,
316 #[doc = "Prescaler/glitch filter clock 1 selected"]
317 _01,
318 #[doc = "Prescaler/glitch filter clock 2 selected"]
319 _10,
320 #[doc = "Prescaler/glitch filter clock 3 selected"]
321 _11,
322}
323impl PCSW {
324 #[allow(missing_docs)]
325 #[doc(hidden)]
326 #[inline]
327 pub fn _bits(&self) -> u8 {
328 match *self {
329 PCSW::_00 => 0,
330 PCSW::_01 => 1,
331 PCSW::_10 => 2,
332 PCSW::_11 => 3,
333 }
334 }
335}
336#[doc = r" Proxy"]
337pub struct _PCSW<'a> {
338 w: &'a mut W,
339}
340impl<'a> _PCSW<'a> {
341 #[doc = r" Writes `variant` to the field"]
342 #[inline]
343 pub fn variant(self, variant: PCSW) -> &'a mut W {
344 {
345 self.bits(variant._bits())
346 }
347 }
348 #[doc = "Prescaler/glitch filter clock 0 selected"]
349 #[inline]
350 pub fn _00(self) -> &'a mut W {
351 self.variant(PCSW::_00)
352 }
353 #[doc = "Prescaler/glitch filter clock 1 selected"]
354 #[inline]
355 pub fn _01(self) -> &'a mut W {
356 self.variant(PCSW::_01)
357 }
358 #[doc = "Prescaler/glitch filter clock 2 selected"]
359 #[inline]
360 pub fn _10(self) -> &'a mut W {
361 self.variant(PCSW::_10)
362 }
363 #[doc = "Prescaler/glitch filter clock 3 selected"]
364 #[inline]
365 pub fn _11(self) -> &'a mut W {
366 self.variant(PCSW::_11)
367 }
368 #[doc = r" Writes raw bits to the field"]
369 #[inline]
370 pub fn bits(self, value: u8) -> &'a mut W {
371 const MASK: u8 = 3;
372 const OFFSET: u8 = 0;
373 self.w.bits &= !((MASK as u32) << OFFSET);
374 self.w.bits |= ((value & MASK) as u32) << OFFSET;
375 self.w
376 }
377}
378#[doc = "Values that can be written to the field `PBYP`"]
379pub enum PBYPW {
380 #[doc = "Prescaler/Glitch Filter is enabled."]
381 _0,
382 #[doc = "Prescaler/Glitch Filter is bypassed."]
383 _1,
384}
385impl PBYPW {
386 #[allow(missing_docs)]
387 #[doc(hidden)]
388 #[inline]
389 pub fn _bits(&self) -> bool {
390 match *self {
391 PBYPW::_0 => false,
392 PBYPW::_1 => true,
393 }
394 }
395}
396#[doc = r" Proxy"]
397pub struct _PBYPW<'a> {
398 w: &'a mut W,
399}
400impl<'a> _PBYPW<'a> {
401 #[doc = r" Writes `variant` to the field"]
402 #[inline]
403 pub fn variant(self, variant: PBYPW) -> &'a mut W {
404 {
405 self.bit(variant._bits())
406 }
407 }
408 #[doc = "Prescaler/Glitch Filter is enabled."]
409 #[inline]
410 pub fn _0(self) -> &'a mut W {
411 self.variant(PBYPW::_0)
412 }
413 #[doc = "Prescaler/Glitch Filter is bypassed."]
414 #[inline]
415 pub fn _1(self) -> &'a mut W {
416 self.variant(PBYPW::_1)
417 }
418 #[doc = r" Sets the field bit"]
419 pub fn set_bit(self) -> &'a mut W {
420 self.bit(true)
421 }
422 #[doc = r" Clears the field bit"]
423 pub fn clear_bit(self) -> &'a mut W {
424 self.bit(false)
425 }
426 #[doc = r" Writes raw bits to the field"]
427 #[inline]
428 pub fn bit(self, value: bool) -> &'a mut W {
429 const MASK: bool = true;
430 const OFFSET: u8 = 2;
431 self.w.bits &= !((MASK as u32) << OFFSET);
432 self.w.bits |= ((value & MASK) as u32) << OFFSET;
433 self.w
434 }
435}
436#[doc = "Values that can be written to the field `PRESCALE`"]
437pub enum PRESCALEW {
438 #[doc = "Prescaler divides the prescaler clock by 2; Glitch Filter does not support this configuration."]
439 _0000,
440 #[doc = "Prescaler divides the prescaler clock by 4; Glitch Filter recognizes change on input pin after 2 rising clock edges."]
441 _0001,
442 #[doc = "Prescaler divides the prescaler clock by 8; Glitch Filter recognizes change on input pin after 4 rising clock edges."]
443 _0010,
444 #[doc = "Prescaler divides the prescaler clock by 16; Glitch Filter recognizes change on input pin after 8 rising clock edges."]
445 _0011,
446 #[doc = "Prescaler divides the prescaler clock by 32; Glitch Filter recognizes change on input pin after 16 rising clock edges."]
447 _0100,
448 #[doc = "Prescaler divides the prescaler clock by 64; Glitch Filter recognizes change on input pin after 32 rising clock edges."]
449 _0101,
450 #[doc = "Prescaler divides the prescaler clock by 128; Glitch Filter recognizes change on input pin after 64 rising clock edges."]
451 _0110,
452 #[doc = "Prescaler divides the prescaler clock by 256; Glitch Filter recognizes change on input pin after 128 rising clock edges."]
453 _0111,
454 #[doc = "Prescaler divides the prescaler clock by 512; Glitch Filter recognizes change on input pin after 256 rising clock edges."]
455 _1000,
456 #[doc = "Prescaler divides the prescaler clock by 1024; Glitch Filter recognizes change on input pin after 512 rising clock edges."]
457 _1001,
458 #[doc = "Prescaler divides the prescaler clock by 2048; Glitch Filter recognizes change on input pin after 1024 rising clock edges."]
459 _1010,
460 #[doc = "Prescaler divides the prescaler clock by 4096; Glitch Filter recognizes change on input pin after 2048 rising clock edges."]
461 _1011,
462 #[doc = "Prescaler divides the prescaler clock by 8192; Glitch Filter recognizes change on input pin after 4096 rising clock edges."]
463 _1100,
464 #[doc = "Prescaler divides the prescaler clock by 16384; Glitch Filter recognizes change on input pin after 8192 rising clock edges."]
465 _1101,
466 #[doc = "Prescaler divides the prescaler clock by 32768; Glitch Filter recognizes change on input pin after 16384 rising clock edges."]
467 _1110,
468 #[doc = "Prescaler divides the prescaler clock by 65536; Glitch Filter recognizes change on input pin after 32768 rising clock edges."]
469 _1111,
470}
471impl PRESCALEW {
472 #[allow(missing_docs)]
473 #[doc(hidden)]
474 #[inline]
475 pub fn _bits(&self) -> u8 {
476 match *self {
477 PRESCALEW::_0000 => 0,
478 PRESCALEW::_0001 => 1,
479 PRESCALEW::_0010 => 2,
480 PRESCALEW::_0011 => 3,
481 PRESCALEW::_0100 => 4,
482 PRESCALEW::_0101 => 5,
483 PRESCALEW::_0110 => 6,
484 PRESCALEW::_0111 => 7,
485 PRESCALEW::_1000 => 8,
486 PRESCALEW::_1001 => 9,
487 PRESCALEW::_1010 => 10,
488 PRESCALEW::_1011 => 11,
489 PRESCALEW::_1100 => 12,
490 PRESCALEW::_1101 => 13,
491 PRESCALEW::_1110 => 14,
492 PRESCALEW::_1111 => 15,
493 }
494 }
495}
496#[doc = r" Proxy"]
497pub struct _PRESCALEW<'a> {
498 w: &'a mut W,
499}
500impl<'a> _PRESCALEW<'a> {
501 #[doc = r" Writes `variant` to the field"]
502 #[inline]
503 pub fn variant(self, variant: PRESCALEW) -> &'a mut W {
504 {
505 self.bits(variant._bits())
506 }
507 }
508 #[doc = "Prescaler divides the prescaler clock by 2; Glitch Filter does not support this configuration."]
509 #[inline]
510 pub fn _0000(self) -> &'a mut W {
511 self.variant(PRESCALEW::_0000)
512 }
513 #[doc = "Prescaler divides the prescaler clock by 4; Glitch Filter recognizes change on input pin after 2 rising clock edges."]
514 #[inline]
515 pub fn _0001(self) -> &'a mut W {
516 self.variant(PRESCALEW::_0001)
517 }
518 #[doc = "Prescaler divides the prescaler clock by 8; Glitch Filter recognizes change on input pin after 4 rising clock edges."]
519 #[inline]
520 pub fn _0010(self) -> &'a mut W {
521 self.variant(PRESCALEW::_0010)
522 }
523 #[doc = "Prescaler divides the prescaler clock by 16; Glitch Filter recognizes change on input pin after 8 rising clock edges."]
524 #[inline]
525 pub fn _0011(self) -> &'a mut W {
526 self.variant(PRESCALEW::_0011)
527 }
528 #[doc = "Prescaler divides the prescaler clock by 32; Glitch Filter recognizes change on input pin after 16 rising clock edges."]
529 #[inline]
530 pub fn _0100(self) -> &'a mut W {
531 self.variant(PRESCALEW::_0100)
532 }
533 #[doc = "Prescaler divides the prescaler clock by 64; Glitch Filter recognizes change on input pin after 32 rising clock edges."]
534 #[inline]
535 pub fn _0101(self) -> &'a mut W {
536 self.variant(PRESCALEW::_0101)
537 }
538 #[doc = "Prescaler divides the prescaler clock by 128; Glitch Filter recognizes change on input pin after 64 rising clock edges."]
539 #[inline]
540 pub fn _0110(self) -> &'a mut W {
541 self.variant(PRESCALEW::_0110)
542 }
543 #[doc = "Prescaler divides the prescaler clock by 256; Glitch Filter recognizes change on input pin after 128 rising clock edges."]
544 #[inline]
545 pub fn _0111(self) -> &'a mut W {
546 self.variant(PRESCALEW::_0111)
547 }
548 #[doc = "Prescaler divides the prescaler clock by 512; Glitch Filter recognizes change on input pin after 256 rising clock edges."]
549 #[inline]
550 pub fn _1000(self) -> &'a mut W {
551 self.variant(PRESCALEW::_1000)
552 }
553 #[doc = "Prescaler divides the prescaler clock by 1024; Glitch Filter recognizes change on input pin after 512 rising clock edges."]
554 #[inline]
555 pub fn _1001(self) -> &'a mut W {
556 self.variant(PRESCALEW::_1001)
557 }
558 #[doc = "Prescaler divides the prescaler clock by 2048; Glitch Filter recognizes change on input pin after 1024 rising clock edges."]
559 #[inline]
560 pub fn _1010(self) -> &'a mut W {
561 self.variant(PRESCALEW::_1010)
562 }
563 #[doc = "Prescaler divides the prescaler clock by 4096; Glitch Filter recognizes change on input pin after 2048 rising clock edges."]
564 #[inline]
565 pub fn _1011(self) -> &'a mut W {
566 self.variant(PRESCALEW::_1011)
567 }
568 #[doc = "Prescaler divides the prescaler clock by 8192; Glitch Filter recognizes change on input pin after 4096 rising clock edges."]
569 #[inline]
570 pub fn _1100(self) -> &'a mut W {
571 self.variant(PRESCALEW::_1100)
572 }
573 #[doc = "Prescaler divides the prescaler clock by 16384; Glitch Filter recognizes change on input pin after 8192 rising clock edges."]
574 #[inline]
575 pub fn _1101(self) -> &'a mut W {
576 self.variant(PRESCALEW::_1101)
577 }
578 #[doc = "Prescaler divides the prescaler clock by 32768; Glitch Filter recognizes change on input pin after 16384 rising clock edges."]
579 #[inline]
580 pub fn _1110(self) -> &'a mut W {
581 self.variant(PRESCALEW::_1110)
582 }
583 #[doc = "Prescaler divides the prescaler clock by 65536; Glitch Filter recognizes change on input pin after 32768 rising clock edges."]
584 #[inline]
585 pub fn _1111(self) -> &'a mut W {
586 self.variant(PRESCALEW::_1111)
587 }
588 #[doc = r" Writes raw bits to the field"]
589 #[inline]
590 pub fn bits(self, value: u8) -> &'a mut W {
591 const MASK: u8 = 15;
592 const OFFSET: u8 = 3;
593 self.w.bits &= !((MASK as u32) << OFFSET);
594 self.w.bits |= ((value & MASK) as u32) << OFFSET;
595 self.w
596 }
597}
598impl R {
599 #[doc = r" Value of the register as raw bits"]
600 #[inline]
601 pub fn bits(&self) -> u32 {
602 self.bits
603 }
604 #[doc = "Bits 0:1 - Prescaler Clock Select"]
605 #[inline]
606 pub fn pcs(&self) -> PCSR {
607 PCSR::_from({
608 const MASK: u8 = 3;
609 const OFFSET: u8 = 0;
610 ((self.bits >> OFFSET) & MASK as u32) as u8
611 })
612 }
613 #[doc = "Bit 2 - Prescaler Bypass"]
614 #[inline]
615 pub fn pbyp(&self) -> PBYPR {
616 PBYPR::_from({
617 const MASK: bool = true;
618 const OFFSET: u8 = 2;
619 ((self.bits >> OFFSET) & MASK as u32) != 0
620 })
621 }
622 #[doc = "Bits 3:6 - Prescale Value"]
623 #[inline]
624 pub fn prescale(&self) -> PRESCALER {
625 PRESCALER::_from({
626 const MASK: u8 = 15;
627 const OFFSET: u8 = 3;
628 ((self.bits >> OFFSET) & MASK as u32) as u8
629 })
630 }
631}
632impl W {
633 #[doc = r" Reset value of the register"]
634 #[inline]
635 pub fn reset_value() -> W {
636 W { bits: 0 }
637 }
638 #[doc = r" Writes raw bits to the register"]
639 #[inline]
640 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
641 self.bits = bits;
642 self
643 }
644 #[doc = "Bits 0:1 - Prescaler Clock Select"]
645 #[inline]
646 pub fn pcs(&mut self) -> _PCSW {
647 _PCSW { w: self }
648 }
649 #[doc = "Bit 2 - Prescaler Bypass"]
650 #[inline]
651 pub fn pbyp(&mut self) -> _PBYPW {
652 _PBYPW { w: self }
653 }
654 #[doc = "Bits 3:6 - Prescale Value"]
655 #[inline]
656 pub fn prescale(&mut self) -> _PRESCALEW {
657 _PRESCALEW { w: self }
658 }
659}