1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::SC3 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `AVGS`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum AVGSR {
48 #[doc = "4 samples averaged."]
49 _00,
50 #[doc = "8 samples averaged."]
51 _01,
52 #[doc = "16 samples averaged."]
53 _10,
54 #[doc = "32 samples averaged."]
55 _11,
56}
57impl AVGSR {
58 #[doc = r" Value of the field as raw bits"]
59 #[inline]
60 pub fn bits(&self) -> u8 {
61 match *self {
62 AVGSR::_00 => 0,
63 AVGSR::_01 => 1,
64 AVGSR::_10 => 2,
65 AVGSR::_11 => 3,
66 }
67 }
68 #[allow(missing_docs)]
69 #[doc(hidden)]
70 #[inline]
71 pub fn _from(value: u8) -> AVGSR {
72 match value {
73 0 => AVGSR::_00,
74 1 => AVGSR::_01,
75 2 => AVGSR::_10,
76 3 => AVGSR::_11,
77 _ => unreachable!(),
78 }
79 }
80 #[doc = "Checks if the value of the field is `_00`"]
81 #[inline]
82 pub fn is_00(&self) -> bool {
83 *self == AVGSR::_00
84 }
85 #[doc = "Checks if the value of the field is `_01`"]
86 #[inline]
87 pub fn is_01(&self) -> bool {
88 *self == AVGSR::_01
89 }
90 #[doc = "Checks if the value of the field is `_10`"]
91 #[inline]
92 pub fn is_10(&self) -> bool {
93 *self == AVGSR::_10
94 }
95 #[doc = "Checks if the value of the field is `_11`"]
96 #[inline]
97 pub fn is_11(&self) -> bool {
98 *self == AVGSR::_11
99 }
100}
101#[doc = "Possible values of the field `AVGE`"]
102#[derive(Clone, Copy, Debug, PartialEq)]
103pub enum AVGER {
104 #[doc = "Hardware average function disabled."]
105 _0,
106 #[doc = "Hardware average function enabled."]
107 _1,
108}
109impl AVGER {
110 #[doc = r" Returns `true` if the bit is clear (0)"]
111 #[inline]
112 pub fn bit_is_clear(&self) -> bool {
113 !self.bit()
114 }
115 #[doc = r" Returns `true` if the bit is set (1)"]
116 #[inline]
117 pub fn bit_is_set(&self) -> bool {
118 self.bit()
119 }
120 #[doc = r" Value of the field as raw bits"]
121 #[inline]
122 pub fn bit(&self) -> bool {
123 match *self {
124 AVGER::_0 => false,
125 AVGER::_1 => true,
126 }
127 }
128 #[allow(missing_docs)]
129 #[doc(hidden)]
130 #[inline]
131 pub fn _from(value: bool) -> AVGER {
132 match value {
133 false => AVGER::_0,
134 true => AVGER::_1,
135 }
136 }
137 #[doc = "Checks if the value of the field is `_0`"]
138 #[inline]
139 pub fn is_0(&self) -> bool {
140 *self == AVGER::_0
141 }
142 #[doc = "Checks if the value of the field is `_1`"]
143 #[inline]
144 pub fn is_1(&self) -> bool {
145 *self == AVGER::_1
146 }
147}
148#[doc = "Possible values of the field `ADCO`"]
149#[derive(Clone, Copy, Debug, PartialEq)]
150pub enum ADCOR {
151 #[doc = "One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion."]
152 _0,
153 #[doc = "Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion."]
154 _1,
155}
156impl ADCOR {
157 #[doc = r" Returns `true` if the bit is clear (0)"]
158 #[inline]
159 pub fn bit_is_clear(&self) -> bool {
160 !self.bit()
161 }
162 #[doc = r" Returns `true` if the bit is set (1)"]
163 #[inline]
164 pub fn bit_is_set(&self) -> bool {
165 self.bit()
166 }
167 #[doc = r" Value of the field as raw bits"]
168 #[inline]
169 pub fn bit(&self) -> bool {
170 match *self {
171 ADCOR::_0 => false,
172 ADCOR::_1 => true,
173 }
174 }
175 #[allow(missing_docs)]
176 #[doc(hidden)]
177 #[inline]
178 pub fn _from(value: bool) -> ADCOR {
179 match value {
180 false => ADCOR::_0,
181 true => ADCOR::_1,
182 }
183 }
184 #[doc = "Checks if the value of the field is `_0`"]
185 #[inline]
186 pub fn is_0(&self) -> bool {
187 *self == ADCOR::_0
188 }
189 #[doc = "Checks if the value of the field is `_1`"]
190 #[inline]
191 pub fn is_1(&self) -> bool {
192 *self == ADCOR::_1
193 }
194}
195#[doc = "Possible values of the field `CALF`"]
196#[derive(Clone, Copy, Debug, PartialEq)]
197pub enum CALFR {
198 #[doc = "Calibration completed normally."]
199 _0,
200 #[doc = "Calibration failed. ADC accuracy specifications are not guaranteed."]
201 _1,
202}
203impl CALFR {
204 #[doc = r" Returns `true` if the bit is clear (0)"]
205 #[inline]
206 pub fn bit_is_clear(&self) -> bool {
207 !self.bit()
208 }
209 #[doc = r" Returns `true` if the bit is set (1)"]
210 #[inline]
211 pub fn bit_is_set(&self) -> bool {
212 self.bit()
213 }
214 #[doc = r" Value of the field as raw bits"]
215 #[inline]
216 pub fn bit(&self) -> bool {
217 match *self {
218 CALFR::_0 => false,
219 CALFR::_1 => true,
220 }
221 }
222 #[allow(missing_docs)]
223 #[doc(hidden)]
224 #[inline]
225 pub fn _from(value: bool) -> CALFR {
226 match value {
227 false => CALFR::_0,
228 true => CALFR::_1,
229 }
230 }
231 #[doc = "Checks if the value of the field is `_0`"]
232 #[inline]
233 pub fn is_0(&self) -> bool {
234 *self == CALFR::_0
235 }
236 #[doc = "Checks if the value of the field is `_1`"]
237 #[inline]
238 pub fn is_1(&self) -> bool {
239 *self == CALFR::_1
240 }
241}
242#[doc = r" Value of the field"]
243pub struct CALR {
244 bits: bool,
245}
246impl CALR {
247 #[doc = r" Value of the field as raw bits"]
248 #[inline]
249 pub fn bit(&self) -> bool {
250 self.bits
251 }
252 #[doc = r" Returns `true` if the bit is clear (0)"]
253 #[inline]
254 pub fn bit_is_clear(&self) -> bool {
255 !self.bit()
256 }
257 #[doc = r" Returns `true` if the bit is set (1)"]
258 #[inline]
259 pub fn bit_is_set(&self) -> bool {
260 self.bit()
261 }
262}
263#[doc = "Values that can be written to the field `AVGS`"]
264pub enum AVGSW {
265 #[doc = "4 samples averaged."]
266 _00,
267 #[doc = "8 samples averaged."]
268 _01,
269 #[doc = "16 samples averaged."]
270 _10,
271 #[doc = "32 samples averaged."]
272 _11,
273}
274impl AVGSW {
275 #[allow(missing_docs)]
276 #[doc(hidden)]
277 #[inline]
278 pub fn _bits(&self) -> u8 {
279 match *self {
280 AVGSW::_00 => 0,
281 AVGSW::_01 => 1,
282 AVGSW::_10 => 2,
283 AVGSW::_11 => 3,
284 }
285 }
286}
287#[doc = r" Proxy"]
288pub struct _AVGSW<'a> {
289 w: &'a mut W,
290}
291impl<'a> _AVGSW<'a> {
292 #[doc = r" Writes `variant` to the field"]
293 #[inline]
294 pub fn variant(self, variant: AVGSW) -> &'a mut W {
295 {
296 self.bits(variant._bits())
297 }
298 }
299 #[doc = "4 samples averaged."]
300 #[inline]
301 pub fn _00(self) -> &'a mut W {
302 self.variant(AVGSW::_00)
303 }
304 #[doc = "8 samples averaged."]
305 #[inline]
306 pub fn _01(self) -> &'a mut W {
307 self.variant(AVGSW::_01)
308 }
309 #[doc = "16 samples averaged."]
310 #[inline]
311 pub fn _10(self) -> &'a mut W {
312 self.variant(AVGSW::_10)
313 }
314 #[doc = "32 samples averaged."]
315 #[inline]
316 pub fn _11(self) -> &'a mut W {
317 self.variant(AVGSW::_11)
318 }
319 #[doc = r" Writes raw bits to the field"]
320 #[inline]
321 pub fn bits(self, value: u8) -> &'a mut W {
322 const MASK: u8 = 3;
323 const OFFSET: u8 = 0;
324 self.w.bits &= !((MASK as u32) << OFFSET);
325 self.w.bits |= ((value & MASK) as u32) << OFFSET;
326 self.w
327 }
328}
329#[doc = "Values that can be written to the field `AVGE`"]
330pub enum AVGEW {
331 #[doc = "Hardware average function disabled."]
332 _0,
333 #[doc = "Hardware average function enabled."]
334 _1,
335}
336impl AVGEW {
337 #[allow(missing_docs)]
338 #[doc(hidden)]
339 #[inline]
340 pub fn _bits(&self) -> bool {
341 match *self {
342 AVGEW::_0 => false,
343 AVGEW::_1 => true,
344 }
345 }
346}
347#[doc = r" Proxy"]
348pub struct _AVGEW<'a> {
349 w: &'a mut W,
350}
351impl<'a> _AVGEW<'a> {
352 #[doc = r" Writes `variant` to the field"]
353 #[inline]
354 pub fn variant(self, variant: AVGEW) -> &'a mut W {
355 {
356 self.bit(variant._bits())
357 }
358 }
359 #[doc = "Hardware average function disabled."]
360 #[inline]
361 pub fn _0(self) -> &'a mut W {
362 self.variant(AVGEW::_0)
363 }
364 #[doc = "Hardware average function enabled."]
365 #[inline]
366 pub fn _1(self) -> &'a mut W {
367 self.variant(AVGEW::_1)
368 }
369 #[doc = r" Sets the field bit"]
370 pub fn set_bit(self) -> &'a mut W {
371 self.bit(true)
372 }
373 #[doc = r" Clears the field bit"]
374 pub fn clear_bit(self) -> &'a mut W {
375 self.bit(false)
376 }
377 #[doc = r" Writes raw bits to the field"]
378 #[inline]
379 pub fn bit(self, value: bool) -> &'a mut W {
380 const MASK: bool = true;
381 const OFFSET: u8 = 2;
382 self.w.bits &= !((MASK as u32) << OFFSET);
383 self.w.bits |= ((value & MASK) as u32) << OFFSET;
384 self.w
385 }
386}
387#[doc = "Values that can be written to the field `ADCO`"]
388pub enum ADCOW {
389 #[doc = "One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion."]
390 _0,
391 #[doc = "Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion."]
392 _1,
393}
394impl ADCOW {
395 #[allow(missing_docs)]
396 #[doc(hidden)]
397 #[inline]
398 pub fn _bits(&self) -> bool {
399 match *self {
400 ADCOW::_0 => false,
401 ADCOW::_1 => true,
402 }
403 }
404}
405#[doc = r" Proxy"]
406pub struct _ADCOW<'a> {
407 w: &'a mut W,
408}
409impl<'a> _ADCOW<'a> {
410 #[doc = r" Writes `variant` to the field"]
411 #[inline]
412 pub fn variant(self, variant: ADCOW) -> &'a mut W {
413 {
414 self.bit(variant._bits())
415 }
416 }
417 #[doc = "One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion."]
418 #[inline]
419 pub fn _0(self) -> &'a mut W {
420 self.variant(ADCOW::_0)
421 }
422 #[doc = "Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion."]
423 #[inline]
424 pub fn _1(self) -> &'a mut W {
425 self.variant(ADCOW::_1)
426 }
427 #[doc = r" Sets the field bit"]
428 pub fn set_bit(self) -> &'a mut W {
429 self.bit(true)
430 }
431 #[doc = r" Clears the field bit"]
432 pub fn clear_bit(self) -> &'a mut W {
433 self.bit(false)
434 }
435 #[doc = r" Writes raw bits to the field"]
436 #[inline]
437 pub fn bit(self, value: bool) -> &'a mut W {
438 const MASK: bool = true;
439 const OFFSET: u8 = 3;
440 self.w.bits &= !((MASK as u32) << OFFSET);
441 self.w.bits |= ((value & MASK) as u32) << OFFSET;
442 self.w
443 }
444}
445#[doc = "Values that can be written to the field `CALF`"]
446pub enum CALFW {
447 #[doc = "Calibration completed normally."]
448 _0,
449 #[doc = "Calibration failed. ADC accuracy specifications are not guaranteed."]
450 _1,
451}
452impl CALFW {
453 #[allow(missing_docs)]
454 #[doc(hidden)]
455 #[inline]
456 pub fn _bits(&self) -> bool {
457 match *self {
458 CALFW::_0 => false,
459 CALFW::_1 => true,
460 }
461 }
462}
463#[doc = r" Proxy"]
464pub struct _CALFW<'a> {
465 w: &'a mut W,
466}
467impl<'a> _CALFW<'a> {
468 #[doc = r" Writes `variant` to the field"]
469 #[inline]
470 pub fn variant(self, variant: CALFW) -> &'a mut W {
471 {
472 self.bit(variant._bits())
473 }
474 }
475 #[doc = "Calibration completed normally."]
476 #[inline]
477 pub fn _0(self) -> &'a mut W {
478 self.variant(CALFW::_0)
479 }
480 #[doc = "Calibration failed. ADC accuracy specifications are not guaranteed."]
481 #[inline]
482 pub fn _1(self) -> &'a mut W {
483 self.variant(CALFW::_1)
484 }
485 #[doc = r" Sets the field bit"]
486 pub fn set_bit(self) -> &'a mut W {
487 self.bit(true)
488 }
489 #[doc = r" Clears the field bit"]
490 pub fn clear_bit(self) -> &'a mut W {
491 self.bit(false)
492 }
493 #[doc = r" Writes raw bits to the field"]
494 #[inline]
495 pub fn bit(self, value: bool) -> &'a mut W {
496 const MASK: bool = true;
497 const OFFSET: u8 = 6;
498 self.w.bits &= !((MASK as u32) << OFFSET);
499 self.w.bits |= ((value & MASK) as u32) << OFFSET;
500 self.w
501 }
502}
503#[doc = r" Proxy"]
504pub struct _CALW<'a> {
505 w: &'a mut W,
506}
507impl<'a> _CALW<'a> {
508 #[doc = r" Sets the field bit"]
509 pub fn set_bit(self) -> &'a mut W {
510 self.bit(true)
511 }
512 #[doc = r" Clears the field bit"]
513 pub fn clear_bit(self) -> &'a mut W {
514 self.bit(false)
515 }
516 #[doc = r" Writes raw bits to the field"]
517 #[inline]
518 pub fn bit(self, value: bool) -> &'a mut W {
519 const MASK: bool = true;
520 const OFFSET: u8 = 7;
521 self.w.bits &= !((MASK as u32) << OFFSET);
522 self.w.bits |= ((value & MASK) as u32) << OFFSET;
523 self.w
524 }
525}
526impl R {
527 #[doc = r" Value of the register as raw bits"]
528 #[inline]
529 pub fn bits(&self) -> u32 {
530 self.bits
531 }
532 #[doc = "Bits 0:1 - Hardware average select"]
533 #[inline]
534 pub fn avgs(&self) -> AVGSR {
535 AVGSR::_from({
536 const MASK: u8 = 3;
537 const OFFSET: u8 = 0;
538 ((self.bits >> OFFSET) & MASK as u32) as u8
539 })
540 }
541 #[doc = "Bit 2 - Hardware average enable"]
542 #[inline]
543 pub fn avge(&self) -> AVGER {
544 AVGER::_from({
545 const MASK: bool = true;
546 const OFFSET: u8 = 2;
547 ((self.bits >> OFFSET) & MASK as u32) != 0
548 })
549 }
550 #[doc = "Bit 3 - Continuous conversion enable"]
551 #[inline]
552 pub fn adco(&self) -> ADCOR {
553 ADCOR::_from({
554 const MASK: bool = true;
555 const OFFSET: u8 = 3;
556 ((self.bits >> OFFSET) & MASK as u32) != 0
557 })
558 }
559 #[doc = "Bit 6 - Calibration failed flag"]
560 #[inline]
561 pub fn calf(&self) -> CALFR {
562 CALFR::_from({
563 const MASK: bool = true;
564 const OFFSET: u8 = 6;
565 ((self.bits >> OFFSET) & MASK as u32) != 0
566 })
567 }
568 #[doc = "Bit 7 - Calibration"]
569 #[inline]
570 pub fn cal(&self) -> CALR {
571 let bits = {
572 const MASK: bool = true;
573 const OFFSET: u8 = 7;
574 ((self.bits >> OFFSET) & MASK as u32) != 0
575 };
576 CALR { bits }
577 }
578}
579impl W {
580 #[doc = r" Reset value of the register"]
581 #[inline]
582 pub fn reset_value() -> W {
583 W { bits: 0 }
584 }
585 #[doc = r" Writes raw bits to the register"]
586 #[inline]
587 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
588 self.bits = bits;
589 self
590 }
591 #[doc = "Bits 0:1 - Hardware average select"]
592 #[inline]
593 pub fn avgs(&mut self) -> _AVGSW {
594 _AVGSW { w: self }
595 }
596 #[doc = "Bit 2 - Hardware average enable"]
597 #[inline]
598 pub fn avge(&mut self) -> _AVGEW {
599 _AVGEW { w: self }
600 }
601 #[doc = "Bit 3 - Continuous conversion enable"]
602 #[inline]
603 pub fn adco(&mut self) -> _ADCOW {
604 _ADCOW { w: self }
605 }
606 #[doc = "Bit 6 - Calibration failed flag"]
607 #[inline]
608 pub fn calf(&mut self) -> _CALFW {
609 _CALFW { w: self }
610 }
611 #[doc = "Bit 7 - Calibration"]
612 #[inline]
613 pub fn cal(&mut self) -> _CALW {
614 _CALW { w: self }
615 }
616}