mimxrt685s_pac/i2c0/
msttime.rs1#[doc = "Register `MSTTIME` reader"]
2pub type R = crate::R<MsttimeSpec>;
3#[doc = "Register `MSTTIME` writer"]
4pub type W = crate::W<MsttimeSpec>;
5#[doc = "Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.\n\nValue on reset: 7"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Mstscllow {
10 #[doc = "0: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider."]
11 Clocks2 = 0,
12 #[doc = "1: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider."]
13 Clocks3 = 1,
14 #[doc = "2: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider."]
15 Clocks4 = 2,
16 #[doc = "3: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider."]
17 Clocks5 = 3,
18 #[doc = "4: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider."]
19 Clocks6 = 4,
20 #[doc = "5: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider."]
21 Clocks7 = 5,
22 #[doc = "6: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider."]
23 Clocks8 = 6,
24 #[doc = "7: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider."]
25 Clocks9 = 7,
26}
27impl From<Mstscllow> for u8 {
28 #[inline(always)]
29 fn from(variant: Mstscllow) -> Self {
30 variant as _
31 }
32}
33impl crate::FieldSpec for Mstscllow {
34 type Ux = u8;
35}
36impl crate::IsEnum for Mstscllow {}
37#[doc = "Field `MSTSCLLOW` reader - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW."]
38pub type MstscllowR = crate::FieldReader<Mstscllow>;
39impl MstscllowR {
40 #[doc = "Get enumerated values variant"]
41 #[inline(always)]
42 pub const fn variant(&self) -> Mstscllow {
43 match self.bits {
44 0 => Mstscllow::Clocks2,
45 1 => Mstscllow::Clocks3,
46 2 => Mstscllow::Clocks4,
47 3 => Mstscllow::Clocks5,
48 4 => Mstscllow::Clocks6,
49 5 => Mstscllow::Clocks7,
50 6 => Mstscllow::Clocks8,
51 7 => Mstscllow::Clocks9,
52 _ => unreachable!(),
53 }
54 }
55 #[doc = "2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider."]
56 #[inline(always)]
57 pub fn is_clocks_2(&self) -> bool {
58 *self == Mstscllow::Clocks2
59 }
60 #[doc = "3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider."]
61 #[inline(always)]
62 pub fn is_clocks_3(&self) -> bool {
63 *self == Mstscllow::Clocks3
64 }
65 #[doc = "4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider."]
66 #[inline(always)]
67 pub fn is_clocks_4(&self) -> bool {
68 *self == Mstscllow::Clocks4
69 }
70 #[doc = "5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider."]
71 #[inline(always)]
72 pub fn is_clocks_5(&self) -> bool {
73 *self == Mstscllow::Clocks5
74 }
75 #[doc = "6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider."]
76 #[inline(always)]
77 pub fn is_clocks_6(&self) -> bool {
78 *self == Mstscllow::Clocks6
79 }
80 #[doc = "7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider."]
81 #[inline(always)]
82 pub fn is_clocks_7(&self) -> bool {
83 *self == Mstscllow::Clocks7
84 }
85 #[doc = "8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider."]
86 #[inline(always)]
87 pub fn is_clocks_8(&self) -> bool {
88 *self == Mstscllow::Clocks8
89 }
90 #[doc = "9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider."]
91 #[inline(always)]
92 pub fn is_clocks_9(&self) -> bool {
93 *self == Mstscllow::Clocks9
94 }
95}
96#[doc = "Field `MSTSCLLOW` writer - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW."]
97pub type MstscllowW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mstscllow, crate::Safe>;
98impl<'a, REG> MstscllowW<'a, REG>
99where
100 REG: crate::Writable + crate::RegisterSpec,
101 REG::Ux: From<u8>,
102{
103 #[doc = "2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider."]
104 #[inline(always)]
105 pub fn clocks_2(self) -> &'a mut crate::W<REG> {
106 self.variant(Mstscllow::Clocks2)
107 }
108 #[doc = "3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider."]
109 #[inline(always)]
110 pub fn clocks_3(self) -> &'a mut crate::W<REG> {
111 self.variant(Mstscllow::Clocks3)
112 }
113 #[doc = "4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider."]
114 #[inline(always)]
115 pub fn clocks_4(self) -> &'a mut crate::W<REG> {
116 self.variant(Mstscllow::Clocks4)
117 }
118 #[doc = "5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider."]
119 #[inline(always)]
120 pub fn clocks_5(self) -> &'a mut crate::W<REG> {
121 self.variant(Mstscllow::Clocks5)
122 }
123 #[doc = "6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider."]
124 #[inline(always)]
125 pub fn clocks_6(self) -> &'a mut crate::W<REG> {
126 self.variant(Mstscllow::Clocks6)
127 }
128 #[doc = "7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider."]
129 #[inline(always)]
130 pub fn clocks_7(self) -> &'a mut crate::W<REG> {
131 self.variant(Mstscllow::Clocks7)
132 }
133 #[doc = "8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider."]
134 #[inline(always)]
135 pub fn clocks_8(self) -> &'a mut crate::W<REG> {
136 self.variant(Mstscllow::Clocks8)
137 }
138 #[doc = "9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider."]
139 #[inline(always)]
140 pub fn clocks_9(self) -> &'a mut crate::W<REG> {
141 self.variant(Mstscllow::Clocks9)
142 }
143}
144#[doc = "Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.\n\nValue on reset: 7"]
145#[cfg_attr(feature = "defmt", derive(defmt::Format))]
146#[derive(Clone, Copy, Debug, PartialEq, Eq)]
147#[repr(u8)]
148pub enum Mstsclhigh {
149 #[doc = "0: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider."]
150 Clocks2 = 0,
151 #[doc = "1: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider ."]
152 Clocks3 = 1,
153 #[doc = "2: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider."]
154 Clocks4 = 2,
155 #[doc = "3: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider."]
156 Clocks5 = 3,
157 #[doc = "4: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider."]
158 Clocks6 = 4,
159 #[doc = "5: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider."]
160 Clocks7 = 5,
161 #[doc = "6: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider."]
162 Clocks8 = 6,
163 #[doc = "7: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider."]
164 Clocks9 = 7,
165}
166impl From<Mstsclhigh> for u8 {
167 #[inline(always)]
168 fn from(variant: Mstsclhigh) -> Self {
169 variant as _
170 }
171}
172impl crate::FieldSpec for Mstsclhigh {
173 type Ux = u8;
174}
175impl crate::IsEnum for Mstsclhigh {}
176#[doc = "Field `MSTSCLHIGH` reader - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH."]
177pub type MstsclhighR = crate::FieldReader<Mstsclhigh>;
178impl MstsclhighR {
179 #[doc = "Get enumerated values variant"]
180 #[inline(always)]
181 pub const fn variant(&self) -> Mstsclhigh {
182 match self.bits {
183 0 => Mstsclhigh::Clocks2,
184 1 => Mstsclhigh::Clocks3,
185 2 => Mstsclhigh::Clocks4,
186 3 => Mstsclhigh::Clocks5,
187 4 => Mstsclhigh::Clocks6,
188 5 => Mstsclhigh::Clocks7,
189 6 => Mstsclhigh::Clocks8,
190 7 => Mstsclhigh::Clocks9,
191 _ => unreachable!(),
192 }
193 }
194 #[doc = "2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider."]
195 #[inline(always)]
196 pub fn is_clocks_2(&self) -> bool {
197 *self == Mstsclhigh::Clocks2
198 }
199 #[doc = "3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider ."]
200 #[inline(always)]
201 pub fn is_clocks_3(&self) -> bool {
202 *self == Mstsclhigh::Clocks3
203 }
204 #[doc = "4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider."]
205 #[inline(always)]
206 pub fn is_clocks_4(&self) -> bool {
207 *self == Mstsclhigh::Clocks4
208 }
209 #[doc = "5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider."]
210 #[inline(always)]
211 pub fn is_clocks_5(&self) -> bool {
212 *self == Mstsclhigh::Clocks5
213 }
214 #[doc = "6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider."]
215 #[inline(always)]
216 pub fn is_clocks_6(&self) -> bool {
217 *self == Mstsclhigh::Clocks6
218 }
219 #[doc = "7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider."]
220 #[inline(always)]
221 pub fn is_clocks_7(&self) -> bool {
222 *self == Mstsclhigh::Clocks7
223 }
224 #[doc = "8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider."]
225 #[inline(always)]
226 pub fn is_clocks_8(&self) -> bool {
227 *self == Mstsclhigh::Clocks8
228 }
229 #[doc = "9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider."]
230 #[inline(always)]
231 pub fn is_clocks_9(&self) -> bool {
232 *self == Mstsclhigh::Clocks9
233 }
234}
235#[doc = "Field `MSTSCLHIGH` writer - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH."]
236pub type MstsclhighW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mstsclhigh, crate::Safe>;
237impl<'a, REG> MstsclhighW<'a, REG>
238where
239 REG: crate::Writable + crate::RegisterSpec,
240 REG::Ux: From<u8>,
241{
242 #[doc = "2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider."]
243 #[inline(always)]
244 pub fn clocks_2(self) -> &'a mut crate::W<REG> {
245 self.variant(Mstsclhigh::Clocks2)
246 }
247 #[doc = "3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider ."]
248 #[inline(always)]
249 pub fn clocks_3(self) -> &'a mut crate::W<REG> {
250 self.variant(Mstsclhigh::Clocks3)
251 }
252 #[doc = "4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider."]
253 #[inline(always)]
254 pub fn clocks_4(self) -> &'a mut crate::W<REG> {
255 self.variant(Mstsclhigh::Clocks4)
256 }
257 #[doc = "5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider."]
258 #[inline(always)]
259 pub fn clocks_5(self) -> &'a mut crate::W<REG> {
260 self.variant(Mstsclhigh::Clocks5)
261 }
262 #[doc = "6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider."]
263 #[inline(always)]
264 pub fn clocks_6(self) -> &'a mut crate::W<REG> {
265 self.variant(Mstsclhigh::Clocks6)
266 }
267 #[doc = "7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider."]
268 #[inline(always)]
269 pub fn clocks_7(self) -> &'a mut crate::W<REG> {
270 self.variant(Mstsclhigh::Clocks7)
271 }
272 #[doc = "8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider."]
273 #[inline(always)]
274 pub fn clocks_8(self) -> &'a mut crate::W<REG> {
275 self.variant(Mstsclhigh::Clocks8)
276 }
277 #[doc = "9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider."]
278 #[inline(always)]
279 pub fn clocks_9(self) -> &'a mut crate::W<REG> {
280 self.variant(Mstsclhigh::Clocks9)
281 }
282}
283impl R {
284 #[doc = "Bits 0:2 - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW."]
285 #[inline(always)]
286 pub fn mstscllow(&self) -> MstscllowR {
287 MstscllowR::new((self.bits & 7) as u8)
288 }
289 #[doc = "Bits 4:6 - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH."]
290 #[inline(always)]
291 pub fn mstsclhigh(&self) -> MstsclhighR {
292 MstsclhighR::new(((self.bits >> 4) & 7) as u8)
293 }
294}
295#[cfg(feature = "debug")]
296impl core::fmt::Debug for R {
297 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
298 f.debug_struct("MSTTIME")
299 .field("mstscllow", &self.mstscllow())
300 .field("mstsclhigh", &self.mstsclhigh())
301 .finish()
302 }
303}
304impl W {
305 #[doc = "Bits 0:2 - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW."]
306 #[inline(always)]
307 pub fn mstscllow(&mut self) -> MstscllowW<MsttimeSpec> {
308 MstscllowW::new(self, 0)
309 }
310 #[doc = "Bits 4:6 - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH."]
311 #[inline(always)]
312 pub fn mstsclhigh(&mut self) -> MstsclhighW<MsttimeSpec> {
313 MstsclhighW::new(self, 4)
314 }
315}
316#[doc = "Master timing configuration.\n\nYou can [`read`](crate::Reg::read) this register and get [`msttime::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msttime::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
317pub struct MsttimeSpec;
318impl crate::RegisterSpec for MsttimeSpec {
319 type Ux = u32;
320}
321#[doc = "`read()` method returns [`msttime::R`](R) reader structure"]
322impl crate::Readable for MsttimeSpec {}
323#[doc = "`write(|w| ..)` method takes [`msttime::W`](W) writer structure"]
324impl crate::Writable for MsttimeSpec {
325 type Safety = crate::Unsafe;
326 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
327 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
328}
329#[doc = "`reset()` method sets MSTTIME to value 0x77"]
330impl crate::Resettable for MsttimeSpec {
331 const RESET_VALUE: u32 = 0x77;
332}