mimxrt685s_pac/gpio/
dirclr.rs

1#[doc = "Register `DIRCLR[%s]` writer"]
2pub type W = crate::W<DirclrSpec>;
3#[doc = "Field `DIRCLRP` writer - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."]
4pub type DirclrpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
5#[cfg(feature = "debug")]
6impl core::fmt::Debug for crate::generic::Reg<DirclrSpec> {
7    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
8        write!(f, "(not readable)")
9    }
10}
11impl W {
12    #[doc = "Bits 0:31 - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."]
13    #[inline(always)]
14    pub fn dirclrp(&mut self) -> DirclrpW<DirclrSpec> {
15        DirclrpW::new(self, 0)
16    }
17}
18#[doc = "Clear pin direction bits for port\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dirclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19pub struct DirclrSpec;
20impl crate::RegisterSpec for DirclrSpec {
21    type Ux = u32;
22}
23#[doc = "`write(|w| ..)` method takes [`dirclr::W`](W) writer structure"]
24impl crate::Writable for DirclrSpec {
25    type Safety = crate::Unsafe;
26    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
27    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
28}
29#[doc = "`reset()` method sets DIRCLR[%s]
30to value 0"]
31impl crate::Resettable for DirclrSpec {
32    const RESET_VALUE: u32 = 0;
33}
mimxrt685s_pac/gpio/dirclr.rs

mimxrt685s_pac/gpio/
dirclr.rs
