1#[repr(C)]
2#[cfg_attr(feature = "debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 sct0_in_sel: [Sct0InSel; 7],
6 _reserved1: [u8; 0xe4],
7 pint_sel: [PintSel; 8],
8 _reserved2: [u8; 0x20],
9 dsp_int_sel: [DspIntSel; 27],
10 _reserved3: [u8; 0x54],
11 dmac0_itrig_sel: [Dmac0ItrigSel; 33],
12 _reserved4: [u8; 0x7c],
13 dmac0_otrig_sel: [Dmac0OtrigSel; 4],
14 _reserved5: [u8; 0xf0],
15 dmac1_itrig_sel: [Dmac1ItrigSel; 33],
16 _reserved6: [u8; 0x7c],
17 dmac1_otrig_sel: [Dmac1OtrigSel; 4],
18 _reserved7: [u8; 0xf0],
19 ct32bit_cap: [Ct32bitCap; 5],
20 _reserved8: [u8; 0xb0],
21 fmeasure_ch_sel: [FmeasureChSel; 2],
22 _reserved9: [u8; 0x38],
23 dmac0_req_ena0: Dmac0ReqEna0,
24 _reserved10: [u8; 0x04],
25 dmac0_req_ena0_set: Dmac0ReqEna0Set,
26 _reserved11: [u8; 0x04],
27 dmac0_req_ena0_clr: Dmac0ReqEna0Clr,
28 _reserved12: [u8; 0x0c],
29 dmac1_req_ena0: Dmac1ReqEna0,
30 _reserved13: [u8; 0x04],
31 dmac1_req_ena0_set: Dmac1ReqEna0Set,
32 _reserved14: [u8; 0x04],
33 dmac1_req_ena0_clr: Dmac1ReqEna0Clr,
34 _reserved15: [u8; 0x0c],
35 dmac0_itrig_ena0: Dmac0ItrigEna0,
36 _reserved16: [u8; 0x04],
37 dmac0_itrig_ena0_set: Dmac0ItrigEna0Set,
38 _reserved17: [u8; 0x04],
39 dmac0_itrig_ena0_clr: Dmac0ItrigEna0Clr,
40 _reserved18: [u8; 0x0c],
41 dmac1_itrig_ena0: Dmac1ItrigEna0,
42 _reserved19: [u8; 0x04],
43 dmac1_itrig_ena0_set: Dmac1ItrigEna0Set,
44 _reserved20: [u8; 0x04],
45 dmac1_itrig_ena0_clr: Dmac1ItrigEna0Clr,
46}
47impl RegisterBlock {
48 #[doc = "0x00..0x1c - SCT Peripheral Input Multiplexers N"]
49 #[inline(always)]
50 pub const fn sct0_in_sel(&self, n: usize) -> &Sct0InSel {
51 &self.sct0_in_sel[n]
52 }
53 #[doc = "Iterator for array of:"]
54 #[doc = "0x00..0x1c - SCT Peripheral Input Multiplexers N"]
55 #[inline(always)]
56 pub fn sct0_in_sel_iter(&self) -> impl Iterator<Item = &Sct0InSel> {
57 self.sct0_in_sel.iter()
58 }
59 #[doc = "0x100..0x120 - GPIO Pin Input Multiplexer N"]
60 #[inline(always)]
61 pub const fn pint_sel(&self, n: usize) -> &PintSel {
62 &self.pint_sel[n]
63 }
64 #[doc = "Iterator for array of:"]
65 #[doc = "0x100..0x120 - GPIO Pin Input Multiplexer N"]
66 #[inline(always)]
67 pub fn pint_sel_iter(&self) -> impl Iterator<Item = &PintSel> {
68 self.pint_sel.iter()
69 }
70 #[doc = "0x140..0x1ac - DSP Interrupt Input Multiplexers N"]
71 #[inline(always)]
72 pub const fn dsp_int_sel(&self, n: usize) -> &DspIntSel {
73 &self.dsp_int_sel[n]
74 }
75 #[doc = "Iterator for array of:"]
76 #[doc = "0x140..0x1ac - DSP Interrupt Input Multiplexers N"]
77 #[inline(always)]
78 pub fn dsp_int_sel_iter(&self) -> impl Iterator<Item = &DspIntSel> {
79 self.dsp_int_sel.iter()
80 }
81 #[doc = "0x200..0x284 - DMAC0 Input Trigger Multiplexers N"]
82 #[inline(always)]
83 pub const fn dmac0_itrig_sel(&self, n: usize) -> &Dmac0ItrigSel {
84 &self.dmac0_itrig_sel[n]
85 }
86 #[doc = "Iterator for array of:"]
87 #[doc = "0x200..0x284 - DMAC0 Input Trigger Multiplexers N"]
88 #[inline(always)]
89 pub fn dmac0_itrig_sel_iter(&self) -> impl Iterator<Item = &Dmac0ItrigSel> {
90 self.dmac0_itrig_sel.iter()
91 }
92 #[doc = "0x300..0x310 - DMAC0 Output Trigger Multiplexers N"]
93 #[inline(always)]
94 pub const fn dmac0_otrig_sel(&self, n: usize) -> &Dmac0OtrigSel {
95 &self.dmac0_otrig_sel[n]
96 }
97 #[doc = "Iterator for array of:"]
98 #[doc = "0x300..0x310 - DMAC0 Output Trigger Multiplexers N"]
99 #[inline(always)]
100 pub fn dmac0_otrig_sel_iter(&self) -> impl Iterator<Item = &Dmac0OtrigSel> {
101 self.dmac0_otrig_sel.iter()
102 }
103 #[doc = "0x400..0x484 - DMAC1 Input Trigger Multiplexers N"]
104 #[inline(always)]
105 pub const fn dmac1_itrig_sel(&self, n: usize) -> &Dmac1ItrigSel {
106 &self.dmac1_itrig_sel[n]
107 }
108 #[doc = "Iterator for array of:"]
109 #[doc = "0x400..0x484 - DMAC1 Input Trigger Multiplexers N"]
110 #[inline(always)]
111 pub fn dmac1_itrig_sel_iter(&self) -> impl Iterator<Item = &Dmac1ItrigSel> {
112 self.dmac1_itrig_sel.iter()
113 }
114 #[doc = "0x500..0x510 - DMAC1 Output Trigger Multiplexers N"]
115 #[inline(always)]
116 pub const fn dmac1_otrig_sel(&self, n: usize) -> &Dmac1OtrigSel {
117 &self.dmac1_otrig_sel[n]
118 }
119 #[doc = "Iterator for array of:"]
120 #[doc = "0x500..0x510 - DMAC1 Output Trigger Multiplexers N"]
121 #[inline(always)]
122 pub fn dmac1_otrig_sel_iter(&self) -> impl Iterator<Item = &Dmac1OtrigSel> {
123 self.dmac1_otrig_sel.iter()
124 }
125 #[doc = "0x600..0x650 - CT32BITn Counter Timer Capture Trigger Multiplexers"]
126 #[inline(always)]
127 pub const fn ct32bit_cap(&self, n: usize) -> &Ct32bitCap {
128 &self.ct32bit_cap[n]
129 }
130 #[doc = "Iterator for array of:"]
131 #[doc = "0x600..0x650 - CT32BITn Counter Timer Capture Trigger Multiplexers"]
132 #[inline(always)]
133 pub fn ct32bit_cap_iter(&self) -> impl Iterator<Item = &Ct32bitCap> {
134 self.ct32bit_cap.iter()
135 }
136 #[doc = "0x700..0x708 - Frequency Measurement Input Channel Multiplexers"]
137 #[inline(always)]
138 pub const fn fmeasure_ch_sel(&self, n: usize) -> &FmeasureChSel {
139 &self.fmeasure_ch_sel[n]
140 }
141 #[doc = "Iterator for array of:"]
142 #[doc = "0x700..0x708 - Frequency Measurement Input Channel Multiplexers"]
143 #[inline(always)]
144 pub fn fmeasure_ch_sel_iter(&self) -> impl Iterator<Item = &FmeasureChSel> {
145 self.fmeasure_ch_sel.iter()
146 }
147 #[doc = "0x740 - DMAC0 request enable 0"]
148 #[inline(always)]
149 pub const fn dmac0_req_ena0(&self) -> &Dmac0ReqEna0 {
150 &self.dmac0_req_ena0
151 }
152 #[doc = "0x748 - DMAC0 request enable set 0"]
153 #[inline(always)]
154 pub const fn dmac0_req_ena0_set(&self) -> &Dmac0ReqEna0Set {
155 &self.dmac0_req_ena0_set
156 }
157 #[doc = "0x750 - DMAC0 request enable clear 0"]
158 #[inline(always)]
159 pub const fn dmac0_req_ena0_clr(&self) -> &Dmac0ReqEna0Clr {
160 &self.dmac0_req_ena0_clr
161 }
162 #[doc = "0x760 - DMAC1 request enable 0"]
163 #[inline(always)]
164 pub const fn dmac1_req_ena0(&self) -> &Dmac1ReqEna0 {
165 &self.dmac1_req_ena0
166 }
167 #[doc = "0x768 - DMAC1 request enable set 0"]
168 #[inline(always)]
169 pub const fn dmac1_req_ena0_set(&self) -> &Dmac1ReqEna0Set {
170 &self.dmac1_req_ena0_set
171 }
172 #[doc = "0x770 - DMAC1 request enable clear 0"]
173 #[inline(always)]
174 pub const fn dmac1_req_ena0_clr(&self) -> &Dmac1ReqEna0Clr {
175 &self.dmac1_req_ena0_clr
176 }
177 #[doc = "0x780 - DMAC0 input trigger enable 0"]
178 #[inline(always)]
179 pub const fn dmac0_itrig_ena0(&self) -> &Dmac0ItrigEna0 {
180 &self.dmac0_itrig_ena0
181 }
182 #[doc = "0x788 - DMAC0 input trigger enable set 0"]
183 #[inline(always)]
184 pub const fn dmac0_itrig_ena0_set(&self) -> &Dmac0ItrigEna0Set {
185 &self.dmac0_itrig_ena0_set
186 }
187 #[doc = "0x790 - DMAC0 input trigger enable clear 0"]
188 #[inline(always)]
189 pub const fn dmac0_itrig_ena0_clr(&self) -> &Dmac0ItrigEna0Clr {
190 &self.dmac0_itrig_ena0_clr
191 }
192 #[doc = "0x7a0 - DMAC1 input trigger enable 0"]
193 #[inline(always)]
194 pub const fn dmac1_itrig_ena0(&self) -> &Dmac1ItrigEna0 {
195 &self.dmac1_itrig_ena0
196 }
197 #[doc = "0x7a8 - DMAC1 input trigger enable set 0"]
198 #[inline(always)]
199 pub const fn dmac1_itrig_ena0_set(&self) -> &Dmac1ItrigEna0Set {
200 &self.dmac1_itrig_ena0_set
201 }
202 #[doc = "0x7b0 - DMAC1 input trigger enable clear 0"]
203 #[inline(always)]
204 pub const fn dmac1_itrig_ena0_clr(&self) -> &Dmac1ItrigEna0Clr {
205 &self.dmac1_itrig_ena0_clr
206 }
207}
208#[doc = "SCT0_IN_SEL (rw) register accessor: SCT Peripheral Input Multiplexers N\n\nYou can [`read`](crate::Reg::read) this register and get [`sct0_in_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sct0_in_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sct0_in_sel`]
209module"]
210#[doc(alias = "SCT0_IN_SEL")]
211pub type Sct0InSel = crate::Reg<sct0_in_sel::Sct0InSelSpec>;
212#[doc = "SCT Peripheral Input Multiplexers N"]
213pub mod sct0_in_sel;
214#[doc = "PINT_SEL (rw) register accessor: GPIO Pin Input Multiplexer N\n\nYou can [`read`](crate::Reg::read) this register and get [`pint_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pint_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pint_sel`]
215module"]
216#[doc(alias = "PINT_SEL")]
217pub type PintSel = crate::Reg<pint_sel::PintSelSpec>;
218#[doc = "GPIO Pin Input Multiplexer N"]
219pub mod pint_sel;
220#[doc = "DSP_INT_SEL (rw) register accessor: DSP Interrupt Input Multiplexers N\n\nYou can [`read`](crate::Reg::read) this register and get [`dsp_int_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dsp_int_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsp_int_sel`]
221module"]
222#[doc(alias = "DSP_INT_SEL")]
223pub type DspIntSel = crate::Reg<dsp_int_sel::DspIntSelSpec>;
224#[doc = "DSP Interrupt Input Multiplexers N"]
225pub mod dsp_int_sel;
226#[doc = "DMAC0_ITRIG_SEL (rw) register accessor: DMAC0 Input Trigger Multiplexers N\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac0_itrig_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_itrig_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac0_itrig_sel`]
227module"]
228#[doc(alias = "DMAC0_ITRIG_SEL")]
229pub type Dmac0ItrigSel = crate::Reg<dmac0_itrig_sel::Dmac0ItrigSelSpec>;
230#[doc = "DMAC0 Input Trigger Multiplexers N"]
231pub mod dmac0_itrig_sel;
232#[doc = "DMAC0_OTRIG_SEL (rw) register accessor: DMAC0 Output Trigger Multiplexers N\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac0_otrig_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_otrig_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac0_otrig_sel`]
233module"]
234#[doc(alias = "DMAC0_OTRIG_SEL")]
235pub type Dmac0OtrigSel = crate::Reg<dmac0_otrig_sel::Dmac0OtrigSelSpec>;
236#[doc = "DMAC0 Output Trigger Multiplexers N"]
237pub mod dmac0_otrig_sel;
238#[doc = "DMAC1_ITRIG_SEL (rw) register accessor: DMAC1 Input Trigger Multiplexers N\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac1_itrig_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac1_itrig_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac1_itrig_sel`]
239module"]
240#[doc(alias = "DMAC1_ITRIG_SEL")]
241pub type Dmac1ItrigSel = crate::Reg<dmac1_itrig_sel::Dmac1ItrigSelSpec>;
242#[doc = "DMAC1 Input Trigger Multiplexers N"]
243pub mod dmac1_itrig_sel;
244#[doc = "DMAC1_OTRIG_SEL (rw) register accessor: DMAC1 Output Trigger Multiplexers N\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac1_otrig_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac1_otrig_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac1_otrig_sel`]
245module"]
246#[doc(alias = "DMAC1_OTRIG_SEL")]
247pub type Dmac1OtrigSel = crate::Reg<dmac1_otrig_sel::Dmac1OtrigSelSpec>;
248#[doc = "DMAC1 Output Trigger Multiplexers N"]
249pub mod dmac1_otrig_sel;
250#[doc = "CT32BITn Counter Timer Capture Trigger Multiplexers"]
251pub use self::ct32bit_cap::Ct32bitCap;
252#[doc = r"Cluster"]
253#[doc = "CT32BITn Counter Timer Capture Trigger Multiplexers"]
254pub mod ct32bit_cap;
255#[doc = "FMEASURE_CH_SEL (rw) register accessor: Frequency Measurement Input Channel Multiplexers\n\nYou can [`read`](crate::Reg::read) this register and get [`fmeasure_ch_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fmeasure_ch_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmeasure_ch_sel`]
256module"]
257#[doc(alias = "FMEASURE_CH_SEL")]
258pub type FmeasureChSel = crate::Reg<fmeasure_ch_sel::FmeasureChSelSpec>;
259#[doc = "Frequency Measurement Input Channel Multiplexers"]
260pub mod fmeasure_ch_sel;
261#[doc = "DMAC0_REQ_ENA0 (rw) register accessor: DMAC0 request enable 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac0_req_ena0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_req_ena0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac0_req_ena0`]
262module"]
263#[doc(alias = "DMAC0_REQ_ENA0")]
264pub type Dmac0ReqEna0 = crate::Reg<dmac0_req_ena0::Dmac0ReqEna0Spec>;
265#[doc = "DMAC0 request enable 0"]
266pub mod dmac0_req_ena0;
267#[doc = "DMAC0_REQ_ENA0_SET (w) register accessor: DMAC0 request enable set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_req_ena0_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac0_req_ena0_set`]
268module"]
269#[doc(alias = "DMAC0_REQ_ENA0_SET")]
270pub type Dmac0ReqEna0Set = crate::Reg<dmac0_req_ena0_set::Dmac0ReqEna0SetSpec>;
271#[doc = "DMAC0 request enable set 0"]
272pub mod dmac0_req_ena0_set;
273#[doc = "DMAC0_REQ_ENA0_CLR (w) register accessor: DMAC0 request enable clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_req_ena0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac0_req_ena0_clr`]
274module"]
275#[doc(alias = "DMAC0_REQ_ENA0_CLR")]
276pub type Dmac0ReqEna0Clr = crate::Reg<dmac0_req_ena0_clr::Dmac0ReqEna0ClrSpec>;
277#[doc = "DMAC0 request enable clear 0"]
278pub mod dmac0_req_ena0_clr;
279#[doc = "DMAC1_REQ_ENA0 (rw) register accessor: DMAC1 request enable 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac1_req_ena0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac1_req_ena0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac1_req_ena0`]
280module"]
281#[doc(alias = "DMAC1_REQ_ENA0")]
282pub type Dmac1ReqEna0 = crate::Reg<dmac1_req_ena0::Dmac1ReqEna0Spec>;
283#[doc = "DMAC1 request enable 0"]
284pub mod dmac1_req_ena0;
285#[doc = "DMAC1_REQ_ENA0_SET (w) register accessor: DMAC1 request enable set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac1_req_ena0_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac1_req_ena0_set`]
286module"]
287#[doc(alias = "DMAC1_REQ_ENA0_SET")]
288pub type Dmac1ReqEna0Set = crate::Reg<dmac1_req_ena0_set::Dmac1ReqEna0SetSpec>;
289#[doc = "DMAC1 request enable set 0"]
290pub mod dmac1_req_ena0_set;
291#[doc = "DMAC1_REQ_ENA0_CLR (w) register accessor: DMAC1 request enable clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac1_req_ena0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac1_req_ena0_clr`]
292module"]
293#[doc(alias = "DMAC1_REQ_ENA0_CLR")]
294pub type Dmac1ReqEna0Clr = crate::Reg<dmac1_req_ena0_clr::Dmac1ReqEna0ClrSpec>;
295#[doc = "DMAC1 request enable clear 0"]
296pub mod dmac1_req_ena0_clr;
297#[doc = "DMAC0_ITRIG_ENA0 (rw) register accessor: DMAC0 input trigger enable 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac0_itrig_ena0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_itrig_ena0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac0_itrig_ena0`]
298module"]
299#[doc(alias = "DMAC0_ITRIG_ENA0")]
300pub type Dmac0ItrigEna0 = crate::Reg<dmac0_itrig_ena0::Dmac0ItrigEna0Spec>;
301#[doc = "DMAC0 input trigger enable 0"]
302pub mod dmac0_itrig_ena0;
303#[doc = "DMAC0_ITRIG_ENA0_SET (w) register accessor: DMAC0 input trigger enable set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_itrig_ena0_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac0_itrig_ena0_set`]
304module"]
305#[doc(alias = "DMAC0_ITRIG_ENA0_SET")]
306pub type Dmac0ItrigEna0Set = crate::Reg<dmac0_itrig_ena0_set::Dmac0ItrigEna0SetSpec>;
307#[doc = "DMAC0 input trigger enable set 0"]
308pub mod dmac0_itrig_ena0_set;
309#[doc = "DMAC0_ITRIG_ENA0_CLR (w) register accessor: DMAC0 input trigger enable clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_itrig_ena0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac0_itrig_ena0_clr`]
310module"]
311#[doc(alias = "DMAC0_ITRIG_ENA0_CLR")]
312pub type Dmac0ItrigEna0Clr = crate::Reg<dmac0_itrig_ena0_clr::Dmac0ItrigEna0ClrSpec>;
313#[doc = "DMAC0 input trigger enable clear 0"]
314pub mod dmac0_itrig_ena0_clr;
315#[doc = "DMAC1_ITRIG_ENA0 (rw) register accessor: DMAC1 input trigger enable 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac1_itrig_ena0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac1_itrig_ena0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac1_itrig_ena0`]
316module"]
317#[doc(alias = "DMAC1_ITRIG_ENA0")]
318pub type Dmac1ItrigEna0 = crate::Reg<dmac1_itrig_ena0::Dmac1ItrigEna0Spec>;
319#[doc = "DMAC1 input trigger enable 0"]
320pub mod dmac1_itrig_ena0;
321#[doc = "DMAC1_ITRIG_ENA0_SET (w) register accessor: DMAC1 input trigger enable set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac1_itrig_ena0_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac1_itrig_ena0_set`]
322module"]
323#[doc(alias = "DMAC1_ITRIG_ENA0_SET")]
324pub type Dmac1ItrigEna0Set = crate::Reg<dmac1_itrig_ena0_set::Dmac1ItrigEna0SetSpec>;
325#[doc = "DMAC1 input trigger enable set 0"]
326pub mod dmac1_itrig_ena0_set;
327#[doc = "DMAC1_ITRIG_ENA0_CLR (w) register accessor: DMAC1 input trigger enable clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac1_itrig_ena0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac1_itrig_ena0_clr`]
328module"]
329#[doc(alias = "DMAC1_ITRIG_ENA0_CLR")]
330pub type Dmac1ItrigEna0Clr = crate::Reg<dmac1_itrig_ena0_clr::Dmac1ItrigEna0ClrSpec>;
331#[doc = "DMAC1 input trigger enable clear 0"]
332pub mod dmac1_itrig_ena0_clr;