1#[repr(C)]
2#[cfg_attr(feature = "debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 _reserved0: [u8; 0x0c00],
6 cfg1: Cfg1,
7 cfg2: Cfg2,
8 stat: Stat,
9 _reserved3: [u8; 0x10],
10 div: Div,
11 secchannel: (),
12 _reserved5: [u8; 0x01e0],
13 fifocfg: Fifocfg,
14 fifostat: Fifostat,
15 fifotrig: Fifotrig,
16 _reserved8: [u8; 0x04],
17 fifointenset: Fifointenset,
18 fifointenclr: Fifointenclr,
19 fifointstat: Fifointstat,
20 _reserved11: [u8; 0x04],
21 fifowr: Fifowr,
22 fifowr48h: Fifowr48h,
23 _reserved13: [u8; 0x08],
24 fiford: Fiford,
25 fiford48h: Fiford48h,
26 _reserved15: [u8; 0x08],
27 fifordnopop: Fifordnopop,
28 fiford48hnopop: Fiford48hnopop,
29 fifosize: Fifosize,
30 _reserved18: [u8; 0x01b0],
31 id: Id,
32}
33impl RegisterBlock {
34 #[doc = "0xc00 - Configuration register 1 for the primary channel pair."]
35 #[inline(always)]
36 pub const fn cfg1(&self) -> &Cfg1 {
37 &self.cfg1
38 }
39 #[doc = "0xc04 - Configuration register 2 for the primary channel pair."]
40 #[inline(always)]
41 pub const fn cfg2(&self) -> &Cfg2 {
42 &self.cfg2
43 }
44 #[doc = "0xc08 - Status register for the primary channel pair."]
45 #[inline(always)]
46 pub const fn stat(&self) -> &Stat {
47 &self.stat
48 }
49 #[doc = "0xc1c - Clock divider, used by all channel pairs."]
50 #[inline(always)]
51 pub const fn div(&self) -> &Div {
52 &self.div
53 }
54 #[doc = "0xc20..0xc44 - no description available"]
55 #[inline(always)]
56 pub const fn secchannel(&self, n: usize) -> &Secchannel {
57 #[allow(clippy::no_effect)]
58 [(); 3][n];
59 unsafe {
60 &*core::ptr::from_ref(self)
61 .cast::<u8>()
62 .add(3104)
63 .add(32 * n)
64 .cast()
65 }
66 }
67 #[doc = "Iterator for array of:"]
68 #[doc = "0xc20..0xc44 - no description available"]
69 #[inline(always)]
70 pub fn secchannel_iter(&self) -> impl Iterator<Item = &Secchannel> {
71 (0..3).map(move |n| unsafe {
72 &*core::ptr::from_ref(self)
73 .cast::<u8>()
74 .add(3104)
75 .add(32 * n)
76 .cast()
77 })
78 }
79 #[doc = "0xe00 - FIFO configuration and enable register."]
80 #[inline(always)]
81 pub const fn fifocfg(&self) -> &Fifocfg {
82 &self.fifocfg
83 }
84 #[doc = "0xe04 - FIFO status register."]
85 #[inline(always)]
86 pub const fn fifostat(&self) -> &Fifostat {
87 &self.fifostat
88 }
89 #[doc = "0xe08 - FIFO trigger settings for interrupt and DMA request."]
90 #[inline(always)]
91 pub const fn fifotrig(&self) -> &Fifotrig {
92 &self.fifotrig
93 }
94 #[doc = "0xe10 - FIFO interrupt enable set (enable) and read register."]
95 #[inline(always)]
96 pub const fn fifointenset(&self) -> &Fifointenset {
97 &self.fifointenset
98 }
99 #[doc = "0xe14 - FIFO interrupt enable clear (disable) and read register."]
100 #[inline(always)]
101 pub const fn fifointenclr(&self) -> &Fifointenclr {
102 &self.fifointenclr
103 }
104 #[doc = "0xe18 - FIFO interrupt status register."]
105 #[inline(always)]
106 pub const fn fifointstat(&self) -> &Fifointstat {
107 &self.fifointstat
108 }
109 #[doc = "0xe20 - FIFO write data."]
110 #[inline(always)]
111 pub const fn fifowr(&self) -> &Fifowr {
112 &self.fifowr
113 }
114 #[doc = "0xe24 - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."]
115 #[inline(always)]
116 pub const fn fifowr48h(&self) -> &Fifowr48h {
117 &self.fifowr48h
118 }
119 #[doc = "0xe30 - FIFO read data."]
120 #[inline(always)]
121 pub const fn fiford(&self) -> &Fiford {
122 &self.fiford
123 }
124 #[doc = "0xe34 - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."]
125 #[inline(always)]
126 pub const fn fiford48h(&self) -> &Fiford48h {
127 &self.fiford48h
128 }
129 #[doc = "0xe40 - FIFO data read with no FIFO pop."]
130 #[inline(always)]
131 pub const fn fifordnopop(&self) -> &Fifordnopop {
132 &self.fifordnopop
133 }
134 #[doc = "0xe44 - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."]
135 #[inline(always)]
136 pub const fn fiford48hnopop(&self) -> &Fiford48hnopop {
137 &self.fiford48hnopop
138 }
139 #[doc = "0xe48 - FIFO size register"]
140 #[inline(always)]
141 pub const fn fifosize(&self) -> &Fifosize {
142 &self.fifosize
143 }
144 #[doc = "0xffc - I2S Module identification"]
145 #[inline(always)]
146 pub const fn id(&self) -> &Id {
147 &self.id
148 }
149}
150#[doc = "CFG1 (rw) register accessor: Configuration register 1 for the primary channel pair.\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg1`]
151module"]
152#[doc(alias = "CFG1")]
153pub type Cfg1 = crate::Reg<cfg1::Cfg1Spec>;
154#[doc = "Configuration register 1 for the primary channel pair."]
155pub mod cfg1;
156#[doc = "no description available"]
157pub use self::secchannel::Secchannel;
158#[doc = r"Cluster"]
159#[doc = "no description available"]
160pub mod secchannel;
161#[doc = "CFG2 (rw) register accessor: Configuration register 2 for the primary channel pair.\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg2`]
162module"]
163#[doc(alias = "CFG2")]
164pub type Cfg2 = crate::Reg<cfg2::Cfg2Spec>;
165#[doc = "Configuration register 2 for the primary channel pair."]
166pub mod cfg2;
167#[doc = "STAT (rw) register accessor: Status register for the primary channel pair.\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
168module"]
169#[doc(alias = "STAT")]
170pub type Stat = crate::Reg<stat::StatSpec>;
171#[doc = "Status register for the primary channel pair."]
172pub mod stat;
173#[doc = "DIV (rw) register accessor: Clock divider, used by all channel pairs.\n\nYou can [`read`](crate::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div`]
174module"]
175#[doc(alias = "DIV")]
176pub type Div = crate::Reg<div::DivSpec>;
177#[doc = "Clock divider, used by all channel pairs."]
178pub mod div;
179#[doc = "FIFOCFG (rw) register accessor: FIFO configuration and enable register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifocfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifocfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifocfg`]
180module"]
181#[doc(alias = "FIFOCFG")]
182pub type Fifocfg = crate::Reg<fifocfg::FifocfgSpec>;
183#[doc = "FIFO configuration and enable register."]
184pub mod fifocfg;
185#[doc = "FIFOSTAT (rw) register accessor: FIFO status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifostat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifostat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifostat`]
186module"]
187#[doc(alias = "FIFOSTAT")]
188pub type Fifostat = crate::Reg<fifostat::FifostatSpec>;
189#[doc = "FIFO status register."]
190pub mod fifostat;
191#[doc = "FIFOTRIG (rw) register accessor: FIFO trigger settings for interrupt and DMA request.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifotrig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifotrig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifotrig`]
192module"]
193#[doc(alias = "FIFOTRIG")]
194pub type Fifotrig = crate::Reg<fifotrig::FifotrigSpec>;
195#[doc = "FIFO trigger settings for interrupt and DMA request."]
196pub mod fifotrig;
197#[doc = "FIFOINTENSET (rw) register accessor: FIFO interrupt enable set (enable) and read register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifointenset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifointenset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifointenset`]
198module"]
199#[doc(alias = "FIFOINTENSET")]
200pub type Fifointenset = crate::Reg<fifointenset::FifointensetSpec>;
201#[doc = "FIFO interrupt enable set (enable) and read register."]
202pub mod fifointenset;
203#[doc = "FIFOINTENCLR (rw) register accessor: FIFO interrupt enable clear (disable) and read register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifointenclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifointenclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifointenclr`]
204module"]
205#[doc(alias = "FIFOINTENCLR")]
206pub type Fifointenclr = crate::Reg<fifointenclr::FifointenclrSpec>;
207#[doc = "FIFO interrupt enable clear (disable) and read register."]
208pub mod fifointenclr;
209#[doc = "FIFOINTSTAT (r) register accessor: FIFO interrupt status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifointstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifointstat`]
210module"]
211#[doc(alias = "FIFOINTSTAT")]
212pub type Fifointstat = crate::Reg<fifointstat::FifointstatSpec>;
213#[doc = "FIFO interrupt status register."]
214pub mod fifointstat;
215#[doc = "FIFOWR (w) register accessor: FIFO write data.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifowr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifowr`]
216module"]
217#[doc(alias = "FIFOWR")]
218pub type Fifowr = crate::Reg<fifowr::FifowrSpec>;
219#[doc = "FIFO write data."]
220pub mod fifowr;
221#[doc = "FIFOWR48H (w) register accessor: FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifowr48h::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifowr48h`]
222module"]
223#[doc(alias = "FIFOWR48H")]
224pub type Fifowr48h = crate::Reg<fifowr48h::Fifowr48hSpec>;
225#[doc = "FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."]
226pub mod fifowr48h;
227#[doc = "FIFORD (r) register accessor: FIFO read data.\n\nYou can [`read`](crate::Reg::read) this register and get [`fiford::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fiford`]
228module"]
229#[doc(alias = "FIFORD")]
230pub type Fiford = crate::Reg<fiford::FifordSpec>;
231#[doc = "FIFO read data."]
232pub mod fiford;
233#[doc = "FIFORD48H (r) register accessor: FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.\n\nYou can [`read`](crate::Reg::read) this register and get [`fiford48h::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fiford48h`]
234module"]
235#[doc(alias = "FIFORD48H")]
236pub type Fiford48h = crate::Reg<fiford48h::Fiford48hSpec>;
237#[doc = "FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."]
238pub mod fiford48h;
239#[doc = "FIFORDNOPOP (r) register accessor: FIFO data read with no FIFO pop.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifordnopop::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifordnopop`]
240module"]
241#[doc(alias = "FIFORDNOPOP")]
242pub type Fifordnopop = crate::Reg<fifordnopop::FifordnopopSpec>;
243#[doc = "FIFO data read with no FIFO pop."]
244pub mod fifordnopop;
245#[doc = "FIFORD48HNOPOP (r) register accessor: FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.\n\nYou can [`read`](crate::Reg::read) this register and get [`fiford48hnopop::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fiford48hnopop`]
246module"]
247#[doc(alias = "FIFORD48HNOPOP")]
248pub type Fiford48hnopop = crate::Reg<fiford48hnopop::Fiford48hnopopSpec>;
249#[doc = "FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."]
250pub mod fiford48hnopop;
251#[doc = "FIFOSIZE (rw) register accessor: FIFO size register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifosize::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifosize::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifosize`]
252module"]
253#[doc(alias = "FIFOSIZE")]
254pub type Fifosize = crate::Reg<fifosize::FifosizeSpec>;
255#[doc = "FIFO size register"]
256pub mod fifosize;
257#[doc = "ID (r) register accessor: I2S Module identification\n\nYou can [`read`](crate::Reg::read) this register and get [`id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id`]
258module"]
259#[doc(alias = "ID")]
260pub type Id = crate::Reg<id::IdSpec>;
261#[doc = "I2S Module identification"]
262pub mod id;