1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - USART Configuration"]
5 pub cfg: CFG,
6 #[doc = "0x04 - USART Control"]
7 pub ctl: CTL,
8 #[doc = "0x08 - USART Status"]
9 pub stat: STAT,
10 #[doc = "0x0c - Interrupt Enable Read and Set for USART (not FIFO) Status"]
11 pub intenset: INTENSET,
12 #[doc = "0x10 - Interrupt Enable Clear"]
13 pub intenclr: INTENCLR,
14 _reserved5: [u8; 0x0c],
15 #[doc = "0x20 - Baud Rate Generator"]
16 pub brg: BRG,
17 #[doc = "0x24 - Interrupt Status"]
18 pub intstat: INTSTAT,
19 #[doc = "0x28 - Oversample Selection Register for Asynchronous Communication"]
20 pub osr: OSR,
21 #[doc = "0x2c - Address Register for Automatic Address Matching"]
22 pub addr: ADDR,
23 _reserved9: [u8; 0x0dd0],
24 #[doc = "0xe00 - FIFO Configuration"]
25 pub fifocfg: FIFOCFG,
26 #[doc = "0xe04 - FIFO Status"]
27 pub fifostat: FIFOSTAT,
28 #[doc = "0xe08 - FIFO Trigger Settings for Interrupt and DMA Request"]
29 pub fifotrig: FIFOTRIG,
30 _reserved12: [u8; 0x04],
31 #[doc = "0xe10 - FIFO Interrupt Enable"]
32 pub fifointenset: FIFOINTENSET,
33 #[doc = "0xe14 - FIFO Interrupt Enable Clear"]
34 pub fifointenclr: FIFOINTENCLR,
35 #[doc = "0xe18 - FIFO Interrupt Status"]
36 pub fifointstat: FIFOINTSTAT,
37 _reserved15: [u8; 0x04],
38 #[doc = "0xe20 - FIFO Write Data"]
39 pub fifowr: FIFOWR,
40 _reserved16: [u8; 0x0c],
41 #[doc = "0xe30 - FIFO Read Data"]
42 pub fiford: FIFORD,
43 _reserved17: [u8; 0x0c],
44 #[doc = "0xe40 - FIFO Data Read with No FIFO Pop"]
45 pub fifordnopop: FIFORDNOPOP,
46 _reserved18: [u8; 0x04],
47 #[doc = "0xe48 - FIFO Size"]
48 pub fifosize: FIFOSIZE,
49 _reserved19: [u8; 0x01b0],
50 #[doc = "0xffc - Peripheral Identification"]
51 pub id: ID,
52}
53#[doc = "CFG (rw) register accessor: an alias for `Reg<CFG_SPEC>`"]
54pub type CFG = crate::Reg<cfg::CFG_SPEC>;
55#[doc = "USART Configuration"]
56pub mod cfg;
57#[doc = "CTL (rw) register accessor: an alias for `Reg<CTL_SPEC>`"]
58pub type CTL = crate::Reg<ctl::CTL_SPEC>;
59#[doc = "USART Control"]
60pub mod ctl;
61#[doc = "STAT (rw) register accessor: an alias for `Reg<STAT_SPEC>`"]
62pub type STAT = crate::Reg<stat::STAT_SPEC>;
63#[doc = "USART Status"]
64pub mod stat;
65#[doc = "INTENSET (rw) register accessor: an alias for `Reg<INTENSET_SPEC>`"]
66pub type INTENSET = crate::Reg<intenset::INTENSET_SPEC>;
67#[doc = "Interrupt Enable Read and Set for USART (not FIFO) Status"]
68pub mod intenset;
69#[doc = "INTENCLR (w) register accessor: an alias for `Reg<INTENCLR_SPEC>`"]
70pub type INTENCLR = crate::Reg<intenclr::INTENCLR_SPEC>;
71#[doc = "Interrupt Enable Clear"]
72pub mod intenclr;
73#[doc = "BRG (rw) register accessor: an alias for `Reg<BRG_SPEC>`"]
74pub type BRG = crate::Reg<brg::BRG_SPEC>;
75#[doc = "Baud Rate Generator"]
76pub mod brg;
77#[doc = "INTSTAT (r) register accessor: an alias for `Reg<INTSTAT_SPEC>`"]
78pub type INTSTAT = crate::Reg<intstat::INTSTAT_SPEC>;
79#[doc = "Interrupt Status"]
80pub mod intstat;
81#[doc = "OSR (rw) register accessor: an alias for `Reg<OSR_SPEC>`"]
82pub type OSR = crate::Reg<osr::OSR_SPEC>;
83#[doc = "Oversample Selection Register for Asynchronous Communication"]
84pub mod osr;
85#[doc = "ADDR (rw) register accessor: an alias for `Reg<ADDR_SPEC>`"]
86pub type ADDR = crate::Reg<addr::ADDR_SPEC>;
87#[doc = "Address Register for Automatic Address Matching"]
88pub mod addr;
89#[doc = "FIFOCFG (rw) register accessor: an alias for `Reg<FIFOCFG_SPEC>`"]
90pub type FIFOCFG = crate::Reg<fifocfg::FIFOCFG_SPEC>;
91#[doc = "FIFO Configuration"]
92pub mod fifocfg;
93#[doc = "FIFOSTAT (rw) register accessor: an alias for `Reg<FIFOSTAT_SPEC>`"]
94pub type FIFOSTAT = crate::Reg<fifostat::FIFOSTAT_SPEC>;
95#[doc = "FIFO Status"]
96pub mod fifostat;
97#[doc = "FIFOTRIG (rw) register accessor: an alias for `Reg<FIFOTRIG_SPEC>`"]
98pub type FIFOTRIG = crate::Reg<fifotrig::FIFOTRIG_SPEC>;
99#[doc = "FIFO Trigger Settings for Interrupt and DMA Request"]
100pub mod fifotrig;
101#[doc = "FIFOINTENSET (rw) register accessor: an alias for `Reg<FIFOINTENSET_SPEC>`"]
102pub type FIFOINTENSET = crate::Reg<fifointenset::FIFOINTENSET_SPEC>;
103#[doc = "FIFO Interrupt Enable"]
104pub mod fifointenset;
105#[doc = "FIFOINTENCLR (rw) register accessor: an alias for `Reg<FIFOINTENCLR_SPEC>`"]
106pub type FIFOINTENCLR = crate::Reg<fifointenclr::FIFOINTENCLR_SPEC>;
107#[doc = "FIFO Interrupt Enable Clear"]
108pub mod fifointenclr;
109#[doc = "FIFOINTSTAT (r) register accessor: an alias for `Reg<FIFOINTSTAT_SPEC>`"]
110pub type FIFOINTSTAT = crate::Reg<fifointstat::FIFOINTSTAT_SPEC>;
111#[doc = "FIFO Interrupt Status"]
112pub mod fifointstat;
113#[doc = "FIFOWR (w) register accessor: an alias for `Reg<FIFOWR_SPEC>`"]
114pub type FIFOWR = crate::Reg<fifowr::FIFOWR_SPEC>;
115#[doc = "FIFO Write Data"]
116pub mod fifowr;
117#[doc = "FIFORD (r) register accessor: an alias for `Reg<FIFORD_SPEC>`"]
118pub type FIFORD = crate::Reg<fiford::FIFORD_SPEC>;
119#[doc = "FIFO Read Data"]
120pub mod fiford;
121#[doc = "FIFORDNOPOP (r) register accessor: an alias for `Reg<FIFORDNOPOP_SPEC>`"]
122pub type FIFORDNOPOP = crate::Reg<fifordnopop::FIFORDNOPOP_SPEC>;
123#[doc = "FIFO Data Read with No FIFO Pop"]
124pub mod fifordnopop;
125#[doc = "FIFOSIZE (r) register accessor: an alias for `Reg<FIFOSIZE_SPEC>`"]
126pub type FIFOSIZE = crate::Reg<fifosize::FIFOSIZE_SPEC>;
127#[doc = "FIFO Size"]
128pub mod fifosize;
129#[doc = "ID (r) register accessor: an alias for `Reg<ID_SPEC>`"]
130pub type ID = crate::Reg<id::ID_SPEC>;
131#[doc = "Peripheral Identification"]
132pub mod id;