mimxrt595s/usbphy/
pll_sic_clr.rs

1#[doc = "Register `PLL_SIC_CLR` reader"]
2pub struct R(crate::R<PLL_SIC_CLR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PLL_SIC_CLR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PLL_SIC_CLR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PLL_SIC_CLR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PLL_SIC_CLR` writer"]
17pub struct W(crate::W<PLL_SIC_CLR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PLL_SIC_CLR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PLL_SIC_CLR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PLL_SIC_CLR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PLL_EN_USB_CLKS` reader - PLL_EN_USB_CLKS"]
38pub type PLL_EN_USB_CLKS_R = crate::BitReader<PLL_EN_USB_CLKS_A>;
39#[doc = "PLL_EN_USB_CLKS\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum PLL_EN_USB_CLKS_A {
42    #[doc = "0: No effect"]
43    DISABLE = 0,
44    #[doc = "1: Clears the corresponding bit"]
45    ENABLE = 1,
46}
47impl From<PLL_EN_USB_CLKS_A> for bool {
48    #[inline(always)]
49    fn from(variant: PLL_EN_USB_CLKS_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl PLL_EN_USB_CLKS_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> PLL_EN_USB_CLKS_A {
57        match self.bits {
58            false => PLL_EN_USB_CLKS_A::DISABLE,
59            true => PLL_EN_USB_CLKS_A::ENABLE,
60        }
61    }
62    #[doc = "Checks if the value of the field is `DISABLE`"]
63    #[inline(always)]
64    pub fn is_disable(&self) -> bool {
65        *self == PLL_EN_USB_CLKS_A::DISABLE
66    }
67    #[doc = "Checks if the value of the field is `ENABLE`"]
68    #[inline(always)]
69    pub fn is_enable(&self) -> bool {
70        *self == PLL_EN_USB_CLKS_A::ENABLE
71    }
72}
73#[doc = "Field `PLL_EN_USB_CLKS` writer - PLL_EN_USB_CLKS"]
74pub type PLL_EN_USB_CLKS_W<'a, const O: u8> =
75    crate::BitWriter<'a, u32, PLL_SIC_CLR_SPEC, PLL_EN_USB_CLKS_A, O>;
76impl<'a, const O: u8> PLL_EN_USB_CLKS_W<'a, O> {
77    #[doc = "No effect"]
78    #[inline(always)]
79    pub fn disable(self) -> &'a mut W {
80        self.variant(PLL_EN_USB_CLKS_A::DISABLE)
81    }
82    #[doc = "Clears the corresponding bit"]
83    #[inline(always)]
84    pub fn enable(self) -> &'a mut W {
85        self.variant(PLL_EN_USB_CLKS_A::ENABLE)
86    }
87}
88#[doc = "Field `PLL_POWER` reader - POWER"]
89pub type PLL_POWER_R = crate::BitReader<PLL_POWER_A>;
90#[doc = "POWER\n\nValue on reset: 0"]
91#[derive(Clone, Copy, Debug, PartialEq, Eq)]
92pub enum PLL_POWER_A {
93    #[doc = "0: No effect"]
94    DISABLE = 0,
95    #[doc = "1: Clears the corresponding bit"]
96    ENABLE = 1,
97}
98impl From<PLL_POWER_A> for bool {
99    #[inline(always)]
100    fn from(variant: PLL_POWER_A) -> Self {
101        variant as u8 != 0
102    }
103}
104impl PLL_POWER_R {
105    #[doc = "Get enumerated values variant"]
106    #[inline(always)]
107    pub fn variant(&self) -> PLL_POWER_A {
108        match self.bits {
109            false => PLL_POWER_A::DISABLE,
110            true => PLL_POWER_A::ENABLE,
111        }
112    }
113    #[doc = "Checks if the value of the field is `DISABLE`"]
114    #[inline(always)]
115    pub fn is_disable(&self) -> bool {
116        *self == PLL_POWER_A::DISABLE
117    }
118    #[doc = "Checks if the value of the field is `ENABLE`"]
119    #[inline(always)]
120    pub fn is_enable(&self) -> bool {
121        *self == PLL_POWER_A::ENABLE
122    }
123}
124#[doc = "Field `PLL_POWER` writer - POWER"]
125pub type PLL_POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, PLL_SIC_CLR_SPEC, PLL_POWER_A, O>;
126impl<'a, const O: u8> PLL_POWER_W<'a, O> {
127    #[doc = "No effect"]
128    #[inline(always)]
129    pub fn disable(self) -> &'a mut W {
130        self.variant(PLL_POWER_A::DISABLE)
131    }
132    #[doc = "Clears the corresponding bit"]
133    #[inline(always)]
134    pub fn enable(self) -> &'a mut W {
135        self.variant(PLL_POWER_A::ENABLE)
136    }
137}
138#[doc = "Field `PLL_ENABLE` reader - ENABLE"]
139pub type PLL_ENABLE_R = crate::BitReader<PLL_ENABLE_A>;
140#[doc = "ENABLE\n\nValue on reset: 1"]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum PLL_ENABLE_A {
143    #[doc = "0: No effect"]
144    DISABLE = 0,
145    #[doc = "1: Clears the corresponding bit"]
146    ENABLE = 1,
147}
148impl From<PLL_ENABLE_A> for bool {
149    #[inline(always)]
150    fn from(variant: PLL_ENABLE_A) -> Self {
151        variant as u8 != 0
152    }
153}
154impl PLL_ENABLE_R {
155    #[doc = "Get enumerated values variant"]
156    #[inline(always)]
157    pub fn variant(&self) -> PLL_ENABLE_A {
158        match self.bits {
159            false => PLL_ENABLE_A::DISABLE,
160            true => PLL_ENABLE_A::ENABLE,
161        }
162    }
163    #[doc = "Checks if the value of the field is `DISABLE`"]
164    #[inline(always)]
165    pub fn is_disable(&self) -> bool {
166        *self == PLL_ENABLE_A::DISABLE
167    }
168    #[doc = "Checks if the value of the field is `ENABLE`"]
169    #[inline(always)]
170    pub fn is_enable(&self) -> bool {
171        *self == PLL_ENABLE_A::ENABLE
172    }
173}
174#[doc = "Field `PLL_ENABLE` writer - ENABLE"]
175pub type PLL_ENABLE_W<'a, const O: u8> =
176    crate::BitWriter<'a, u32, PLL_SIC_CLR_SPEC, PLL_ENABLE_A, O>;
177impl<'a, const O: u8> PLL_ENABLE_W<'a, O> {
178    #[doc = "No effect"]
179    #[inline(always)]
180    pub fn disable(self) -> &'a mut W {
181        self.variant(PLL_ENABLE_A::DISABLE)
182    }
183    #[doc = "Clears the corresponding bit"]
184    #[inline(always)]
185    pub fn enable(self) -> &'a mut W {
186        self.variant(PLL_ENABLE_A::ENABLE)
187    }
188}
189#[doc = "Field `PLL_BYPASS` reader - Bypass USB PLL"]
190pub type PLL_BYPASS_R = crate::BitReader<PLL_BYPASS_A>;
191#[doc = "Bypass USB PLL\n\nValue on reset: 1"]
192#[derive(Clone, Copy, Debug, PartialEq, Eq)]
193pub enum PLL_BYPASS_A {
194    #[doc = "0: No effect"]
195    DISABLE = 0,
196    #[doc = "1: Clears the corresponding bit"]
197    ENABLE = 1,
198}
199impl From<PLL_BYPASS_A> for bool {
200    #[inline(always)]
201    fn from(variant: PLL_BYPASS_A) -> Self {
202        variant as u8 != 0
203    }
204}
205impl PLL_BYPASS_R {
206    #[doc = "Get enumerated values variant"]
207    #[inline(always)]
208    pub fn variant(&self) -> PLL_BYPASS_A {
209        match self.bits {
210            false => PLL_BYPASS_A::DISABLE,
211            true => PLL_BYPASS_A::ENABLE,
212        }
213    }
214    #[doc = "Checks if the value of the field is `DISABLE`"]
215    #[inline(always)]
216    pub fn is_disable(&self) -> bool {
217        *self == PLL_BYPASS_A::DISABLE
218    }
219    #[doc = "Checks if the value of the field is `ENABLE`"]
220    #[inline(always)]
221    pub fn is_enable(&self) -> bool {
222        *self == PLL_BYPASS_A::ENABLE
223    }
224}
225#[doc = "Field `PLL_BYPASS` writer - Bypass USB PLL"]
226pub type PLL_BYPASS_W<'a, const O: u8> =
227    crate::BitWriter<'a, u32, PLL_SIC_CLR_SPEC, PLL_BYPASS_A, O>;
228impl<'a, const O: u8> PLL_BYPASS_W<'a, O> {
229    #[doc = "No effect"]
230    #[inline(always)]
231    pub fn disable(self) -> &'a mut W {
232        self.variant(PLL_BYPASS_A::DISABLE)
233    }
234    #[doc = "Clears the corresponding bit"]
235    #[inline(always)]
236    pub fn enable(self) -> &'a mut W {
237        self.variant(PLL_BYPASS_A::ENABLE)
238    }
239}
240#[doc = "Field `REFBIAS_PWD_SEL` reader - REFBIAS_PWD_SEL"]
241pub type REFBIAS_PWD_SEL_R = crate::BitReader<REFBIAS_PWD_SEL_A>;
242#[doc = "REFBIAS_PWD_SEL\n\nValue on reset: 0"]
243#[derive(Clone, Copy, Debug, PartialEq, Eq)]
244pub enum REFBIAS_PWD_SEL_A {
245    #[doc = "0: No effect"]
246    DISABLE = 0,
247    #[doc = "1: Clears the corresponding bit"]
248    ENABLE = 1,
249}
250impl From<REFBIAS_PWD_SEL_A> for bool {
251    #[inline(always)]
252    fn from(variant: REFBIAS_PWD_SEL_A) -> Self {
253        variant as u8 != 0
254    }
255}
256impl REFBIAS_PWD_SEL_R {
257    #[doc = "Get enumerated values variant"]
258    #[inline(always)]
259    pub fn variant(&self) -> REFBIAS_PWD_SEL_A {
260        match self.bits {
261            false => REFBIAS_PWD_SEL_A::DISABLE,
262            true => REFBIAS_PWD_SEL_A::ENABLE,
263        }
264    }
265    #[doc = "Checks if the value of the field is `DISABLE`"]
266    #[inline(always)]
267    pub fn is_disable(&self) -> bool {
268        *self == REFBIAS_PWD_SEL_A::DISABLE
269    }
270    #[doc = "Checks if the value of the field is `ENABLE`"]
271    #[inline(always)]
272    pub fn is_enable(&self) -> bool {
273        *self == REFBIAS_PWD_SEL_A::ENABLE
274    }
275}
276#[doc = "Field `REFBIAS_PWD_SEL` writer - REFBIAS_PWD_SEL"]
277pub type REFBIAS_PWD_SEL_W<'a, const O: u8> =
278    crate::BitWriter<'a, u32, PLL_SIC_CLR_SPEC, REFBIAS_PWD_SEL_A, O>;
279impl<'a, const O: u8> REFBIAS_PWD_SEL_W<'a, O> {
280    #[doc = "No effect"]
281    #[inline(always)]
282    pub fn disable(self) -> &'a mut W {
283        self.variant(REFBIAS_PWD_SEL_A::DISABLE)
284    }
285    #[doc = "Clears the corresponding bit"]
286    #[inline(always)]
287    pub fn enable(self) -> &'a mut W {
288        self.variant(REFBIAS_PWD_SEL_A::ENABLE)
289    }
290}
291#[doc = "Field `REFBIAS_PWD` reader - REFBIAS_PWD"]
292pub type REFBIAS_PWD_R = crate::BitReader<REFBIAS_PWD_A>;
293#[doc = "REFBIAS_PWD\n\nValue on reset: 1"]
294#[derive(Clone, Copy, Debug, PartialEq, Eq)]
295pub enum REFBIAS_PWD_A {
296    #[doc = "0: No effect"]
297    DISABLE = 0,
298    #[doc = "1: Clears the corresponding bit"]
299    ENABLE = 1,
300}
301impl From<REFBIAS_PWD_A> for bool {
302    #[inline(always)]
303    fn from(variant: REFBIAS_PWD_A) -> Self {
304        variant as u8 != 0
305    }
306}
307impl REFBIAS_PWD_R {
308    #[doc = "Get enumerated values variant"]
309    #[inline(always)]
310    pub fn variant(&self) -> REFBIAS_PWD_A {
311        match self.bits {
312            false => REFBIAS_PWD_A::DISABLE,
313            true => REFBIAS_PWD_A::ENABLE,
314        }
315    }
316    #[doc = "Checks if the value of the field is `DISABLE`"]
317    #[inline(always)]
318    pub fn is_disable(&self) -> bool {
319        *self == REFBIAS_PWD_A::DISABLE
320    }
321    #[doc = "Checks if the value of the field is `ENABLE`"]
322    #[inline(always)]
323    pub fn is_enable(&self) -> bool {
324        *self == REFBIAS_PWD_A::ENABLE
325    }
326}
327#[doc = "Field `REFBIAS_PWD` writer - REFBIAS_PWD"]
328pub type REFBIAS_PWD_W<'a, const O: u8> =
329    crate::BitWriter<'a, u32, PLL_SIC_CLR_SPEC, REFBIAS_PWD_A, O>;
330impl<'a, const O: u8> REFBIAS_PWD_W<'a, O> {
331    #[doc = "No effect"]
332    #[inline(always)]
333    pub fn disable(self) -> &'a mut W {
334        self.variant(REFBIAS_PWD_A::DISABLE)
335    }
336    #[doc = "Clears the corresponding bit"]
337    #[inline(always)]
338    pub fn enable(self) -> &'a mut W {
339        self.variant(REFBIAS_PWD_A::ENABLE)
340    }
341}
342#[doc = "Field `PLL_REG_ENABLE` reader - PLL_REG_ENABLE"]
343pub type PLL_REG_ENABLE_R = crate::BitReader<PLL_REG_ENABLE_A>;
344#[doc = "PLL_REG_ENABLE\n\nValue on reset: 0"]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum PLL_REG_ENABLE_A {
347    #[doc = "0: No effect"]
348    DISABLE = 0,
349    #[doc = "1: Clears the corresponding bit"]
350    ENABLE = 1,
351}
352impl From<PLL_REG_ENABLE_A> for bool {
353    #[inline(always)]
354    fn from(variant: PLL_REG_ENABLE_A) -> Self {
355        variant as u8 != 0
356    }
357}
358impl PLL_REG_ENABLE_R {
359    #[doc = "Get enumerated values variant"]
360    #[inline(always)]
361    pub fn variant(&self) -> PLL_REG_ENABLE_A {
362        match self.bits {
363            false => PLL_REG_ENABLE_A::DISABLE,
364            true => PLL_REG_ENABLE_A::ENABLE,
365        }
366    }
367    #[doc = "Checks if the value of the field is `DISABLE`"]
368    #[inline(always)]
369    pub fn is_disable(&self) -> bool {
370        *self == PLL_REG_ENABLE_A::DISABLE
371    }
372    #[doc = "Checks if the value of the field is `ENABLE`"]
373    #[inline(always)]
374    pub fn is_enable(&self) -> bool {
375        *self == PLL_REG_ENABLE_A::ENABLE
376    }
377}
378#[doc = "Field `PLL_REG_ENABLE` writer - PLL_REG_ENABLE"]
379pub type PLL_REG_ENABLE_W<'a, const O: u8> =
380    crate::BitWriter<'a, u32, PLL_SIC_CLR_SPEC, PLL_REG_ENABLE_A, O>;
381impl<'a, const O: u8> PLL_REG_ENABLE_W<'a, O> {
382    #[doc = "No effect"]
383    #[inline(always)]
384    pub fn disable(self) -> &'a mut W {
385        self.variant(PLL_REG_ENABLE_A::DISABLE)
386    }
387    #[doc = "Clears the corresponding bit"]
388    #[inline(always)]
389    pub fn enable(self) -> &'a mut W {
390        self.variant(PLL_REG_ENABLE_A::ENABLE)
391    }
392}
393#[doc = "Field `PLL_DIV_SEL` reader - PLL_DIV_SEL"]
394pub type PLL_DIV_SEL_R = crate::FieldReader<u8, PLL_DIV_SEL_A>;
395#[doc = "PLL_DIV_SEL\n\nValue on reset: 3"]
396#[derive(Clone, Copy, Debug, PartialEq, Eq)]
397#[repr(u8)]
398pub enum PLL_DIV_SEL_A {
399    #[doc = "0: No effect"]
400    DISABLE = 0,
401    #[doc = "1: Clears the corresponding bit"]
402    ENABLE = 1,
403}
404impl From<PLL_DIV_SEL_A> for u8 {
405    #[inline(always)]
406    fn from(variant: PLL_DIV_SEL_A) -> Self {
407        variant as _
408    }
409}
410impl PLL_DIV_SEL_R {
411    #[doc = "Get enumerated values variant"]
412    #[inline(always)]
413    pub fn variant(&self) -> Option<PLL_DIV_SEL_A> {
414        match self.bits {
415            0 => Some(PLL_DIV_SEL_A::DISABLE),
416            1 => Some(PLL_DIV_SEL_A::ENABLE),
417            _ => None,
418        }
419    }
420    #[doc = "Checks if the value of the field is `DISABLE`"]
421    #[inline(always)]
422    pub fn is_disable(&self) -> bool {
423        *self == PLL_DIV_SEL_A::DISABLE
424    }
425    #[doc = "Checks if the value of the field is `ENABLE`"]
426    #[inline(always)]
427    pub fn is_enable(&self) -> bool {
428        *self == PLL_DIV_SEL_A::ENABLE
429    }
430}
431#[doc = "Field `PLL_DIV_SEL` writer - PLL_DIV_SEL"]
432pub type PLL_DIV_SEL_W<'a, const O: u8> =
433    crate::FieldWriter<'a, u32, PLL_SIC_CLR_SPEC, u8, PLL_DIV_SEL_A, 3, O>;
434impl<'a, const O: u8> PLL_DIV_SEL_W<'a, O> {
435    #[doc = "No effect"]
436    #[inline(always)]
437    pub fn disable(self) -> &'a mut W {
438        self.variant(PLL_DIV_SEL_A::DISABLE)
439    }
440    #[doc = "Clears the corresponding bit"]
441    #[inline(always)]
442    pub fn enable(self) -> &'a mut W {
443        self.variant(PLL_DIV_SEL_A::ENABLE)
444    }
445}
446#[doc = "Field `PLL_LOCK` reader - PLL_LOCK"]
447pub type PLL_LOCK_R = crate::BitReader<PLL_LOCK_A>;
448#[doc = "PLL_LOCK\n\nValue on reset: 0"]
449#[derive(Clone, Copy, Debug, PartialEq, Eq)]
450pub enum PLL_LOCK_A {
451    #[doc = "0: No effect"]
452    DISABLE = 0,
453    #[doc = "1: Clears the corresponding bit"]
454    ENABLE = 1,
455}
456impl From<PLL_LOCK_A> for bool {
457    #[inline(always)]
458    fn from(variant: PLL_LOCK_A) -> Self {
459        variant as u8 != 0
460    }
461}
462impl PLL_LOCK_R {
463    #[doc = "Get enumerated values variant"]
464    #[inline(always)]
465    pub fn variant(&self) -> PLL_LOCK_A {
466        match self.bits {
467            false => PLL_LOCK_A::DISABLE,
468            true => PLL_LOCK_A::ENABLE,
469        }
470    }
471    #[doc = "Checks if the value of the field is `DISABLE`"]
472    #[inline(always)]
473    pub fn is_disable(&self) -> bool {
474        *self == PLL_LOCK_A::DISABLE
475    }
476    #[doc = "Checks if the value of the field is `ENABLE`"]
477    #[inline(always)]
478    pub fn is_enable(&self) -> bool {
479        *self == PLL_LOCK_A::ENABLE
480    }
481}
482impl R {
483    #[doc = "Bit 6 - PLL_EN_USB_CLKS"]
484    #[inline(always)]
485    pub fn pll_en_usb_clks(&self) -> PLL_EN_USB_CLKS_R {
486        PLL_EN_USB_CLKS_R::new(((self.bits >> 6) & 1) != 0)
487    }
488    #[doc = "Bit 12 - POWER"]
489    #[inline(always)]
490    pub fn pll_power(&self) -> PLL_POWER_R {
491        PLL_POWER_R::new(((self.bits >> 12) & 1) != 0)
492    }
493    #[doc = "Bit 13 - ENABLE"]
494    #[inline(always)]
495    pub fn pll_enable(&self) -> PLL_ENABLE_R {
496        PLL_ENABLE_R::new(((self.bits >> 13) & 1) != 0)
497    }
498    #[doc = "Bit 16 - Bypass USB PLL"]
499    #[inline(always)]
500    pub fn pll_bypass(&self) -> PLL_BYPASS_R {
501        PLL_BYPASS_R::new(((self.bits >> 16) & 1) != 0)
502    }
503    #[doc = "Bit 19 - REFBIAS_PWD_SEL"]
504    #[inline(always)]
505    pub fn refbias_pwd_sel(&self) -> REFBIAS_PWD_SEL_R {
506        REFBIAS_PWD_SEL_R::new(((self.bits >> 19) & 1) != 0)
507    }
508    #[doc = "Bit 20 - REFBIAS_PWD"]
509    #[inline(always)]
510    pub fn refbias_pwd(&self) -> REFBIAS_PWD_R {
511        REFBIAS_PWD_R::new(((self.bits >> 20) & 1) != 0)
512    }
513    #[doc = "Bit 21 - PLL_REG_ENABLE"]
514    #[inline(always)]
515    pub fn pll_reg_enable(&self) -> PLL_REG_ENABLE_R {
516        PLL_REG_ENABLE_R::new(((self.bits >> 21) & 1) != 0)
517    }
518    #[doc = "Bits 22:24 - PLL_DIV_SEL"]
519    #[inline(always)]
520    pub fn pll_div_sel(&self) -> PLL_DIV_SEL_R {
521        PLL_DIV_SEL_R::new(((self.bits >> 22) & 7) as u8)
522    }
523    #[doc = "Bit 31 - PLL_LOCK"]
524    #[inline(always)]
525    pub fn pll_lock(&self) -> PLL_LOCK_R {
526        PLL_LOCK_R::new(((self.bits >> 31) & 1) != 0)
527    }
528}
529impl W {
530    #[doc = "Bit 6 - PLL_EN_USB_CLKS"]
531    #[inline(always)]
532    #[must_use]
533    pub fn pll_en_usb_clks(&mut self) -> PLL_EN_USB_CLKS_W<6> {
534        PLL_EN_USB_CLKS_W::new(self)
535    }
536    #[doc = "Bit 12 - POWER"]
537    #[inline(always)]
538    #[must_use]
539    pub fn pll_power(&mut self) -> PLL_POWER_W<12> {
540        PLL_POWER_W::new(self)
541    }
542    #[doc = "Bit 13 - ENABLE"]
543    #[inline(always)]
544    #[must_use]
545    pub fn pll_enable(&mut self) -> PLL_ENABLE_W<13> {
546        PLL_ENABLE_W::new(self)
547    }
548    #[doc = "Bit 16 - Bypass USB PLL"]
549    #[inline(always)]
550    #[must_use]
551    pub fn pll_bypass(&mut self) -> PLL_BYPASS_W<16> {
552        PLL_BYPASS_W::new(self)
553    }
554    #[doc = "Bit 19 - REFBIAS_PWD_SEL"]
555    #[inline(always)]
556    #[must_use]
557    pub fn refbias_pwd_sel(&mut self) -> REFBIAS_PWD_SEL_W<19> {
558        REFBIAS_PWD_SEL_W::new(self)
559    }
560    #[doc = "Bit 20 - REFBIAS_PWD"]
561    #[inline(always)]
562    #[must_use]
563    pub fn refbias_pwd(&mut self) -> REFBIAS_PWD_W<20> {
564        REFBIAS_PWD_W::new(self)
565    }
566    #[doc = "Bit 21 - PLL_REG_ENABLE"]
567    #[inline(always)]
568    #[must_use]
569    pub fn pll_reg_enable(&mut self) -> PLL_REG_ENABLE_W<21> {
570        PLL_REG_ENABLE_W::new(self)
571    }
572    #[doc = "Bits 22:24 - PLL_DIV_SEL"]
573    #[inline(always)]
574    #[must_use]
575    pub fn pll_div_sel(&mut self) -> PLL_DIV_SEL_W<22> {
576        PLL_DIV_SEL_W::new(self)
577    }
578    #[doc = "Writes raw bits to the register."]
579    #[inline(always)]
580    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
581        self.0.bits(bits);
582        self
583    }
584}
585#[doc = "PLL Control/Status Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll_sic_clr](index.html) module"]
586pub struct PLL_SIC_CLR_SPEC;
587impl crate::RegisterSpec for PLL_SIC_CLR_SPEC {
588    type Ux = u32;
589}
590#[doc = "`read()` method returns [pll_sic_clr::R](R) reader structure"]
591impl crate::Readable for PLL_SIC_CLR_SPEC {
592    type Reader = R;
593}
594#[doc = "`write(|w| ..)` method takes [pll_sic_clr::W](W) writer structure"]
595impl crate::Writable for PLL_SIC_CLR_SPEC {
596    type Writer = W;
597    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
598    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
599}
600#[doc = "`reset()` method sets PLL_SIC_CLR to value 0x00d1_2000"]
601impl crate::Resettable for PLL_SIC_CLR_SPEC {
602    const RESET_VALUE: Self::Ux = 0x00d1_2000;
603}
mimxrt595s/usbphy/pll_sic_clr.rs

mimxrt595s/usbphy/
pll_sic_clr.rs
