mimxrt595s/clkctl0/
pscctl2_set.rs

1#[doc = "Register `PSCCTL2_SET` writer"]
2pub struct W(crate::W<PSCCTL2_SET_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<PSCCTL2_SET_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<PSCCTL2_SET_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<PSCCTL2_SET_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Micro-Tick Timer 0 clock set\n\nValue on reset: 0"]
23#[derive(Clone, Copy, Debug, PartialEq, Eq)]
24pub enum UTICK0_CLK_AW {
25    #[doc = "0: No effect"]
26    NO_EFFECT = 0,
27    #[doc = "1: Sets the corresponding bit in PSCCTL2 register"]
28    CLK_ENABLE_SET = 1,
29}
30impl From<UTICK0_CLK_AW> for bool {
31    #[inline(always)]
32    fn from(variant: UTICK0_CLK_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36#[doc = "Field `UTICK0_CLK` writer - Micro-Tick Timer 0 clock set"]
37pub type UTICK0_CLK_W<'a, const O: u8> =
38    crate::BitWriter<'a, u32, PSCCTL2_SET_SPEC, UTICK0_CLK_AW, O>;
39impl<'a, const O: u8> UTICK0_CLK_W<'a, O> {
40    #[doc = "No effect"]
41    #[inline(always)]
42    pub fn no_effect(self) -> &'a mut W {
43        self.variant(UTICK0_CLK_AW::NO_EFFECT)
44    }
45    #[doc = "Sets the corresponding bit in PSCCTL2 register"]
46    #[inline(always)]
47    pub fn clk_enable_set(self) -> &'a mut W {
48        self.variant(UTICK0_CLK_AW::CLK_ENABLE_SET)
49    }
50}
51#[doc = "Watchdog Timer 0 clock set\n\nValue on reset: 0"]
52#[derive(Clone, Copy, Debug, PartialEq, Eq)]
53pub enum WWDT0_CLK_AW {
54    #[doc = "0: No effect"]
55    NO_EFFECT = 0,
56    #[doc = "1: Sets the corresponding bit in PSCCTL2 register"]
57    CLK_ENABLE_SET = 1,
58}
59impl From<WWDT0_CLK_AW> for bool {
60    #[inline(always)]
61    fn from(variant: WWDT0_CLK_AW) -> Self {
62        variant as u8 != 0
63    }
64}
65#[doc = "Field `WWDT0_CLK` writer - Watchdog Timer 0 clock set"]
66pub type WWDT0_CLK_W<'a, const O: u8> =
67    crate::BitWriter<'a, u32, PSCCTL2_SET_SPEC, WWDT0_CLK_AW, O>;
68impl<'a, const O: u8> WWDT0_CLK_W<'a, O> {
69    #[doc = "No effect"]
70    #[inline(always)]
71    pub fn no_effect(self) -> &'a mut W {
72        self.variant(WWDT0_CLK_AW::NO_EFFECT)
73    }
74    #[doc = "Sets the corresponding bit in PSCCTL2 register"]
75    #[inline(always)]
76    pub fn clk_enable_set(self) -> &'a mut W {
77        self.variant(WWDT0_CLK_AW::CLK_ENABLE_SET)
78    }
79}
80#[doc = "Power Management Controller clock set\n\nValue on reset: 0"]
81#[derive(Clone, Copy, Debug, PartialEq, Eq)]
82pub enum PMC_AW {
83    #[doc = "0: No effect"]
84    NO_EFFECT = 0,
85    #[doc = "1: Sets the corresponding bit in PSCCTL2 register"]
86    CLK_ENABLE_SET = 1,
87}
88impl From<PMC_AW> for bool {
89    #[inline(always)]
90    fn from(variant: PMC_AW) -> Self {
91        variant as u8 != 0
92    }
93}
94#[doc = "Field `PMC` writer - Power Management Controller clock set"]
95pub type PMC_W<'a, const O: u8> = crate::BitWriter<'a, u32, PSCCTL2_SET_SPEC, PMC_AW, O>;
96impl<'a, const O: u8> PMC_W<'a, O> {
97    #[doc = "No effect"]
98    #[inline(always)]
99    pub fn no_effect(self) -> &'a mut W {
100        self.variant(PMC_AW::NO_EFFECT)
101    }
102    #[doc = "Sets the corresponding bit in PSCCTL2 register"]
103    #[inline(always)]
104    pub fn clk_enable_set(self) -> &'a mut W {
105        self.variant(PMC_AW::CLK_ENABLE_SET)
106    }
107}
108impl W {
109    #[doc = "Bit 0 - Micro-Tick Timer 0 clock set"]
110    #[inline(always)]
111    #[must_use]
112    pub fn utick0_clk(&mut self) -> UTICK0_CLK_W<0> {
113        UTICK0_CLK_W::new(self)
114    }
115    #[doc = "Bit 1 - Watchdog Timer 0 clock set"]
116    #[inline(always)]
117    #[must_use]
118    pub fn wwdt0_clk(&mut self) -> WWDT0_CLK_W<1> {
119        WWDT0_CLK_W::new(self)
120    }
121    #[doc = "Bit 29 - Power Management Controller clock set"]
122    #[inline(always)]
123    #[must_use]
124    pub fn pmc(&mut self) -> PMC_W<29> {
125        PMC_W::new(self)
126    }
127    #[doc = "Writes raw bits to the register."]
128    #[inline(always)]
129    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
130        self.0.bits(bits);
131        self
132    }
133}
134#[doc = "Clock Control 2 Set\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pscctl2_set](index.html) module"]
135pub struct PSCCTL2_SET_SPEC;
136impl crate::RegisterSpec for PSCCTL2_SET_SPEC {
137    type Ux = u32;
138}
139#[doc = "`write(|w| ..)` method takes [pscctl2_set::W](W) writer structure"]
140impl crate::Writable for PSCCTL2_SET_SPEC {
141    type Writer = W;
142    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
143    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
144}
145#[doc = "`reset()` method sets PSCCTL2_SET to value 0"]
146impl crate::Resettable for PSCCTL2_SET_SPEC {
147    const RESET_VALUE: Self::Ux = 0;
148}
mimxrt595s/clkctl0/pscctl2_set.rs

mimxrt595s/clkctl0/
pscctl2_set.rs
