mimxrt595s/rstctl0/
prstctl0_set.rs

1#[doc = "Register `PRSTCTL0_SET` writer"]
2pub struct W(crate::W<PRSTCTL0_SET_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<PRSTCTL0_SET_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<PRSTCTL0_SET_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<PRSTCTL0_SET_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Fusion_ DSP reset set\n\nValue on reset: 0"]
23#[derive(Clone, Copy, Debug, PartialEq, Eq)]
24pub enum DSP_AW {
25    #[doc = "0: No Effect"]
26    DSP_CLR = 0,
27    #[doc = "1: Sets the PRSTCTL0 Bit"]
28    DSP_SET = 1,
29}
30impl From<DSP_AW> for bool {
31    #[inline(always)]
32    fn from(variant: DSP_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36#[doc = "Field `DSP` writer - Fusion_ DSP reset set"]
37pub type DSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, DSP_AW, O>;
38impl<'a, const O: u8> DSP_W<'a, O> {
39    #[doc = "No Effect"]
40    #[inline(always)]
41    pub fn dsp_clr(self) -> &'a mut W {
42        self.variant(DSP_AW::DSP_CLR)
43    }
44    #[doc = "Sets the PRSTCTL0 Bit"]
45    #[inline(always)]
46    pub fn dsp_set(self) -> &'a mut W {
47        self.variant(DSP_AW::DSP_SET)
48    }
49}
50#[doc = "AXI SWITCH reset set\n\nValue on reset: 0"]
51#[derive(Clone, Copy, Debug, PartialEq, Eq)]
52pub enum AXI_SWITCH_AW {
53    #[doc = "0: No Effect"]
54    AXI_SWITCH_CLR = 0,
55    #[doc = "1: Sets the PRSTCTL0 Bit"]
56    AXI_SWITCH_SET = 1,
57}
58impl From<AXI_SWITCH_AW> for bool {
59    #[inline(always)]
60    fn from(variant: AXI_SWITCH_AW) -> Self {
61        variant as u8 != 0
62    }
63}
64#[doc = "Field `AXI_SWITCH` writer - AXI SWITCH reset set"]
65pub type AXI_SWITCH_W<'a, const O: u8> =
66    crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, AXI_SWITCH_AW, O>;
67impl<'a, const O: u8> AXI_SWITCH_W<'a, O> {
68    #[doc = "No Effect"]
69    #[inline(always)]
70    pub fn axi_switch_clr(self) -> &'a mut W {
71        self.variant(AXI_SWITCH_AW::AXI_SWITCH_CLR)
72    }
73    #[doc = "Sets the PRSTCTL0 Bit"]
74    #[inline(always)]
75    pub fn axi_switch_set(self) -> &'a mut W {
76        self.variant(AXI_SWITCH_AW::AXI_SWITCH_SET)
77    }
78}
79#[doc = "POWERQUAD reset set\n\nValue on reset: 0"]
80#[derive(Clone, Copy, Debug, PartialEq, Eq)]
81pub enum POWERQUAD_AW {
82    #[doc = "0: No Effect"]
83    POWERQUAD_CLR = 0,
84    #[doc = "1: Sets the PRSTCTL0 Bit"]
85    POWERQUAD_SET = 1,
86}
87impl From<POWERQUAD_AW> for bool {
88    #[inline(always)]
89    fn from(variant: POWERQUAD_AW) -> Self {
90        variant as u8 != 0
91    }
92}
93#[doc = "Field `POWERQUAD` writer - POWERQUAD reset set"]
94pub type POWERQUAD_W<'a, const O: u8> =
95    crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, POWERQUAD_AW, O>;
96impl<'a, const O: u8> POWERQUAD_W<'a, O> {
97    #[doc = "No Effect"]
98    #[inline(always)]
99    pub fn powerquad_clr(self) -> &'a mut W {
100        self.variant(POWERQUAD_AW::POWERQUAD_CLR)
101    }
102    #[doc = "Sets the PRSTCTL0 Bit"]
103    #[inline(always)]
104    pub fn powerquad_set(self) -> &'a mut W {
105        self.variant(POWERQUAD_AW::POWERQUAD_SET)
106    }
107}
108#[doc = "CASPER reset set\n\nValue on reset: 0"]
109#[derive(Clone, Copy, Debug, PartialEq, Eq)]
110pub enum CASPER_AW {
111    #[doc = "0: No Effect"]
112    CASPER_CLR = 0,
113    #[doc = "1: Sets the PRSTCTL0 Bit"]
114    CASPER_SET = 1,
115}
116impl From<CASPER_AW> for bool {
117    #[inline(always)]
118    fn from(variant: CASPER_AW) -> Self {
119        variant as u8 != 0
120    }
121}
122#[doc = "Field `CASPER` writer - CASPER reset set"]
123pub type CASPER_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, CASPER_AW, O>;
124impl<'a, const O: u8> CASPER_W<'a, O> {
125    #[doc = "No Effect"]
126    #[inline(always)]
127    pub fn casper_clr(self) -> &'a mut W {
128        self.variant(CASPER_AW::CASPER_CLR)
129    }
130    #[doc = "Sets the PRSTCTL0 Bit"]
131    #[inline(always)]
132    pub fn casper_set(self) -> &'a mut W {
133        self.variant(CASPER_AW::CASPER_SET)
134    }
135}
136#[doc = "HASHCRYPT reset set\n\nValue on reset: 0"]
137#[derive(Clone, Copy, Debug, PartialEq, Eq)]
138pub enum HASHCRYPT_AW {
139    #[doc = "0: No Effect"]
140    HASHCRYPT_CLR = 0,
141    #[doc = "1: Sets the PRSTCTL0 Bit"]
142    HASHCRYPT_SET = 1,
143}
144impl From<HASHCRYPT_AW> for bool {
145    #[inline(always)]
146    fn from(variant: HASHCRYPT_AW) -> Self {
147        variant as u8 != 0
148    }
149}
150#[doc = "Field `HASHCRYPT` writer - HASHCRYPT reset set"]
151pub type HASHCRYPT_W<'a, const O: u8> =
152    crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, HASHCRYPT_AW, O>;
153impl<'a, const O: u8> HASHCRYPT_W<'a, O> {
154    #[doc = "No Effect"]
155    #[inline(always)]
156    pub fn hashcrypt_clr(self) -> &'a mut W {
157        self.variant(HASHCRYPT_AW::HASHCRYPT_CLR)
158    }
159    #[doc = "Sets the PRSTCTL0 Bit"]
160    #[inline(always)]
161    pub fn hashcrypt_set(self) -> &'a mut W {
162        self.variant(HASHCRYPT_AW::HASHCRYPT_SET)
163    }
164}
165#[doc = "PUF reset set\n\nValue on reset: 0"]
166#[derive(Clone, Copy, Debug, PartialEq, Eq)]
167pub enum PUF_AW {
168    #[doc = "0: No Effect"]
169    PUF_CLR = 0,
170    #[doc = "1: Sets the PRSTCTL0 Bit"]
171    PUF_SET = 1,
172}
173impl From<PUF_AW> for bool {
174    #[inline(always)]
175    fn from(variant: PUF_AW) -> Self {
176        variant as u8 != 0
177    }
178}
179#[doc = "Field `PUF` writer - PUF reset set"]
180pub type PUF_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, PUF_AW, O>;
181impl<'a, const O: u8> PUF_W<'a, O> {
182    #[doc = "No Effect"]
183    #[inline(always)]
184    pub fn puf_clr(self) -> &'a mut W {
185        self.variant(PUF_AW::PUF_CLR)
186    }
187    #[doc = "Sets the PRSTCTL0 Bit"]
188    #[inline(always)]
189    pub fn puf_set(self) -> &'a mut W {
190        self.variant(PUF_AW::PUF_SET)
191    }
192}
193#[doc = "RNG reset set\n\nValue on reset: 0"]
194#[derive(Clone, Copy, Debug, PartialEq, Eq)]
195pub enum RNG_AW {
196    #[doc = "0: No Effect"]
197    RNG_CLR = 0,
198    #[doc = "1: Sets the PRSTCTL0 Bit"]
199    RNG_SET = 1,
200}
201impl From<RNG_AW> for bool {
202    #[inline(always)]
203    fn from(variant: RNG_AW) -> Self {
204        variant as u8 != 0
205    }
206}
207#[doc = "Field `RNG` writer - RNG reset set"]
208pub type RNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, RNG_AW, O>;
209impl<'a, const O: u8> RNG_W<'a, O> {
210    #[doc = "No Effect"]
211    #[inline(always)]
212    pub fn rng_clr(self) -> &'a mut W {
213        self.variant(RNG_AW::RNG_CLR)
214    }
215    #[doc = "Sets the PRSTCTL0 Bit"]
216    #[inline(always)]
217    pub fn rng_set(self) -> &'a mut W {
218        self.variant(RNG_AW::RNG_SET)
219    }
220}
221#[doc = "FLEXSPI0 and OTFAD reset set\n\nValue on reset: 0"]
222#[derive(Clone, Copy, Debug, PartialEq, Eq)]
223pub enum FLEXSPI0_OTFAD_AW {
224    #[doc = "0: No Effect"]
225    FLEXSPI0_OTFAD_CLR = 0,
226    #[doc = "1: Sets the PRSTCTL0 Bit"]
227    FLEXSPI0_OTFAD_SET = 1,
228}
229impl From<FLEXSPI0_OTFAD_AW> for bool {
230    #[inline(always)]
231    fn from(variant: FLEXSPI0_OTFAD_AW) -> Self {
232        variant as u8 != 0
233    }
234}
235#[doc = "Field `FLEXSPI0_OTFAD` writer - FLEXSPI0 and OTFAD reset set"]
236pub type FLEXSPI0_OTFAD_W<'a, const O: u8> =
237    crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, FLEXSPI0_OTFAD_AW, O>;
238impl<'a, const O: u8> FLEXSPI0_OTFAD_W<'a, O> {
239    #[doc = "No Effect"]
240    #[inline(always)]
241    pub fn flexspi0_otfad_clr(self) -> &'a mut W {
242        self.variant(FLEXSPI0_OTFAD_AW::FLEXSPI0_OTFAD_CLR)
243    }
244    #[doc = "Sets the PRSTCTL0 Bit"]
245    #[inline(always)]
246    pub fn flexspi0_otfad_set(self) -> &'a mut W {
247        self.variant(FLEXSPI0_OTFAD_AW::FLEXSPI0_OTFAD_SET)
248    }
249}
250#[doc = "FLEXSPI1 reset set\n\nValue on reset: 0"]
251#[derive(Clone, Copy, Debug, PartialEq, Eq)]
252pub enum FLEXSPI1_AW {
253    #[doc = "0: No Effect"]
254    FLEXSPI1_CLR = 0,
255    #[doc = "1: Sets the PRSTCTL0 Bit"]
256    FLEXSPI1_SET = 1,
257}
258impl From<FLEXSPI1_AW> for bool {
259    #[inline(always)]
260    fn from(variant: FLEXSPI1_AW) -> Self {
261        variant as u8 != 0
262    }
263}
264#[doc = "Field `FLEXSPI1` writer - FLEXSPI1 reset set"]
265pub type FLEXSPI1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, FLEXSPI1_AW, O>;
266impl<'a, const O: u8> FLEXSPI1_W<'a, O> {
267    #[doc = "No Effect"]
268    #[inline(always)]
269    pub fn flexspi1_clr(self) -> &'a mut W {
270        self.variant(FLEXSPI1_AW::FLEXSPI1_CLR)
271    }
272    #[doc = "Sets the PRSTCTL0 Bit"]
273    #[inline(always)]
274    pub fn flexspi1_set(self) -> &'a mut W {
275        self.variant(FLEXSPI1_AW::FLEXSPI1_SET)
276    }
277}
278#[doc = "USB PHY reset set\n\nValue on reset: 0"]
279#[derive(Clone, Copy, Debug, PartialEq, Eq)]
280pub enum USBHS_PHY_AW {
281    #[doc = "0: No Effect"]
282    USBHS_PHY_CLR = 0,
283    #[doc = "1: Sets the PRSTCTL0 Bit"]
284    USBHS_PHY_SET = 1,
285}
286impl From<USBHS_PHY_AW> for bool {
287    #[inline(always)]
288    fn from(variant: USBHS_PHY_AW) -> Self {
289        variant as u8 != 0
290    }
291}
292#[doc = "Field `USBHS_PHY` writer - USB PHY reset set"]
293pub type USBHS_PHY_W<'a, const O: u8> =
294    crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, USBHS_PHY_AW, O>;
295impl<'a, const O: u8> USBHS_PHY_W<'a, O> {
296    #[doc = "No Effect"]
297    #[inline(always)]
298    pub fn usbhs_phy_clr(self) -> &'a mut W {
299        self.variant(USBHS_PHY_AW::USBHS_PHY_CLR)
300    }
301    #[doc = "Sets the PRSTCTL0 Bit"]
302    #[inline(always)]
303    pub fn usbhs_phy_set(self) -> &'a mut W {
304        self.variant(USBHS_PHY_AW::USBHS_PHY_SET)
305    }
306}
307#[doc = "USB Device reset set\n\nValue on reset: 0"]
308#[derive(Clone, Copy, Debug, PartialEq, Eq)]
309pub enum USBHS_DEVICE_AW {
310    #[doc = "0: No Effect"]
311    USBHS_DEVICE_CLR = 0,
312    #[doc = "1: Sets the PRSTCTL0 Bit"]
313    USBHS_DEVICE_SET = 1,
314}
315impl From<USBHS_DEVICE_AW> for bool {
316    #[inline(always)]
317    fn from(variant: USBHS_DEVICE_AW) -> Self {
318        variant as u8 != 0
319    }
320}
321#[doc = "Field `USBHS_DEVICE` writer - USB Device reset set"]
322pub type USBHS_DEVICE_W<'a, const O: u8> =
323    crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, USBHS_DEVICE_AW, O>;
324impl<'a, const O: u8> USBHS_DEVICE_W<'a, O> {
325    #[doc = "No Effect"]
326    #[inline(always)]
327    pub fn usbhs_device_clr(self) -> &'a mut W {
328        self.variant(USBHS_DEVICE_AW::USBHS_DEVICE_CLR)
329    }
330    #[doc = "Sets the PRSTCTL0 Bit"]
331    #[inline(always)]
332    pub fn usbhs_device_set(self) -> &'a mut W {
333        self.variant(USBHS_DEVICE_AW::USBHS_DEVICE_SET)
334    }
335}
336#[doc = "USB HOST reset set\n\nValue on reset: 0"]
337#[derive(Clone, Copy, Debug, PartialEq, Eq)]
338pub enum USBHS_HOST_AW {
339    #[doc = "0: No Effect"]
340    USBHS_HOST_CLR = 0,
341    #[doc = "1: Sets the PRSTCTL0 Bit"]
342    USBHS_HOST_SET = 1,
343}
344impl From<USBHS_HOST_AW> for bool {
345    #[inline(always)]
346    fn from(variant: USBHS_HOST_AW) -> Self {
347        variant as u8 != 0
348    }
349}
350#[doc = "Field `USBHS_HOST` writer - USB HOST reset set"]
351pub type USBHS_HOST_W<'a, const O: u8> =
352    crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, USBHS_HOST_AW, O>;
353impl<'a, const O: u8> USBHS_HOST_W<'a, O> {
354    #[doc = "No Effect"]
355    #[inline(always)]
356    pub fn usbhs_host_clr(self) -> &'a mut W {
357        self.variant(USBHS_HOST_AW::USBHS_HOST_CLR)
358    }
359    #[doc = "Sets the PRSTCTL0 Bit"]
360    #[inline(always)]
361    pub fn usbhs_host_set(self) -> &'a mut W {
362        self.variant(USBHS_HOST_AW::USBHS_HOST_SET)
363    }
364}
365#[doc = "USBHS SRAM reset set\n\nValue on reset: 0"]
366#[derive(Clone, Copy, Debug, PartialEq, Eq)]
367pub enum USBHS_SRAM_AW {
368    #[doc = "0: No Effect"]
369    USBHS_SRAM_CLR = 0,
370    #[doc = "1: Sets the PRSTCTL0 Bit"]
371    USBHS_SRAM_SET = 1,
372}
373impl From<USBHS_SRAM_AW> for bool {
374    #[inline(always)]
375    fn from(variant: USBHS_SRAM_AW) -> Self {
376        variant as u8 != 0
377    }
378}
379#[doc = "Field `USBHS_SRAM` writer - USBHS SRAM reset set"]
380pub type USBHS_SRAM_W<'a, const O: u8> =
381    crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, USBHS_SRAM_AW, O>;
382impl<'a, const O: u8> USBHS_SRAM_W<'a, O> {
383    #[doc = "No Effect"]
384    #[inline(always)]
385    pub fn usbhs_sram_clr(self) -> &'a mut W {
386        self.variant(USBHS_SRAM_AW::USBHS_SRAM_CLR)
387    }
388    #[doc = "Sets the PRSTCTL0 Bit"]
389    #[inline(always)]
390    pub fn usbhs_sram_set(self) -> &'a mut W {
391        self.variant(USBHS_SRAM_AW::USBHS_SRAM_SET)
392    }
393}
394#[doc = "SCTimer reset set\n\nValue on reset: 0"]
395#[derive(Clone, Copy, Debug, PartialEq, Eq)]
396pub enum SCT_AW {
397    #[doc = "0: No Effect"]
398    SCT_CLR = 0,
399    #[doc = "1: Sets the PRSTCTL0 Bit"]
400    SCT_SET = 1,
401}
402impl From<SCT_AW> for bool {
403    #[inline(always)]
404    fn from(variant: SCT_AW) -> Self {
405        variant as u8 != 0
406    }
407}
408#[doc = "Field `SCT` writer - SCTimer reset set"]
409pub type SCT_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, SCT_AW, O>;
410impl<'a, const O: u8> SCT_W<'a, O> {
411    #[doc = "No Effect"]
412    #[inline(always)]
413    pub fn sct_clr(self) -> &'a mut W {
414        self.variant(SCT_AW::SCT_CLR)
415    }
416    #[doc = "Sets the PRSTCTL0 Bit"]
417    #[inline(always)]
418    pub fn sct_set(self) -> &'a mut W {
419        self.variant(SCT_AW::SCT_SET)
420    }
421}
422#[doc = "GPU reset set\n\nValue on reset: 0"]
423#[derive(Clone, Copy, Debug, PartialEq, Eq)]
424pub enum GPU_AW {
425    #[doc = "0: No Effect"]
426    GPU_CLR = 0,
427    #[doc = "1: Sets the PRSTCTL0 Bit"]
428    GPU_SET = 1,
429}
430impl From<GPU_AW> for bool {
431    #[inline(always)]
432    fn from(variant: GPU_AW) -> Self {
433        variant as u8 != 0
434    }
435}
436#[doc = "Field `GPU` writer - GPU reset set"]
437pub type GPU_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, GPU_AW, O>;
438impl<'a, const O: u8> GPU_W<'a, O> {
439    #[doc = "No Effect"]
440    #[inline(always)]
441    pub fn gpu_clr(self) -> &'a mut W {
442        self.variant(GPU_AW::GPU_CLR)
443    }
444    #[doc = "Sets the PRSTCTL0 Bit"]
445    #[inline(always)]
446    pub fn gpu_set(self) -> &'a mut W {
447        self.variant(GPU_AW::GPU_SET)
448    }
449}
450#[doc = "LCDIF DISPLAY CONTROLLER reset set\n\nValue on reset: 0"]
451#[derive(Clone, Copy, Debug, PartialEq, Eq)]
452pub enum DISPLAY_CONTROLLER_AW {
453    #[doc = "0: No Effect"]
454    DISPLAY_CONTROLLER_CLR = 0,
455    #[doc = "1: Sets the PRSTCTL0 Bit"]
456    DISPLAY_CONTROLLER_SET = 1,
457}
458impl From<DISPLAY_CONTROLLER_AW> for bool {
459    #[inline(always)]
460    fn from(variant: DISPLAY_CONTROLLER_AW) -> Self {
461        variant as u8 != 0
462    }
463}
464#[doc = "Field `DISPLAY_CONTROLLER` writer - LCDIF DISPLAY CONTROLLER reset set"]
465pub type DISPLAY_CONTROLLER_W<'a, const O: u8> =
466    crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, DISPLAY_CONTROLLER_AW, O>;
467impl<'a, const O: u8> DISPLAY_CONTROLLER_W<'a, O> {
468    #[doc = "No Effect"]
469    #[inline(always)]
470    pub fn display_controller_clr(self) -> &'a mut W {
471        self.variant(DISPLAY_CONTROLLER_AW::DISPLAY_CONTROLLER_CLR)
472    }
473    #[doc = "Sets the PRSTCTL0 Bit"]
474    #[inline(always)]
475    pub fn display_controller_set(self) -> &'a mut W {
476        self.variant(DISPLAY_CONTROLLER_AW::DISPLAY_CONTROLLER_SET)
477    }
478}
479#[doc = "MIPI DSI controller reset set\n\nValue on reset: 0"]
480#[derive(Clone, Copy, Debug, PartialEq, Eq)]
481pub enum MIPI_DSI_CONTROLLER_AW {
482    #[doc = "0: No Effect"]
483    MIPI_DSI_CONTROLLER_CLR = 0,
484    #[doc = "1: Sets the PRSTCTL0 Bit"]
485    MIPI_DSI_CONTROLLER_SET = 1,
486}
487impl From<MIPI_DSI_CONTROLLER_AW> for bool {
488    #[inline(always)]
489    fn from(variant: MIPI_DSI_CONTROLLER_AW) -> Self {
490        variant as u8 != 0
491    }
492}
493#[doc = "Field `MIPI_DSI_CONTROLLER` writer - MIPI DSI controller reset set"]
494pub type MIPI_DSI_CONTROLLER_W<'a, const O: u8> =
495    crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, MIPI_DSI_CONTROLLER_AW, O>;
496impl<'a, const O: u8> MIPI_DSI_CONTROLLER_W<'a, O> {
497    #[doc = "No Effect"]
498    #[inline(always)]
499    pub fn mipi_dsi_controller_clr(self) -> &'a mut W {
500        self.variant(MIPI_DSI_CONTROLLER_AW::MIPI_DSI_CONTROLLER_CLR)
501    }
502    #[doc = "Sets the PRSTCTL0 Bit"]
503    #[inline(always)]
504    pub fn mipi_dsi_controller_set(self) -> &'a mut W {
505        self.variant(MIPI_DSI_CONTROLLER_AW::MIPI_DSI_CONTROLLER_SET)
506    }
507}
508#[doc = "MIPI DSI PHY reset set\n\nValue on reset: 0"]
509#[derive(Clone, Copy, Debug, PartialEq, Eq)]
510pub enum MIPI_DSI_PHY_AW {
511    #[doc = "0: No Effect"]
512    MIPI_DSI_PHY_CLR = 0,
513    #[doc = "1: Sets the PRSTCTL0 Bit"]
514    MIPI_DSI_PHY_SET = 1,
515}
516impl From<MIPI_DSI_PHY_AW> for bool {
517    #[inline(always)]
518    fn from(variant: MIPI_DSI_PHY_AW) -> Self {
519        variant as u8 != 0
520    }
521}
522#[doc = "Field `MIPI_DSI_PHY` writer - MIPI DSI PHY reset set"]
523pub type MIPI_DSI_PHY_W<'a, const O: u8> =
524    crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, MIPI_DSI_PHY_AW, O>;
525impl<'a, const O: u8> MIPI_DSI_PHY_W<'a, O> {
526    #[doc = "No Effect"]
527    #[inline(always)]
528    pub fn mipi_dsi_phy_clr(self) -> &'a mut W {
529        self.variant(MIPI_DSI_PHY_AW::MIPI_DSI_PHY_CLR)
530    }
531    #[doc = "Sets the PRSTCTL0 Bit"]
532    #[inline(always)]
533    pub fn mipi_dsi_phy_set(self) -> &'a mut W {
534        self.variant(MIPI_DSI_PHY_AW::MIPI_DSI_PHY_SET)
535    }
536}
537#[doc = "SMARTDMA Event/Algorithm handler reset set\n\nValue on reset: 0"]
538#[derive(Clone, Copy, Debug, PartialEq, Eq)]
539pub enum SMARTDMA_AW {
540    #[doc = "0: No Effect"]
541    SMARTDMA_CLR = 0,
542    #[doc = "1: Sets the PRSTCTL0 Bit"]
543    SMARTDMA_SET = 1,
544}
545impl From<SMARTDMA_AW> for bool {
546    #[inline(always)]
547    fn from(variant: SMARTDMA_AW) -> Self {
548        variant as u8 != 0
549    }
550}
551#[doc = "Field `SMARTDMA` writer - SMARTDMA Event/Algorithm handler reset set"]
552pub type SMARTDMA_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRSTCTL0_SET_SPEC, SMARTDMA_AW, O>;
553impl<'a, const O: u8> SMARTDMA_W<'a, O> {
554    #[doc = "No Effect"]
555    #[inline(always)]
556    pub fn smartdma_clr(self) -> &'a mut W {
557        self.variant(SMARTDMA_AW::SMARTDMA_CLR)
558    }
559    #[doc = "Sets the PRSTCTL0 Bit"]
560    #[inline(always)]
561    pub fn smartdma_set(self) -> &'a mut W {
562        self.variant(SMARTDMA_AW::SMARTDMA_SET)
563    }
564}
565impl W {
566    #[doc = "Bit 1 - Fusion_ DSP reset set"]
567    #[inline(always)]
568    #[must_use]
569    pub fn dsp(&mut self) -> DSP_W<1> {
570        DSP_W::new(self)
571    }
572    #[doc = "Bit 3 - AXI SWITCH reset set"]
573    #[inline(always)]
574    #[must_use]
575    pub fn axi_switch(&mut self) -> AXI_SWITCH_W<3> {
576        AXI_SWITCH_W::new(self)
577    }
578    #[doc = "Bit 8 - POWERQUAD reset set"]
579    #[inline(always)]
580    #[must_use]
581    pub fn powerquad(&mut self) -> POWERQUAD_W<8> {
582        POWERQUAD_W::new(self)
583    }
584    #[doc = "Bit 9 - CASPER reset set"]
585    #[inline(always)]
586    #[must_use]
587    pub fn casper(&mut self) -> CASPER_W<9> {
588        CASPER_W::new(self)
589    }
590    #[doc = "Bit 10 - HASHCRYPT reset set"]
591    #[inline(always)]
592    #[must_use]
593    pub fn hashcrypt(&mut self) -> HASHCRYPT_W<10> {
594        HASHCRYPT_W::new(self)
595    }
596    #[doc = "Bit 11 - PUF reset set"]
597    #[inline(always)]
598    #[must_use]
599    pub fn puf(&mut self) -> PUF_W<11> {
600        PUF_W::new(self)
601    }
602    #[doc = "Bit 12 - RNG reset set"]
603    #[inline(always)]
604    #[must_use]
605    pub fn rng(&mut self) -> RNG_W<12> {
606        RNG_W::new(self)
607    }
608    #[doc = "Bit 16 - FLEXSPI0 and OTFAD reset set"]
609    #[inline(always)]
610    #[must_use]
611    pub fn flexspi0_otfad(&mut self) -> FLEXSPI0_OTFAD_W<16> {
612        FLEXSPI0_OTFAD_W::new(self)
613    }
614    #[doc = "Bit 18 - FLEXSPI1 reset set"]
615    #[inline(always)]
616    #[must_use]
617    pub fn flexspi1(&mut self) -> FLEXSPI1_W<18> {
618        FLEXSPI1_W::new(self)
619    }
620    #[doc = "Bit 20 - USB PHY reset set"]
621    #[inline(always)]
622    #[must_use]
623    pub fn usbhs_phy(&mut self) -> USBHS_PHY_W<20> {
624        USBHS_PHY_W::new(self)
625    }
626    #[doc = "Bit 21 - USB Device reset set"]
627    #[inline(always)]
628    #[must_use]
629    pub fn usbhs_device(&mut self) -> USBHS_DEVICE_W<21> {
630        USBHS_DEVICE_W::new(self)
631    }
632    #[doc = "Bit 22 - USB HOST reset set"]
633    #[inline(always)]
634    #[must_use]
635    pub fn usbhs_host(&mut self) -> USBHS_HOST_W<22> {
636        USBHS_HOST_W::new(self)
637    }
638    #[doc = "Bit 23 - USBHS SRAM reset set"]
639    #[inline(always)]
640    #[must_use]
641    pub fn usbhs_sram(&mut self) -> USBHS_SRAM_W<23> {
642        USBHS_SRAM_W::new(self)
643    }
644    #[doc = "Bit 24 - SCTimer reset set"]
645    #[inline(always)]
646    #[must_use]
647    pub fn sct(&mut self) -> SCT_W<24> {
648        SCT_W::new(self)
649    }
650    #[doc = "Bit 26 - GPU reset set"]
651    #[inline(always)]
652    #[must_use]
653    pub fn gpu(&mut self) -> GPU_W<26> {
654        GPU_W::new(self)
655    }
656    #[doc = "Bit 27 - LCDIF DISPLAY CONTROLLER reset set"]
657    #[inline(always)]
658    #[must_use]
659    pub fn display_controller(&mut self) -> DISPLAY_CONTROLLER_W<27> {
660        DISPLAY_CONTROLLER_W::new(self)
661    }
662    #[doc = "Bit 28 - MIPI DSI controller reset set"]
663    #[inline(always)]
664    #[must_use]
665    pub fn mipi_dsi_controller(&mut self) -> MIPI_DSI_CONTROLLER_W<28> {
666        MIPI_DSI_CONTROLLER_W::new(self)
667    }
668    #[doc = "Bit 29 - MIPI DSI PHY reset set"]
669    #[inline(always)]
670    #[must_use]
671    pub fn mipi_dsi_phy(&mut self) -> MIPI_DSI_PHY_W<29> {
672        MIPI_DSI_PHY_W::new(self)
673    }
674    #[doc = "Bit 30 - SMARTDMA Event/Algorithm handler reset set"]
675    #[inline(always)]
676    #[must_use]
677    pub fn smartdma(&mut self) -> SMARTDMA_W<30> {
678        SMARTDMA_W::new(self)
679    }
680    #[doc = "Writes raw bits to the register."]
681    #[inline(always)]
682    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
683        self.0.bits(bits);
684        self
685    }
686}
687#[doc = "Peripheral Reset Control Register 0 SET\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prstctl0_set](index.html) module"]
688pub struct PRSTCTL0_SET_SPEC;
689impl crate::RegisterSpec for PRSTCTL0_SET_SPEC {
690    type Ux = u32;
691}
692#[doc = "`write(|w| ..)` method takes [prstctl0_set::W](W) writer structure"]
693impl crate::Writable for PRSTCTL0_SET_SPEC {
694    type Writer = W;
695    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
696    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
697}
698#[doc = "`reset()` method sets PRSTCTL0_SET to value 0"]
699impl crate::Resettable for PRSTCTL0_SET_SPEC {
700    const RESET_VALUE: Self::Ux = 0;
701}
mimxrt595s/rstctl0/prstctl0_set.rs

mimxrt595s/rstctl0/
prstctl0_set.rs
