mimxrt595s/flexspi1/
flshcr2.rs

1#[doc = "Register `FLSHCR2%s` reader"]
2pub struct R(crate::R<FLSHCR2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FLSHCR2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FLSHCR2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FLSHCR2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `FLSHCR2%s` writer"]
17pub struct W(crate::W<FLSHCR2_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FLSHCR2_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FLSHCR2_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FLSHCR2_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ARDSEQID` reader - Sequence Index for AHB Read triggered Command in LUT."]
38pub type ARDSEQID_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `ARDSEQID` writer - Sequence Index for AHB Read triggered Command in LUT."]
40pub type ARDSEQID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FLSHCR2_SPEC, u8, u8, 4, O>;
41#[doc = "Field `ARDSEQNUM` reader - Sequence Number for AHB Read triggered Command in LUT."]
42pub type ARDSEQNUM_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `ARDSEQNUM` writer - Sequence Number for AHB Read triggered Command in LUT."]
44pub type ARDSEQNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FLSHCR2_SPEC, u8, u8, 3, O>;
45#[doc = "Field `AWRSEQID` reader - Sequence Index for AHB Write triggered Command."]
46pub type AWRSEQID_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `AWRSEQID` writer - Sequence Index for AHB Write triggered Command."]
48pub type AWRSEQID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FLSHCR2_SPEC, u8, u8, 4, O>;
49#[doc = "Field `AWRSEQNUM` reader - Sequence Number for AHB Write triggered Command."]
50pub type AWRSEQNUM_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `AWRSEQNUM` writer - Sequence Number for AHB Write triggered Command."]
52pub type AWRSEQNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FLSHCR2_SPEC, u8, u8, 3, O>;
53#[doc = "Field `AWRWAIT` reader - For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface. If another Read command sequence comes before previous programming finished internally, the read data may be wrong. This field is used to hold AHB Bus ready for AHB write access to wait the programming finished in external device. Then there will be no AHB read command triggered before the programming finished in external device. The Wait cycle between AHB triggered command sequences finished on FlexSPI interface and AHB return Bus ready: AWRWAIT * AWRWAITUNIT"]
54pub type AWRWAIT_R = crate::FieldReader<u16, u16>;
55#[doc = "Field `AWRWAIT` writer - For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface. If another Read command sequence comes before previous programming finished internally, the read data may be wrong. This field is used to hold AHB Bus ready for AHB write access to wait the programming finished in external device. Then there will be no AHB read command triggered before the programming finished in external device. The Wait cycle between AHB triggered command sequences finished on FlexSPI interface and AHB return Bus ready: AWRWAIT * AWRWAITUNIT"]
56pub type AWRWAIT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FLSHCR2_SPEC, u16, u16, 12, O>;
57#[doc = "Field `AWRWAITUNIT` reader - AWRWAIT unit"]
58pub type AWRWAITUNIT_R = crate::FieldReader<u8, AWRWAITUNIT_A>;
59#[doc = "AWRWAIT unit\n\nValue on reset: 0"]
60#[derive(Clone, Copy, Debug, PartialEq, Eq)]
61#[repr(u8)]
62pub enum AWRWAITUNIT_A {
63    #[doc = "0: The AWRWAIT unit is 2 AHB clock cycle"]
64    VAL0 = 0,
65    #[doc = "1: The AWRWAIT unit is 8 AHB clock cycle"]
66    VAL1 = 1,
67    #[doc = "2: The AWRWAIT unit is 32 AHB clock cycle"]
68    VAL2 = 2,
69    #[doc = "3: The AWRWAIT unit is 128 AHB clock cycle"]
70    VAL3 = 3,
71    #[doc = "4: The AWRWAIT unit is 512 AHB clock cycle"]
72    VAL4 = 4,
73    #[doc = "5: The AWRWAIT unit is 2048 AHB clock cycle"]
74    VAL5 = 5,
75    #[doc = "6: The AWRWAIT unit is 8192 AHB clock cycle"]
76    VAL6 = 6,
77    #[doc = "7: The AWRWAIT unit is 32768 AHB clock cycle"]
78    VAL7 = 7,
79}
80impl From<AWRWAITUNIT_A> for u8 {
81    #[inline(always)]
82    fn from(variant: AWRWAITUNIT_A) -> Self {
83        variant as _
84    }
85}
86impl AWRWAITUNIT_R {
87    #[doc = "Get enumerated values variant"]
88    #[inline(always)]
89    pub fn variant(&self) -> AWRWAITUNIT_A {
90        match self.bits {
91            0 => AWRWAITUNIT_A::VAL0,
92            1 => AWRWAITUNIT_A::VAL1,
93            2 => AWRWAITUNIT_A::VAL2,
94            3 => AWRWAITUNIT_A::VAL3,
95            4 => AWRWAITUNIT_A::VAL4,
96            5 => AWRWAITUNIT_A::VAL5,
97            6 => AWRWAITUNIT_A::VAL6,
98            7 => AWRWAITUNIT_A::VAL7,
99            _ => unreachable!(),
100        }
101    }
102    #[doc = "Checks if the value of the field is `VAL0`"]
103    #[inline(always)]
104    pub fn is_val0(&self) -> bool {
105        *self == AWRWAITUNIT_A::VAL0
106    }
107    #[doc = "Checks if the value of the field is `VAL1`"]
108    #[inline(always)]
109    pub fn is_val1(&self) -> bool {
110        *self == AWRWAITUNIT_A::VAL1
111    }
112    #[doc = "Checks if the value of the field is `VAL2`"]
113    #[inline(always)]
114    pub fn is_val2(&self) -> bool {
115        *self == AWRWAITUNIT_A::VAL2
116    }
117    #[doc = "Checks if the value of the field is `VAL3`"]
118    #[inline(always)]
119    pub fn is_val3(&self) -> bool {
120        *self == AWRWAITUNIT_A::VAL3
121    }
122    #[doc = "Checks if the value of the field is `VAL4`"]
123    #[inline(always)]
124    pub fn is_val4(&self) -> bool {
125        *self == AWRWAITUNIT_A::VAL4
126    }
127    #[doc = "Checks if the value of the field is `VAL5`"]
128    #[inline(always)]
129    pub fn is_val5(&self) -> bool {
130        *self == AWRWAITUNIT_A::VAL5
131    }
132    #[doc = "Checks if the value of the field is `VAL6`"]
133    #[inline(always)]
134    pub fn is_val6(&self) -> bool {
135        *self == AWRWAITUNIT_A::VAL6
136    }
137    #[doc = "Checks if the value of the field is `VAL7`"]
138    #[inline(always)]
139    pub fn is_val7(&self) -> bool {
140        *self == AWRWAITUNIT_A::VAL7
141    }
142}
143#[doc = "Field `AWRWAITUNIT` writer - AWRWAIT unit"]
144pub type AWRWAITUNIT_W<'a, const O: u8> =
145    crate::FieldWriterSafe<'a, u32, FLSHCR2_SPEC, u8, AWRWAITUNIT_A, 3, O>;
146impl<'a, const O: u8> AWRWAITUNIT_W<'a, O> {
147    #[doc = "The AWRWAIT unit is 2 AHB clock cycle"]
148    #[inline(always)]
149    pub fn val0(self) -> &'a mut W {
150        self.variant(AWRWAITUNIT_A::VAL0)
151    }
152    #[doc = "The AWRWAIT unit is 8 AHB clock cycle"]
153    #[inline(always)]
154    pub fn val1(self) -> &'a mut W {
155        self.variant(AWRWAITUNIT_A::VAL1)
156    }
157    #[doc = "The AWRWAIT unit is 32 AHB clock cycle"]
158    #[inline(always)]
159    pub fn val2(self) -> &'a mut W {
160        self.variant(AWRWAITUNIT_A::VAL2)
161    }
162    #[doc = "The AWRWAIT unit is 128 AHB clock cycle"]
163    #[inline(always)]
164    pub fn val3(self) -> &'a mut W {
165        self.variant(AWRWAITUNIT_A::VAL3)
166    }
167    #[doc = "The AWRWAIT unit is 512 AHB clock cycle"]
168    #[inline(always)]
169    pub fn val4(self) -> &'a mut W {
170        self.variant(AWRWAITUNIT_A::VAL4)
171    }
172    #[doc = "The AWRWAIT unit is 2048 AHB clock cycle"]
173    #[inline(always)]
174    pub fn val5(self) -> &'a mut W {
175        self.variant(AWRWAITUNIT_A::VAL5)
176    }
177    #[doc = "The AWRWAIT unit is 8192 AHB clock cycle"]
178    #[inline(always)]
179    pub fn val6(self) -> &'a mut W {
180        self.variant(AWRWAITUNIT_A::VAL6)
181    }
182    #[doc = "The AWRWAIT unit is 32768 AHB clock cycle"]
183    #[inline(always)]
184    pub fn val7(self) -> &'a mut W {
185        self.variant(AWRWAITUNIT_A::VAL7)
186    }
187}
188#[doc = "Field `CLRINSTRPTR` reader - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS."]
189pub type CLRINSTRPTR_R = crate::BitReader<bool>;
190#[doc = "Field `CLRINSTRPTR` writer - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS."]
191pub type CLRINSTRPTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FLSHCR2_SPEC, bool, O>;
192impl R {
193    #[doc = "Bits 0:3 - Sequence Index for AHB Read triggered Command in LUT."]
194    #[inline(always)]
195    pub fn ardseqid(&self) -> ARDSEQID_R {
196        ARDSEQID_R::new((self.bits & 0x0f) as u8)
197    }
198    #[doc = "Bits 5:7 - Sequence Number for AHB Read triggered Command in LUT."]
199    #[inline(always)]
200    pub fn ardseqnum(&self) -> ARDSEQNUM_R {
201        ARDSEQNUM_R::new(((self.bits >> 5) & 7) as u8)
202    }
203    #[doc = "Bits 8:11 - Sequence Index for AHB Write triggered Command."]
204    #[inline(always)]
205    pub fn awrseqid(&self) -> AWRSEQID_R {
206        AWRSEQID_R::new(((self.bits >> 8) & 0x0f) as u8)
207    }
208    #[doc = "Bits 13:15 - Sequence Number for AHB Write triggered Command."]
209    #[inline(always)]
210    pub fn awrseqnum(&self) -> AWRSEQNUM_R {
211        AWRSEQNUM_R::new(((self.bits >> 13) & 7) as u8)
212    }
213    #[doc = "Bits 16:27 - For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface. If another Read command sequence comes before previous programming finished internally, the read data may be wrong. This field is used to hold AHB Bus ready for AHB write access to wait the programming finished in external device. Then there will be no AHB read command triggered before the programming finished in external device. The Wait cycle between AHB triggered command sequences finished on FlexSPI interface and AHB return Bus ready: AWRWAIT * AWRWAITUNIT"]
214    #[inline(always)]
215    pub fn awrwait(&self) -> AWRWAIT_R {
216        AWRWAIT_R::new(((self.bits >> 16) & 0x0fff) as u16)
217    }
218    #[doc = "Bits 28:30 - AWRWAIT unit"]
219    #[inline(always)]
220    pub fn awrwaitunit(&self) -> AWRWAITUNIT_R {
221        AWRWAITUNIT_R::new(((self.bits >> 28) & 7) as u8)
222    }
223    #[doc = "Bit 31 - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS."]
224    #[inline(always)]
225    pub fn clrinstrptr(&self) -> CLRINSTRPTR_R {
226        CLRINSTRPTR_R::new(((self.bits >> 31) & 1) != 0)
227    }
228}
229impl W {
230    #[doc = "Bits 0:3 - Sequence Index for AHB Read triggered Command in LUT."]
231    #[inline(always)]
232    #[must_use]
233    pub fn ardseqid(&mut self) -> ARDSEQID_W<0> {
234        ARDSEQID_W::new(self)
235    }
236    #[doc = "Bits 5:7 - Sequence Number for AHB Read triggered Command in LUT."]
237    #[inline(always)]
238    #[must_use]
239    pub fn ardseqnum(&mut self) -> ARDSEQNUM_W<5> {
240        ARDSEQNUM_W::new(self)
241    }
242    #[doc = "Bits 8:11 - Sequence Index for AHB Write triggered Command."]
243    #[inline(always)]
244    #[must_use]
245    pub fn awrseqid(&mut self) -> AWRSEQID_W<8> {
246        AWRSEQID_W::new(self)
247    }
248    #[doc = "Bits 13:15 - Sequence Number for AHB Write triggered Command."]
249    #[inline(always)]
250    #[must_use]
251    pub fn awrseqnum(&mut self) -> AWRSEQNUM_W<13> {
252        AWRSEQNUM_W::new(self)
253    }
254    #[doc = "Bits 16:27 - For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface. If another Read command sequence comes before previous programming finished internally, the read data may be wrong. This field is used to hold AHB Bus ready for AHB write access to wait the programming finished in external device. Then there will be no AHB read command triggered before the programming finished in external device. The Wait cycle between AHB triggered command sequences finished on FlexSPI interface and AHB return Bus ready: AWRWAIT * AWRWAITUNIT"]
255    #[inline(always)]
256    #[must_use]
257    pub fn awrwait(&mut self) -> AWRWAIT_W<16> {
258        AWRWAIT_W::new(self)
259    }
260    #[doc = "Bits 28:30 - AWRWAIT unit"]
261    #[inline(always)]
262    #[must_use]
263    pub fn awrwaitunit(&mut self) -> AWRWAITUNIT_W<28> {
264        AWRWAITUNIT_W::new(self)
265    }
266    #[doc = "Bit 31 - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS."]
267    #[inline(always)]
268    #[must_use]
269    pub fn clrinstrptr(&mut self) -> CLRINSTRPTR_W<31> {
270        CLRINSTRPTR_W::new(self)
271    }
272    #[doc = "Writes raw bits to the register."]
273    #[inline(always)]
274    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
275        self.0.bits(bits);
276        self
277    }
278}
279#[doc = "Flash Control Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flshcr2](index.html) module"]
280pub struct FLSHCR2_SPEC;
281impl crate::RegisterSpec for FLSHCR2_SPEC {
282    type Ux = u32;
283}
284#[doc = "`read()` method returns [flshcr2::R](R) reader structure"]
285impl crate::Readable for FLSHCR2_SPEC {
286    type Reader = R;
287}
288#[doc = "`write(|w| ..)` method takes [flshcr2::W](W) writer structure"]
289impl crate::Writable for FLSHCR2_SPEC {
290    type Writer = W;
291    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
292    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
293}
294#[doc = "`reset()` method sets FLSHCR2%s to value 0"]
295impl crate::Resettable for FLSHCR2_SPEC {
296    const RESET_VALUE: Self::Ux = 0;
297}
mimxrt595s/flexspi1/flshcr2.rs

mimxrt595s/flexspi1/
flshcr2.rs
