mimxrt595s/flexspi0/
mcr2.rs

1#[doc = "Register `MCR2` reader"]
2pub struct R(crate::R<MCR2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MCR2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MCR2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MCR2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MCR2` writer"]
17pub struct W(crate::W<MCR2_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MCR2_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MCR2_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MCR2_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CLRAHBBUFOPT` reader - Clear AHB buffer"]
38pub type CLRAHBBUFOPT_R = crate::BitReader<CLRAHBBUFOPT_A>;
39#[doc = "Clear AHB buffer\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum CLRAHBBUFOPT_A {
42    #[doc = "0: AHB RX/TX Buffer will not be cleared automatically when FlexSPI returns Stop mode ACK."]
43    VAL0 = 0,
44    #[doc = "1: AHB RX/TX Buffer will be cleared automatically when FlexSPI returns Stop mode ACK."]
45    VAL1 = 1,
46}
47impl From<CLRAHBBUFOPT_A> for bool {
48    #[inline(always)]
49    fn from(variant: CLRAHBBUFOPT_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl CLRAHBBUFOPT_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> CLRAHBBUFOPT_A {
57        match self.bits {
58            false => CLRAHBBUFOPT_A::VAL0,
59            true => CLRAHBBUFOPT_A::VAL1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `VAL0`"]
63    #[inline(always)]
64    pub fn is_val0(&self) -> bool {
65        *self == CLRAHBBUFOPT_A::VAL0
66    }
67    #[doc = "Checks if the value of the field is `VAL1`"]
68    #[inline(always)]
69    pub fn is_val1(&self) -> bool {
70        *self == CLRAHBBUFOPT_A::VAL1
71    }
72}
73#[doc = "Field `CLRAHBBUFOPT` writer - Clear AHB buffer"]
74pub type CLRAHBBUFOPT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR2_SPEC, CLRAHBBUFOPT_A, O>;
75impl<'a, const O: u8> CLRAHBBUFOPT_W<'a, O> {
76    #[doc = "AHB RX/TX Buffer will not be cleared automatically when FlexSPI returns Stop mode ACK."]
77    #[inline(always)]
78    pub fn val0(self) -> &'a mut W {
79        self.variant(CLRAHBBUFOPT_A::VAL0)
80    }
81    #[doc = "AHB RX/TX Buffer will be cleared automatically when FlexSPI returns Stop mode ACK."]
82    #[inline(always)]
83    pub fn val1(self) -> &'a mut W {
84        self.variant(CLRAHBBUFOPT_A::VAL1)
85    }
86}
87#[doc = "Field `CLRLEARNPHASE` reader - The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately."]
88pub type CLRLEARNPHASE_R = crate::BitReader<CLRLEARNPHASE_A>;
89#[doc = "The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately.\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum CLRLEARNPHASE_A {
92    #[doc = "0: No impact"]
93    VAL0 = 0,
94    #[doc = "1: The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately."]
95    VAL1 = 1,
96}
97impl From<CLRLEARNPHASE_A> for bool {
98    #[inline(always)]
99    fn from(variant: CLRLEARNPHASE_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl CLRLEARNPHASE_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> CLRLEARNPHASE_A {
107        match self.bits {
108            false => CLRLEARNPHASE_A::VAL0,
109            true => CLRLEARNPHASE_A::VAL1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `VAL0`"]
113    #[inline(always)]
114    pub fn is_val0(&self) -> bool {
115        *self == CLRLEARNPHASE_A::VAL0
116    }
117    #[doc = "Checks if the value of the field is `VAL1`"]
118    #[inline(always)]
119    pub fn is_val1(&self) -> bool {
120        *self == CLRLEARNPHASE_A::VAL1
121    }
122}
123#[doc = "Field `CLRLEARNPHASE` writer - The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately."]
124pub type CLRLEARNPHASE_W<'a, const O: u8> =
125    crate::BitWriter<'a, u32, MCR2_SPEC, CLRLEARNPHASE_A, O>;
126impl<'a, const O: u8> CLRLEARNPHASE_W<'a, O> {
127    #[doc = "No impact"]
128    #[inline(always)]
129    pub fn val0(self) -> &'a mut W {
130        self.variant(CLRLEARNPHASE_A::VAL0)
131    }
132    #[doc = "The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately."]
133    #[inline(always)]
134    pub fn val1(self) -> &'a mut W {
135        self.variant(CLRLEARNPHASE_A::VAL1)
136    }
137}
138#[doc = "Field `SAMEDEVICEEN` reader - All external devices are same devices (both in type and size) for A1/A2/B1/B2."]
139pub type SAMEDEVICEEN_R = crate::BitReader<SAMEDEVICEEN_A>;
140#[doc = "All external devices are same devices (both in type and size) for A1/A2/B1/B2.\n\nValue on reset: 1"]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum SAMEDEVICEEN_A {
143    #[doc = "0: In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register setting will be ignored."]
144    INDIVIDUAL_PARALLEL = 0,
145    #[doc = "1: FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register setting will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored."]
146    ENABLE = 1,
147}
148impl From<SAMEDEVICEEN_A> for bool {
149    #[inline(always)]
150    fn from(variant: SAMEDEVICEEN_A) -> Self {
151        variant as u8 != 0
152    }
153}
154impl SAMEDEVICEEN_R {
155    #[doc = "Get enumerated values variant"]
156    #[inline(always)]
157    pub fn variant(&self) -> SAMEDEVICEEN_A {
158        match self.bits {
159            false => SAMEDEVICEEN_A::INDIVIDUAL_PARALLEL,
160            true => SAMEDEVICEEN_A::ENABLE,
161        }
162    }
163    #[doc = "Checks if the value of the field is `INDIVIDUAL_PARALLEL`"]
164    #[inline(always)]
165    pub fn is_individual_parallel(&self) -> bool {
166        *self == SAMEDEVICEEN_A::INDIVIDUAL_PARALLEL
167    }
168    #[doc = "Checks if the value of the field is `ENABLE`"]
169    #[inline(always)]
170    pub fn is_enable(&self) -> bool {
171        *self == SAMEDEVICEEN_A::ENABLE
172    }
173}
174#[doc = "Field `SAMEDEVICEEN` writer - All external devices are same devices (both in type and size) for A1/A2/B1/B2."]
175pub type SAMEDEVICEEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR2_SPEC, SAMEDEVICEEN_A, O>;
176impl<'a, const O: u8> SAMEDEVICEEN_W<'a, O> {
177    #[doc = "In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register setting will be ignored."]
178    #[inline(always)]
179    pub fn individual_parallel(self) -> &'a mut W {
180        self.variant(SAMEDEVICEEN_A::INDIVIDUAL_PARALLEL)
181    }
182    #[doc = "FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register setting will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored."]
183    #[inline(always)]
184    pub fn enable(self) -> &'a mut W {
185        self.variant(SAMEDEVICEEN_A::ENABLE)
186    }
187}
188#[doc = "Field `RESUMEWAIT` reader - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed."]
189pub type RESUMEWAIT_R = crate::FieldReader<u8, u8>;
190#[doc = "Field `RESUMEWAIT` writer - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed."]
191pub type RESUMEWAIT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MCR2_SPEC, u8, u8, 8, O>;
192impl R {
193    #[doc = "Bit 11 - Clear AHB buffer"]
194    #[inline(always)]
195    pub fn clrahbbufopt(&self) -> CLRAHBBUFOPT_R {
196        CLRAHBBUFOPT_R::new(((self.bits >> 11) & 1) != 0)
197    }
198    #[doc = "Bit 14 - The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately."]
199    #[inline(always)]
200    pub fn clrlearnphase(&self) -> CLRLEARNPHASE_R {
201        CLRLEARNPHASE_R::new(((self.bits >> 14) & 1) != 0)
202    }
203    #[doc = "Bit 15 - All external devices are same devices (both in type and size) for A1/A2/B1/B2."]
204    #[inline(always)]
205    pub fn samedeviceen(&self) -> SAMEDEVICEEN_R {
206        SAMEDEVICEEN_R::new(((self.bits >> 15) & 1) != 0)
207    }
208    #[doc = "Bits 24:31 - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed."]
209    #[inline(always)]
210    pub fn resumewait(&self) -> RESUMEWAIT_R {
211        RESUMEWAIT_R::new(((self.bits >> 24) & 0xff) as u8)
212    }
213}
214impl W {
215    #[doc = "Bit 11 - Clear AHB buffer"]
216    #[inline(always)]
217    #[must_use]
218    pub fn clrahbbufopt(&mut self) -> CLRAHBBUFOPT_W<11> {
219        CLRAHBBUFOPT_W::new(self)
220    }
221    #[doc = "Bit 14 - The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately."]
222    #[inline(always)]
223    #[must_use]
224    pub fn clrlearnphase(&mut self) -> CLRLEARNPHASE_W<14> {
225        CLRLEARNPHASE_W::new(self)
226    }
227    #[doc = "Bit 15 - All external devices are same devices (both in type and size) for A1/A2/B1/B2."]
228    #[inline(always)]
229    #[must_use]
230    pub fn samedeviceen(&mut self) -> SAMEDEVICEEN_W<15> {
231        SAMEDEVICEEN_W::new(self)
232    }
233    #[doc = "Bits 24:31 - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed."]
234    #[inline(always)]
235    #[must_use]
236    pub fn resumewait(&mut self) -> RESUMEWAIT_W<24> {
237        RESUMEWAIT_W::new(self)
238    }
239    #[doc = "Writes raw bits to the register."]
240    #[inline(always)]
241    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
242        self.0.bits(bits);
243        self
244    }
245}
246#[doc = "Module Control Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr2](index.html) module"]
247pub struct MCR2_SPEC;
248impl crate::RegisterSpec for MCR2_SPEC {
249    type Ux = u32;
250}
251#[doc = "`read()` method returns [mcr2::R](R) reader structure"]
252impl crate::Readable for MCR2_SPEC {
253    type Reader = R;
254}
255#[doc = "`write(|w| ..)` method takes [mcr2::W](W) writer structure"]
256impl crate::Writable for MCR2_SPEC {
257    type Writer = W;
258    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
259    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
260}
261#[doc = "`reset()` method sets MCR2 to value 0x2000_81f7"]
262impl crate::Resettable for MCR2_SPEC {
263    const RESET_VALUE: Self::Ux = 0x2000_81f7;
264}
mimxrt595s/flexspi0/mcr2.rs

mimxrt595s/flexspi0/
mcr2.rs
