mimxrt595s/clkctl0/
pscctl1_set.rs

1#[doc = "Register `PSCCTL1_SET` writer"]
2pub struct W(crate::W<PSCCTL1_SET_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<PSCCTL1_SET_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<PSCCTL1_SET_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<PSCCTL1_SET_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "SDIO0 clock set\n\nValue on reset: 0"]
23#[derive(Clone, Copy, Debug, PartialEq, Eq)]
24pub enum SDIO0_CLK_AW {
25    #[doc = "0: No effect"]
26    NO_EFFECT = 0,
27    #[doc = "1: Sets the corresponding bit in PSCCTL1 register"]
28    CLK_ENABLE_SET = 1,
29}
30impl From<SDIO0_CLK_AW> for bool {
31    #[inline(always)]
32    fn from(variant: SDIO0_CLK_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36#[doc = "Field `SDIO0_CLK` writer - SDIO0 clock set"]
37pub type SDIO0_CLK_W<'a, const O: u8> =
38    crate::BitWriter<'a, u32, PSCCTL1_SET_SPEC, SDIO0_CLK_AW, O>;
39impl<'a, const O: u8> SDIO0_CLK_W<'a, O> {
40    #[doc = "No effect"]
41    #[inline(always)]
42    pub fn no_effect(self) -> &'a mut W {
43        self.variant(SDIO0_CLK_AW::NO_EFFECT)
44    }
45    #[doc = "Sets the corresponding bit in PSCCTL1 register"]
46    #[inline(always)]
47    pub fn clk_enable_set(self) -> &'a mut W {
48        self.variant(SDIO0_CLK_AW::CLK_ENABLE_SET)
49    }
50}
51#[doc = "SDIO1 clock set\n\nValue on reset: 0"]
52#[derive(Clone, Copy, Debug, PartialEq, Eq)]
53pub enum SDIO1_CLK_AW {
54    #[doc = "0: No effect"]
55    NO_EFFECT = 0,
56    #[doc = "1: Sets the corresponding bit in PSCCTL1 register"]
57    CLK_ENABLE_SET = 1,
58}
59impl From<SDIO1_CLK_AW> for bool {
60    #[inline(always)]
61    fn from(variant: SDIO1_CLK_AW) -> Self {
62        variant as u8 != 0
63    }
64}
65#[doc = "Field `SDIO1_CLK` writer - SDIO1 clock set"]
66pub type SDIO1_CLK_W<'a, const O: u8> =
67    crate::BitWriter<'a, u32, PSCCTL1_SET_SPEC, SDIO1_CLK_AW, O>;
68impl<'a, const O: u8> SDIO1_CLK_W<'a, O> {
69    #[doc = "No effect"]
70    #[inline(always)]
71    pub fn no_effect(self) -> &'a mut W {
72        self.variant(SDIO1_CLK_AW::NO_EFFECT)
73    }
74    #[doc = "Sets the corresponding bit in PSCCTL1 register"]
75    #[inline(always)]
76    pub fn clk_enable_set(self) -> &'a mut W {
77        self.variant(SDIO1_CLK_AW::CLK_ENABLE_SET)
78    }
79}
80#[doc = "ACMP0 clock set\n\nValue on reset: 0"]
81#[derive(Clone, Copy, Debug, PartialEq, Eq)]
82pub enum ACMP0_CLK_AW {
83    #[doc = "0: No effect"]
84    NO_EFFECT = 0,
85    #[doc = "1: Sets the corresponding bit in PSCCTL1 register"]
86    CLK_ENABLE_SET = 1,
87}
88impl From<ACMP0_CLK_AW> for bool {
89    #[inline(always)]
90    fn from(variant: ACMP0_CLK_AW) -> Self {
91        variant as u8 != 0
92    }
93}
94#[doc = "Field `ACMP0_CLK` writer - ACMP0 clock set"]
95pub type ACMP0_CLK_W<'a, const O: u8> =
96    crate::BitWriter<'a, u32, PSCCTL1_SET_SPEC, ACMP0_CLK_AW, O>;
97impl<'a, const O: u8> ACMP0_CLK_W<'a, O> {
98    #[doc = "No effect"]
99    #[inline(always)]
100    pub fn no_effect(self) -> &'a mut W {
101        self.variant(ACMP0_CLK_AW::NO_EFFECT)
102    }
103    #[doc = "Sets the corresponding bit in PSCCTL1 register"]
104    #[inline(always)]
105    pub fn clk_enable_set(self) -> &'a mut W {
106        self.variant(ACMP0_CLK_AW::CLK_ENABLE_SET)
107    }
108}
109#[doc = "ADC0 clock set\n\nValue on reset: 0"]
110#[derive(Clone, Copy, Debug, PartialEq, Eq)]
111pub enum ADC0_CLK_AW {
112    #[doc = "0: No effect"]
113    NO_EFFECT = 0,
114    #[doc = "1: Sets the corresponding bit in PSCCTL1 register"]
115    CLK_ENABLE_SET = 1,
116}
117impl From<ADC0_CLK_AW> for bool {
118    #[inline(always)]
119    fn from(variant: ADC0_CLK_AW) -> Self {
120        variant as u8 != 0
121    }
122}
123#[doc = "Field `ADC0_CLK` writer - ADC0 clock set"]
124pub type ADC0_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PSCCTL1_SET_SPEC, ADC0_CLK_AW, O>;
125impl<'a, const O: u8> ADC0_CLK_W<'a, O> {
126    #[doc = "No effect"]
127    #[inline(always)]
128    pub fn no_effect(self) -> &'a mut W {
129        self.variant(ADC0_CLK_AW::NO_EFFECT)
130    }
131    #[doc = "Sets the corresponding bit in PSCCTL1 register"]
132    #[inline(always)]
133    pub fn clk_enable_set(self) -> &'a mut W {
134        self.variant(ADC0_CLK_AW::CLK_ENABLE_SET)
135    }
136}
137#[doc = "SHSGPIO0 clock set\n\nValue on reset: 0"]
138#[derive(Clone, Copy, Debug, PartialEq, Eq)]
139pub enum SHSGPIO0_CLK_AW {
140    #[doc = "0: No effect"]
141    NO_EFFECT = 0,
142    #[doc = "1: Sets the corresponding bit in PSCCTL1 register"]
143    CLK_ENABLE_SET = 1,
144}
145impl From<SHSGPIO0_CLK_AW> for bool {
146    #[inline(always)]
147    fn from(variant: SHSGPIO0_CLK_AW) -> Self {
148        variant as u8 != 0
149    }
150}
151#[doc = "Field `SHSGPIO0_CLK` writer - SHSGPIO0 clock set"]
152pub type SHSGPIO0_CLK_W<'a, const O: u8> =
153    crate::BitWriter<'a, u32, PSCCTL1_SET_SPEC, SHSGPIO0_CLK_AW, O>;
154impl<'a, const O: u8> SHSGPIO0_CLK_W<'a, O> {
155    #[doc = "No effect"]
156    #[inline(always)]
157    pub fn no_effect(self) -> &'a mut W {
158        self.variant(SHSGPIO0_CLK_AW::NO_EFFECT)
159    }
160    #[doc = "Sets the corresponding bit in PSCCTL1 register"]
161    #[inline(always)]
162    pub fn clk_enable_set(self) -> &'a mut W {
163        self.variant(SHSGPIO0_CLK_AW::CLK_ENABLE_SET)
164    }
165}
166impl W {
167    #[doc = "Bit 2 - SDIO0 clock set"]
168    #[inline(always)]
169    #[must_use]
170    pub fn sdio0_clk(&mut self) -> SDIO0_CLK_W<2> {
171        SDIO0_CLK_W::new(self)
172    }
173    #[doc = "Bit 3 - SDIO1 clock set"]
174    #[inline(always)]
175    #[must_use]
176    pub fn sdio1_clk(&mut self) -> SDIO1_CLK_W<3> {
177        SDIO1_CLK_W::new(self)
178    }
179    #[doc = "Bit 15 - ACMP0 clock set"]
180    #[inline(always)]
181    #[must_use]
182    pub fn acmp0_clk(&mut self) -> ACMP0_CLK_W<15> {
183        ACMP0_CLK_W::new(self)
184    }
185    #[doc = "Bit 16 - ADC0 clock set"]
186    #[inline(always)]
187    #[must_use]
188    pub fn adc0_clk(&mut self) -> ADC0_CLK_W<16> {
189        ADC0_CLK_W::new(self)
190    }
191    #[doc = "Bit 24 - SHSGPIO0 clock set"]
192    #[inline(always)]
193    #[must_use]
194    pub fn shsgpio0_clk(&mut self) -> SHSGPIO0_CLK_W<24> {
195        SHSGPIO0_CLK_W::new(self)
196    }
197    #[doc = "Writes raw bits to the register."]
198    #[inline(always)]
199    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
200        self.0.bits(bits);
201        self
202    }
203}
204#[doc = "Clock Control 1 Set\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pscctl1_set](index.html) module"]
205pub struct PSCCTL1_SET_SPEC;
206impl crate::RegisterSpec for PSCCTL1_SET_SPEC {
207    type Ux = u32;
208}
209#[doc = "`write(|w| ..)` method takes [pscctl1_set::W](W) writer structure"]
210impl crate::Writable for PSCCTL1_SET_SPEC {
211    type Writer = W;
212    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
213    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
214}
215#[doc = "`reset()` method sets PSCCTL1_SET to value 0"]
216impl crate::Resettable for PSCCTL1_SET_SPEC {
217    const RESET_VALUE: Self::Ux = 0;
218}
mimxrt595s/clkctl0/pscctl1_set.rs

mimxrt595s/clkctl0/
pscctl1_set.rs
