1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Miscellaneous Control Register"]
5 pub mctl: MCTL,
6 #[doc = "0x04 - Statistical Check Miscellaneous Register"]
7 pub scmisc: SCMISC,
8 #[doc = "0x08 - Poker Range Register"]
9 pub pkrrng: PKRRNG,
10 _reserved_3_max_sq: [u8; 0x04],
11 #[doc = "0x10 - Seed Control Register"]
12 pub sdctl: SDCTL,
13 _reserved_5_sblim_totsam: [u8; 0x04],
14 #[doc = "0x18 - Frequency Count Minimum Limit Register"]
15 pub frqmin: FRQMIN,
16 _reserved_7_max_cnt: [u8; 0x04],
17 _reserved_8_scml_mc: [u8; 0x04],
18 _reserved_9_scr1l_1c_scr: [u8; 0x04],
19 _reserved_10_scr2l_2c_scr: [u8; 0x04],
20 _reserved_11_scr3l_3c_scr: [u8; 0x04],
21 _reserved_12_scr4l_4c_scr: [u8; 0x04],
22 _reserved_13_scr5l_5c_scr: [u8; 0x04],
23 _reserved_14_scr6pl_pc_scr: [u8; 0x04],
24 #[doc = "0x3c - Status Register"]
25 pub status: STATUS,
26 #[doc = "0x40..0x80 - Entropy Read Register"]
27 pub ent: [ENT; 16],
28 #[doc = "0x80 - Statistical Check Poker Count 1 and 0 Register"]
29 pub pkrcnt10: PKRCNT10,
30 #[doc = "0x84 - Statistical Check Poker Count 3 and 2 Register"]
31 pub pkrcnt32: PKRCNT32,
32 #[doc = "0x88 - Statistical Check Poker Count 5 and 4 Register"]
33 pub pkrcnt54: PKRCNT54,
34 #[doc = "0x8c - Statistical Check Poker Count 7 and 6 Register"]
35 pub pkrcnt76: PKRCNT76,
36 #[doc = "0x90 - Statistical Check Poker Count 9 and 8 Register"]
37 pub pkrcnt98: PKRCNT98,
38 #[doc = "0x94 - Statistical Check Poker Count B and A Register"]
39 pub pkrcntba: PKRCNTBA,
40 #[doc = "0x98 - Statistical Check Poker Count D and C Register"]
41 pub pkrcntdc: PKRCNTDC,
42 #[doc = "0x9c - Statistical Check Poker Count F and E Register"]
43 pub pkrcntfe: PKRCNTFE,
44 #[doc = "0xa0 - Security Configuration Register"]
45 pub sec_cfg: SEC_CFG,
46 #[doc = "0xa4 - Interrupt Control Register"]
47 pub int_ctrl: INT_CTRL,
48 #[doc = "0xa8 - Mask Register"]
49 pub int_mask: INT_MASK,
50 #[doc = "0xac - Interrupt Status Register"]
51 pub int_status: INT_STATUS,
52 _reserved29: [u8; 0x40],
53 #[doc = "0xf0 - Version ID Register (MS)"]
54 pub vid1: VID1,
55 #[doc = "0xf4 - Version ID Register (LS)"]
56 pub vid2: VID2,
57}
58impl RegisterBlock {
59 #[doc = "0x0c - Poker Square Calculation Result Register"]
60 #[inline(always)]
61 pub const fn max_sq_pkrsq(&self) -> &MAX_SQ_PKRSQ {
62 unsafe { &*(self as *const Self).cast::<u8>().add(12usize).cast() }
63 }
64 #[doc = "0x0c - Poker Maximum Limit Register"]
65 #[inline(always)]
66 pub const fn max_sq_pkrmax(&self) -> &MAX_SQ_PKRMAX {
67 unsafe { &*(self as *const Self).cast::<u8>().add(12usize).cast() }
68 }
69 #[doc = "0x14 - Total Samples Register"]
70 #[inline(always)]
71 pub const fn sblim_totsam_totsam(&self) -> &SBLIM_TOTSAM_TOTSAM {
72 unsafe { &*(self as *const Self).cast::<u8>().add(20usize).cast() }
73 }
74 #[doc = "0x14 - Sparse Bit Limit Register"]
75 #[inline(always)]
76 pub const fn sblim_totsam_sblim(&self) -> &SBLIM_TOTSAM_SBLIM {
77 unsafe { &*(self as *const Self).cast::<u8>().add(20usize).cast() }
78 }
79 #[doc = "0x1c - Frequency Count Maximum Limit Register"]
80 #[inline(always)]
81 pub const fn max_cnt_frqmax(&self) -> &MAX_CNT_FRQMAX {
82 unsafe { &*(self as *const Self).cast::<u8>().add(28usize).cast() }
83 }
84 #[doc = "0x1c - Frequency Count Register"]
85 #[inline(always)]
86 pub const fn max_cnt_frqcnt(&self) -> &MAX_CNT_FRQCNT {
87 unsafe { &*(self as *const Self).cast::<u8>().add(28usize).cast() }
88 }
89 #[doc = "0x20 - Statistical Check Monobit Limit Register"]
90 #[inline(always)]
91 pub const fn scml_mc_scml(&self) -> &SCML_MC_SCML {
92 unsafe { &*(self as *const Self).cast::<u8>().add(32usize).cast() }
93 }
94 #[doc = "0x20 - Statistical Check Monobit Count Register"]
95 #[inline(always)]
96 pub const fn scml_mc_scmc(&self) -> &SCML_MC_SCMC {
97 unsafe { &*(self as *const Self).cast::<u8>().add(32usize).cast() }
98 }
99 #[doc = "0x24 - Statistical Check Run Length 1 Limit Register"]
100 #[inline(always)]
101 pub const fn scr1l_1c_scr1l(&self) -> &SCR1L_1C_SCR1L {
102 unsafe { &*(self as *const Self).cast::<u8>().add(36usize).cast() }
103 }
104 #[doc = "0x24 - Statistical Check Run Length 1 Count Register"]
105 #[inline(always)]
106 pub const fn scr1l_1c_scr1c(&self) -> &SCR1L_1C_SCR1C {
107 unsafe { &*(self as *const Self).cast::<u8>().add(36usize).cast() }
108 }
109 #[doc = "0x28 - Statistical Check Run Length 2 Limit Register"]
110 #[inline(always)]
111 pub const fn scr2l_2c_scr2l(&self) -> &SCR2L_2C_SCR2L {
112 unsafe { &*(self as *const Self).cast::<u8>().add(40usize).cast() }
113 }
114 #[doc = "0x28 - Statistical Check Run Length 2 Count Register"]
115 #[inline(always)]
116 pub const fn scr2l_2c_scr2c(&self) -> &SCR2L_2C_SCR2C {
117 unsafe { &*(self as *const Self).cast::<u8>().add(40usize).cast() }
118 }
119 #[doc = "0x2c - Statistical Check Run Length 3 Limit Register"]
120 #[inline(always)]
121 pub const fn scr3l_3c_scr3l(&self) -> &SCR3L_3C_SCR3L {
122 unsafe { &*(self as *const Self).cast::<u8>().add(44usize).cast() }
123 }
124 #[doc = "0x2c - Statistical Check Run Length 3 Count Register"]
125 #[inline(always)]
126 pub const fn scr3l_3c_scr3c(&self) -> &SCR3L_3C_SCR3C {
127 unsafe { &*(self as *const Self).cast::<u8>().add(44usize).cast() }
128 }
129 #[doc = "0x30 - Statistical Check Run Length 4 Limit Register"]
130 #[inline(always)]
131 pub const fn scr4l_4c_scr4l(&self) -> &SCR4L_4C_SCR4L {
132 unsafe { &*(self as *const Self).cast::<u8>().add(48usize).cast() }
133 }
134 #[doc = "0x30 - Statistical Check Run Length 4 Count Register"]
135 #[inline(always)]
136 pub const fn scr4l_4c_scr4c(&self) -> &SCR4L_4C_SCR4C {
137 unsafe { &*(self as *const Self).cast::<u8>().add(48usize).cast() }
138 }
139 #[doc = "0x34 - Statistical Check Run Length 5 Limit Register"]
140 #[inline(always)]
141 pub const fn scr5l_5c_scr5l(&self) -> &SCR5L_5C_SCR5L {
142 unsafe { &*(self as *const Self).cast::<u8>().add(52usize).cast() }
143 }
144 #[doc = "0x34 - Statistical Check Run Length 5 Count Register"]
145 #[inline(always)]
146 pub const fn scr5l_5c_scr5c(&self) -> &SCR5L_5C_SCR5C {
147 unsafe { &*(self as *const Self).cast::<u8>().add(52usize).cast() }
148 }
149 #[doc = "0x38 - Statistical Check Run Length 6+ Limit Register"]
150 #[inline(always)]
151 pub const fn scr6pl_pc_scr6pl(&self) -> &SCR6PL_PC_SCR6PL {
152 unsafe { &*(self as *const Self).cast::<u8>().add(56usize).cast() }
153 }
154 #[doc = "0x38 - Statistical Check Run Length 6+ Count Register"]
155 #[inline(always)]
156 pub const fn scr6pl_pc_scr6pc(&self) -> &SCR6PL_PC_SCR6PC {
157 unsafe { &*(self as *const Self).cast::<u8>().add(56usize).cast() }
158 }
159}
160#[doc = "MCTL (rw) register accessor: an alias for `Reg<MCTL_SPEC>`"]
161pub type MCTL = crate::Reg<mctl::MCTL_SPEC>;
162#[doc = "Miscellaneous Control Register"]
163pub mod mctl;
164#[doc = "SCMISC (rw) register accessor: an alias for `Reg<SCMISC_SPEC>`"]
165pub type SCMISC = crate::Reg<scmisc::SCMISC_SPEC>;
166#[doc = "Statistical Check Miscellaneous Register"]
167pub mod scmisc;
168#[doc = "PKRRNG (rw) register accessor: an alias for `Reg<PKRRNG_SPEC>`"]
169pub type PKRRNG = crate::Reg<pkrrng::PKRRNG_SPEC>;
170#[doc = "Poker Range Register"]
171pub mod pkrrng;
172#[doc = "MAX_SQ_PKRMAX (rw) register accessor: an alias for `Reg<MAX_SQ_PKRMAX_SPEC>`"]
173pub type MAX_SQ_PKRMAX = crate::Reg<max_sq_pkrmax::MAX_SQ_PKRMAX_SPEC>;
174#[doc = "Poker Maximum Limit Register"]
175pub mod max_sq_pkrmax;
176#[doc = "MAX_SQ_PKRSQ (r) register accessor: an alias for `Reg<MAX_SQ_PKRSQ_SPEC>`"]
177pub type MAX_SQ_PKRSQ = crate::Reg<max_sq_pkrsq::MAX_SQ_PKRSQ_SPEC>;
178#[doc = "Poker Square Calculation Result Register"]
179pub mod max_sq_pkrsq;
180#[doc = "SDCTL (rw) register accessor: an alias for `Reg<SDCTL_SPEC>`"]
181pub type SDCTL = crate::Reg<sdctl::SDCTL_SPEC>;
182#[doc = "Seed Control Register"]
183pub mod sdctl;
184#[doc = "SBLIM_TOTSAM_SBLIM (rw) register accessor: an alias for `Reg<SBLIM_TOTSAM_SBLIM_SPEC>`"]
185pub type SBLIM_TOTSAM_SBLIM = crate::Reg<sblim_totsam_sblim::SBLIM_TOTSAM_SBLIM_SPEC>;
186#[doc = "Sparse Bit Limit Register"]
187pub mod sblim_totsam_sblim;
188#[doc = "SBLIM_TOTSAM_TOTSAM (r) register accessor: an alias for `Reg<SBLIM_TOTSAM_TOTSAM_SPEC>`"]
189pub type SBLIM_TOTSAM_TOTSAM = crate::Reg<sblim_totsam_totsam::SBLIM_TOTSAM_TOTSAM_SPEC>;
190#[doc = "Total Samples Register"]
191pub mod sblim_totsam_totsam;
192#[doc = "FRQMIN (rw) register accessor: an alias for `Reg<FRQMIN_SPEC>`"]
193pub type FRQMIN = crate::Reg<frqmin::FRQMIN_SPEC>;
194#[doc = "Frequency Count Minimum Limit Register"]
195pub mod frqmin;
196#[doc = "MAX_CNT_FRQCNT (r) register accessor: an alias for `Reg<MAX_CNT_FRQCNT_SPEC>`"]
197pub type MAX_CNT_FRQCNT = crate::Reg<max_cnt_frqcnt::MAX_CNT_FRQCNT_SPEC>;
198#[doc = "Frequency Count Register"]
199pub mod max_cnt_frqcnt;
200#[doc = "MAX_CNT_FRQMAX (rw) register accessor: an alias for `Reg<MAX_CNT_FRQMAX_SPEC>`"]
201pub type MAX_CNT_FRQMAX = crate::Reg<max_cnt_frqmax::MAX_CNT_FRQMAX_SPEC>;
202#[doc = "Frequency Count Maximum Limit Register"]
203pub mod max_cnt_frqmax;
204#[doc = "SCML_MC_SCMC (r) register accessor: an alias for `Reg<SCML_MC_SCMC_SPEC>`"]
205pub type SCML_MC_SCMC = crate::Reg<scml_mc_scmc::SCML_MC_SCMC_SPEC>;
206#[doc = "Statistical Check Monobit Count Register"]
207pub mod scml_mc_scmc;
208#[doc = "SCML_MC_SCML (rw) register accessor: an alias for `Reg<SCML_MC_SCML_SPEC>`"]
209pub type SCML_MC_SCML = crate::Reg<scml_mc_scml::SCML_MC_SCML_SPEC>;
210#[doc = "Statistical Check Monobit Limit Register"]
211pub mod scml_mc_scml;
212#[doc = "SCR1L_1C_SCR1C (r) register accessor: an alias for `Reg<SCR1L_1C_SCR1C_SPEC>`"]
213pub type SCR1L_1C_SCR1C = crate::Reg<scr1l_1c_scr1c::SCR1L_1C_SCR1C_SPEC>;
214#[doc = "Statistical Check Run Length 1 Count Register"]
215pub mod scr1l_1c_scr1c;
216#[doc = "SCR1L_1C_SCR1L (rw) register accessor: an alias for `Reg<SCR1L_1C_SCR1L_SPEC>`"]
217pub type SCR1L_1C_SCR1L = crate::Reg<scr1l_1c_scr1l::SCR1L_1C_SCR1L_SPEC>;
218#[doc = "Statistical Check Run Length 1 Limit Register"]
219pub mod scr1l_1c_scr1l;
220#[doc = "SCR2L_2C_SCR2C (r) register accessor: an alias for `Reg<SCR2L_2C_SCR2C_SPEC>`"]
221pub type SCR2L_2C_SCR2C = crate::Reg<scr2l_2c_scr2c::SCR2L_2C_SCR2C_SPEC>;
222#[doc = "Statistical Check Run Length 2 Count Register"]
223pub mod scr2l_2c_scr2c;
224#[doc = "SCR2L_2C_SCR2L (rw) register accessor: an alias for `Reg<SCR2L_2C_SCR2L_SPEC>`"]
225pub type SCR2L_2C_SCR2L = crate::Reg<scr2l_2c_scr2l::SCR2L_2C_SCR2L_SPEC>;
226#[doc = "Statistical Check Run Length 2 Limit Register"]
227pub mod scr2l_2c_scr2l;
228#[doc = "SCR3L_3C_SCR3C (r) register accessor: an alias for `Reg<SCR3L_3C_SCR3C_SPEC>`"]
229pub type SCR3L_3C_SCR3C = crate::Reg<scr3l_3c_scr3c::SCR3L_3C_SCR3C_SPEC>;
230#[doc = "Statistical Check Run Length 3 Count Register"]
231pub mod scr3l_3c_scr3c;
232#[doc = "SCR3L_3C_SCR3L (rw) register accessor: an alias for `Reg<SCR3L_3C_SCR3L_SPEC>`"]
233pub type SCR3L_3C_SCR3L = crate::Reg<scr3l_3c_scr3l::SCR3L_3C_SCR3L_SPEC>;
234#[doc = "Statistical Check Run Length 3 Limit Register"]
235pub mod scr3l_3c_scr3l;
236#[doc = "SCR4L_4C_SCR4C (r) register accessor: an alias for `Reg<SCR4L_4C_SCR4C_SPEC>`"]
237pub type SCR4L_4C_SCR4C = crate::Reg<scr4l_4c_scr4c::SCR4L_4C_SCR4C_SPEC>;
238#[doc = "Statistical Check Run Length 4 Count Register"]
239pub mod scr4l_4c_scr4c;
240#[doc = "SCR4L_4C_SCR4L (rw) register accessor: an alias for `Reg<SCR4L_4C_SCR4L_SPEC>`"]
241pub type SCR4L_4C_SCR4L = crate::Reg<scr4l_4c_scr4l::SCR4L_4C_SCR4L_SPEC>;
242#[doc = "Statistical Check Run Length 4 Limit Register"]
243pub mod scr4l_4c_scr4l;
244#[doc = "SCR5L_5C_SCR5C (r) register accessor: an alias for `Reg<SCR5L_5C_SCR5C_SPEC>`"]
245pub type SCR5L_5C_SCR5C = crate::Reg<scr5l_5c_scr5c::SCR5L_5C_SCR5C_SPEC>;
246#[doc = "Statistical Check Run Length 5 Count Register"]
247pub mod scr5l_5c_scr5c;
248#[doc = "SCR5L_5C_SCR5L (rw) register accessor: an alias for `Reg<SCR5L_5C_SCR5L_SPEC>`"]
249pub type SCR5L_5C_SCR5L = crate::Reg<scr5l_5c_scr5l::SCR5L_5C_SCR5L_SPEC>;
250#[doc = "Statistical Check Run Length 5 Limit Register"]
251pub mod scr5l_5c_scr5l;
252#[doc = "SCR6PL_PC_SCR6PC (r) register accessor: an alias for `Reg<SCR6PL_PC_SCR6PC_SPEC>`"]
253pub type SCR6PL_PC_SCR6PC = crate::Reg<scr6pl_pc_scr6pc::SCR6PL_PC_SCR6PC_SPEC>;
254#[doc = "Statistical Check Run Length 6+ Count Register"]
255pub mod scr6pl_pc_scr6pc;
256#[doc = "SCR6PL_PC_SCR6PL (rw) register accessor: an alias for `Reg<SCR6PL_PC_SCR6PL_SPEC>`"]
257pub type SCR6PL_PC_SCR6PL = crate::Reg<scr6pl_pc_scr6pl::SCR6PL_PC_SCR6PL_SPEC>;
258#[doc = "Statistical Check Run Length 6+ Limit Register"]
259pub mod scr6pl_pc_scr6pl;
260#[doc = "STATUS (r) register accessor: an alias for `Reg<STATUS_SPEC>`"]
261pub type STATUS = crate::Reg<status::STATUS_SPEC>;
262#[doc = "Status Register"]
263pub mod status;
264#[doc = "ENT (r) register accessor: an alias for `Reg<ENT_SPEC>`"]
265pub type ENT = crate::Reg<ent::ENT_SPEC>;
266#[doc = "Entropy Read Register"]
267pub mod ent;
268#[doc = "PKRCNT10 (r) register accessor: an alias for `Reg<PKRCNT10_SPEC>`"]
269pub type PKRCNT10 = crate::Reg<pkrcnt10::PKRCNT10_SPEC>;
270#[doc = "Statistical Check Poker Count 1 and 0 Register"]
271pub mod pkrcnt10;
272#[doc = "PKRCNT32 (r) register accessor: an alias for `Reg<PKRCNT32_SPEC>`"]
273pub type PKRCNT32 = crate::Reg<pkrcnt32::PKRCNT32_SPEC>;
274#[doc = "Statistical Check Poker Count 3 and 2 Register"]
275pub mod pkrcnt32;
276#[doc = "PKRCNT54 (r) register accessor: an alias for `Reg<PKRCNT54_SPEC>`"]
277pub type PKRCNT54 = crate::Reg<pkrcnt54::PKRCNT54_SPEC>;
278#[doc = "Statistical Check Poker Count 5 and 4 Register"]
279pub mod pkrcnt54;
280#[doc = "PKRCNT76 (r) register accessor: an alias for `Reg<PKRCNT76_SPEC>`"]
281pub type PKRCNT76 = crate::Reg<pkrcnt76::PKRCNT76_SPEC>;
282#[doc = "Statistical Check Poker Count 7 and 6 Register"]
283pub mod pkrcnt76;
284#[doc = "PKRCNT98 (r) register accessor: an alias for `Reg<PKRCNT98_SPEC>`"]
285pub type PKRCNT98 = crate::Reg<pkrcnt98::PKRCNT98_SPEC>;
286#[doc = "Statistical Check Poker Count 9 and 8 Register"]
287pub mod pkrcnt98;
288#[doc = "PKRCNTBA (r) register accessor: an alias for `Reg<PKRCNTBA_SPEC>`"]
289pub type PKRCNTBA = crate::Reg<pkrcntba::PKRCNTBA_SPEC>;
290#[doc = "Statistical Check Poker Count B and A Register"]
291pub mod pkrcntba;
292#[doc = "PKRCNTDC (r) register accessor: an alias for `Reg<PKRCNTDC_SPEC>`"]
293pub type PKRCNTDC = crate::Reg<pkrcntdc::PKRCNTDC_SPEC>;
294#[doc = "Statistical Check Poker Count D and C Register"]
295pub mod pkrcntdc;
296#[doc = "PKRCNTFE (r) register accessor: an alias for `Reg<PKRCNTFE_SPEC>`"]
297pub type PKRCNTFE = crate::Reg<pkrcntfe::PKRCNTFE_SPEC>;
298#[doc = "Statistical Check Poker Count F and E Register"]
299pub mod pkrcntfe;
300#[doc = "SEC_CFG (rw) register accessor: an alias for `Reg<SEC_CFG_SPEC>`"]
301pub type SEC_CFG = crate::Reg<sec_cfg::SEC_CFG_SPEC>;
302#[doc = "Security Configuration Register"]
303pub mod sec_cfg;
304#[doc = "INT_CTRL (rw) register accessor: an alias for `Reg<INT_CTRL_SPEC>`"]
305pub type INT_CTRL = crate::Reg<int_ctrl::INT_CTRL_SPEC>;
306#[doc = "Interrupt Control Register"]
307pub mod int_ctrl;
308#[doc = "INT_MASK (rw) register accessor: an alias for `Reg<INT_MASK_SPEC>`"]
309pub type INT_MASK = crate::Reg<int_mask::INT_MASK_SPEC>;
310#[doc = "Mask Register"]
311pub mod int_mask;
312#[doc = "INT_STATUS (r) register accessor: an alias for `Reg<INT_STATUS_SPEC>`"]
313pub type INT_STATUS = crate::Reg<int_status::INT_STATUS_SPEC>;
314#[doc = "Interrupt Status Register"]
315pub mod int_status;
316#[doc = "VID1 (r) register accessor: an alias for `Reg<VID1_SPEC>`"]
317pub type VID1 = crate::Reg<vid1::VID1_SPEC>;
318#[doc = "Version ID Register (MS)"]
319pub mod vid1;
320#[doc = "VID2 (r) register accessor: an alias for `Reg<VID2_SPEC>`"]
321pub type VID2 = crate::Reg<vid2::VID2_SPEC>;
322#[doc = "Version ID Register (LS)"]
323pub mod vid2;