1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 0x10],
5 #[doc = "0x10..0x20 - Memory ROM Rule(n) Register"]
6 pub rom_mem_rule: [ROM_MEM_RULE; 4],
7 _reserved1: [u8; 0x10],
8 #[doc = "0x30..0x40 - FLEXSPI0 Region 0 Rule(n) Register"]
9 pub flexspi0_region0_rule: [FLEXSPI0_REGION0_RULE; 4],
10 #[doc = "0x40 - no description available"]
11 pub flexspi0_region1_4_rule0: FLEXSPI0_REGION1_4_RULE,
12 _reserved3: [u8; 0x0c],
13 #[doc = "0x50 - no description available"]
14 pub flexspi0_region1_4_rule1: FLEXSPI0_REGION1_4_RULE,
15 _reserved4: [u8; 0x0c],
16 #[doc = "0x60 - no description available"]
17 pub flexspi0_region1_4_rule2: FLEXSPI0_REGION1_4_RULE,
18 _reserved5: [u8; 0x0c],
19 #[doc = "0x70 - no description available"]
20 pub flexspi0_region1_4_rule3: FLEXSPI0_REGION1_4_RULE,
21 _reserved6: [u8; 0x1c],
22 #[doc = "0x90..0xa0 - SRAM Partition 00 Rule(n) Register"]
23 pub ram00_rule: [RAM00_RULE; 4],
24 #[doc = "0xa0..0xb0 - SRAM Partition 01 Rule(n) Register"]
25 pub ram01_rule: [RAM01_RULE; 4],
26 _reserved8: [u8; 0x10],
27 #[doc = "0xc0..0xd0 - SRAM Partition 02 Rule(n) Register"]
28 pub ram02_rule: [RAM02_RULE; 4],
29 #[doc = "0xd0..0xe0 - SRAM Partition 03 Rule(n) Register"]
30 pub ram03_rule: [RAM03_RULE; 4],
31 _reserved10: [u8; 0x10],
32 #[doc = "0xf0..0x100 - SRAM Partition 04 Rule(n) Register"]
33 pub ram04_rule: [RAM04_RULE; 4],
34 #[doc = "0x100..0x110 - SRAM Partition 05 Rule(n) Register"]
35 pub ram05_rule: [RAM05_RULE; 4],
36 #[doc = "0x110..0x120 - SRAM Partition 06 Rule(n) Register"]
37 pub ram06_rule: [RAM06_RULE; 4],
38 #[doc = "0x120..0x130 - SRAM Partition 07 Rule(n) Register"]
39 pub ram07_rule: [RAM07_RULE; 4],
40 _reserved14: [u8; 0x10],
41 #[doc = "0x140..0x150 - SRAM Partition 08 Rule(n) Register"]
42 pub ram08_rule: [RAM08_RULE; 4],
43 #[doc = "0x150..0x160 - SRAM Partition 09 Rule(n) Register"]
44 pub ram09_rule: [RAM09_RULE; 4],
45 #[doc = "0x160..0x170 - SRAM Partition 10 Rule(n) Register"]
46 pub ram10_rule: [RAM10_RULE; 4],
47 #[doc = "0x170..0x180 - SRAM Partition 11 Rule(n) Register"]
48 pub ram11_rule: [RAM11_RULE; 4],
49 _reserved18: [u8; 0x10],
50 #[doc = "0x190..0x1a0 - SRAM Partition 12 Rule(n) Register"]
51 pub ram12_rule: [RAM12_RULE; 4],
52 #[doc = "0x1a0..0x1b0 - SRAM Partition 13 Rule(n) Register"]
53 pub ram13_rule: [RAM13_RULE; 4],
54 #[doc = "0x1b0..0x1c0 - SRAM Partition 14 Rule(n) Register"]
55 pub ram14_rule: [RAM14_RULE; 4],
56 #[doc = "0x1c0..0x1d0 - SRAM Partition 15 Rule(n) Register"]
57 pub ram15_rule: [RAM15_RULE; 4],
58 _reserved22: [u8; 0x10],
59 #[doc = "0x1e0..0x1f0 - SRAM Partition 16 Rule(n) Register"]
60 pub ram16_rule: [RAM16_RULE; 4],
61 #[doc = "0x1f0..0x200 - SRAM Partition 17 Rule(n) Register"]
62 pub ram17_rule: [RAM17_RULE; 4],
63 #[doc = "0x200..0x210 - SRAM Partition 18 Rule(n) Register"]
64 pub ram18_rule: [RAM18_RULE; 4],
65 #[doc = "0x210..0x220 - SRAM Partition 19 Rule(n) Register"]
66 pub ram19_rule: [RAM19_RULE; 4],
67 _reserved26: [u8; 0x10],
68 #[doc = "0x230..0x240 - SRAM Partition 20 Rule(n) Register"]
69 pub ram20_rule: [RAM20_RULE; 4],
70 #[doc = "0x240..0x250 - SRAM Partition 21 Rule(n) Register"]
71 pub ram21_rule: [RAM21_RULE; 4],
72 #[doc = "0x250..0x260 - SRAM Partition 22 Rule(n) Register"]
73 pub ram22_rule: [RAM22_RULE; 4],
74 #[doc = "0x260..0x270 - SRAM Partition 23 Rule(n) Register"]
75 pub ram23_rule: [RAM23_RULE; 4],
76 _reserved30: [u8; 0x10],
77 #[doc = "0x280..0x290 - SRAM Partition 24 Rule(n) Register"]
78 pub ram24_rule: [RAM24_RULE; 4],
79 #[doc = "0x290..0x2a0 - SRAM Partition 25 Rule(n) Register"]
80 pub ram25_rule: [RAM25_RULE; 4],
81 #[doc = "0x2a0..0x2b0 - SRAM Partition 26 Rule(n) Register"]
82 pub ram26_rule: [RAM26_RULE; 4],
83 #[doc = "0x2b0..0x2c0 - SRAM Partition 27 Rule(n) Register"]
84 pub ram27_rule: [RAM27_RULE; 4],
85 _reserved34: [u8; 0x10],
86 #[doc = "0x2d0..0x2e0 - SRAM Partition 28 Rule(n) Register"]
87 pub ram28_rule: [RAM28_RULE; 4],
88 #[doc = "0x2e0..0x2f0 - SRAM Partition 29 Rule(n) Register"]
89 pub ram29_rule: [RAM29_RULE; 4],
90 #[doc = "0x2f0..0x300 - SRAM Partition 30 Rule(n) Register"]
91 pub ram30_rule: [RAM30_RULE; 4],
92 #[doc = "0x300..0x310 - SRAM Partition 31 Rule(n) Register"]
93 pub ram31_rule: [RAM31_RULE; 4],
94 _reserved38: [u8; 0x10],
95 #[doc = "0x320..0x330 - Smart DMA (SDMA) RAM Rule(n) Register"]
96 pub sdma_ram_rule: [SDMA_RAM_RULE; 4],
97 _reserved39: [u8; 0x10],
98 #[doc = "0x340..0x350 - FlexSPI1 Region 0 Rule(n) Register"]
99 pub flexspi1_region0_rule: [FLEXSPI1_REGION0_RULE; 4],
100 #[doc = "0x350 - no description available"]
101 pub flexspi1_regionn_rule00: FLEXSPI1_REGIONN_RULE0,
102 _reserved41: [u8; 0x0c],
103 #[doc = "0x360 - no description available"]
104 pub flexspi1_regionn_rule01: FLEXSPI1_REGIONN_RULE0,
105 _reserved42: [u8; 0x0c],
106 #[doc = "0x370 - no description available"]
107 pub flexspi1_regionn_rule02: FLEXSPI1_REGIONN_RULE0,
108 _reserved43: [u8; 0x0c],
109 #[doc = "0x380 - no description available"]
110 pub flexspi1_regionn_rule03: FLEXSPI1_REGIONN_RULE0,
111 _reserved44: [u8; 0x1c],
112 #[doc = "0x3a0 - APB Bridge Peripheral 0 Rule 0 Register"]
113 pub apb_bridge_per0_rule0: APB_BRIDGE_PER0_RULE0,
114 #[doc = "0x3a4 - APB Bridge Peripheral 0 Rule 1 Register"]
115 pub apb_bridge_per0_rule1: APB_BRIDGE_PER0_RULE1,
116 _reserved46: [u8; 0x04],
117 #[doc = "0x3ac - APB Bridge Peripheral 0 Rule 3 Register"]
118 pub apb_bridge_per0_rule3: APB_BRIDGE_PER0_RULE3,
119 #[doc = "0x3b0 - APB Bridge Peripheral 1 Rule 0 Register"]
120 pub apb_bridge_per1_rule0: APB_BRIDGE_PER1_RULE0,
121 #[doc = "0x3b4 - APB Bridge Peripheral 1 Rule 1 Register"]
122 pub apb_bridge_per1_rule1: APB_BRIDGE_PER1_RULE1,
123 #[doc = "0x3b8 - APB Bridge Peripheral 1 Rule 2 Register"]
124 pub apb_bridge_per1_rule2: APB_BRIDGE_PER1_RULE2,
125 #[doc = "0x3bc - APB Bridge Peripheral 1 Rule 3 Register"]
126 pub apb_bridge_per1_rule3: APB_BRIDGE_PER1_RULE3,
127 #[doc = "0x3c0 - AHB Peripheral 0 Slave Rule 0 Register"]
128 pub ahb_periph0_slave_rule0: AHB_PERIPH0_SLAVE_RULE0,
129 _reserved52: [u8; 0x0c],
130 #[doc = "0x3d0 - AIPS Bridge Peripheral 0 Rule 0 Register"]
131 pub aips_bridge0_per_rule0: AIPS_BRIDGE0_PER_RULE0,
132 _reserved53: [u8; 0x0c],
133 #[doc = "0x3e0 - AHB Peripheral 1 Slave Rule 0 Register"]
134 pub ahb_periph1_slave_rule0: AHB_PERIPH1_SLAVE_RULE0,
135 #[doc = "0x3e4 - AHB Peripheral 1 Slave Rule 1 Register"]
136 pub ahb_periph1_slave_rule1: AHB_PERIPH1_SLAVE_RULE1,
137 _reserved55: [u8; 0x18],
138 #[doc = "0x400 - AIPS Bridge Peripheral 1 Rule 0 Register"]
139 pub aips_bridge1_per_rule0: AIPS_BRIDGE1_PER_RULE0,
140 #[doc = "0x404 - AIPS Bridge Peripheral 1 Rule 1 Register"]
141 pub aips_bridge1_per_rule1: AIPS_BRIDGE1_PER_RULE1,
142 _reserved57: [u8; 0x08],
143 #[doc = "0x410 - AHB Peripheral 2 Slave Rule 0 Register"]
144 pub ahb_periph2_slave_rule0: AHB_PERIPH2_SLAVE_RULE0,
145 _reserved58: [u8; 0x0c],
146 #[doc = "0x420 - AHB Secure Control Peripheral Rule 0 Register"]
147 pub ahb_secure_ctrl_periph_rule0: AHB_SECURE_CTRL_PERIPH_RULE0,
148 _reserved59: [u8; 0x0c],
149 #[doc = "0x430 - AHB Peripheral 3 Slave Rule 0 Register"]
150 pub ahb_periph3_slave_rule0: AHB_PERIPH3_SLAVE_RULE0,
151 #[doc = "0x434 - AHB Peripheral 3 Slave Rule 1 Register"]
152 pub ahb_periph3_slave_rule1: AHB_PERIPH3_SLAVE_RULE1,
153 _reserved61: [u8; 0x09c8],
154 #[doc = "0xe00..0xe48 - Security Violation Address(n) Register"]
155 pub sec_vio_addr: [SEC_VIO_ADDR; 18],
156 _reserved62: [u8; 0x38],
157 #[doc = "0xe80..0xec8 - Security Violation Miscellaneous Information at Address(n) Register"]
158 pub sec_vio_misc_info: [SEC_VIO_MISC_INFO; 18],
159 _reserved63: [u8; 0x38],
160 #[doc = "0xf00 - Security Violation Info Validity for Address(n) Register"]
161 pub sec_vio_info_valid: SEC_VIO_INFO_VALID,
162 _reserved64: [u8; 0x7c],
163 #[doc = "0xf80..0xf8c - GPIO Mask for Port index Register"]
164 pub sec_gpio_mask: [SEC_GPIO_MASK; 3],
165 _reserved65: [u8; 0x14],
166 #[doc = "0xfa0 - Secure Interrupt Mask for DSP Register"]
167 pub dsp_int_mask0: DSP_INT_MASK0,
168 _reserved66: [u8; 0x18],
169 #[doc = "0xfbc - Secure Mask Lock Register"]
170 pub sec_mask_lock: SEC_MASK_LOCK,
171 _reserved67: [u8; 0x10],
172 #[doc = "0xfd0 - Master Secure Level Register"]
173 pub master_sec_level: MASTER_SEC_LEVEL,
174 #[doc = "0xfd4 - Master Secure Level Register"]
175 pub master_sec_anti_pol_reg: MASTER_SEC_ANTI_POL_REG,
176 _reserved69: [u8; 0x14],
177 #[doc = "0xfec - Miscellaneous CPU0 Control Signals Register"]
178 pub cm33_lock_reg: CM33_LOCK_REG,
179 _reserved70: [u8; 0x08],
180 #[doc = "0xff8 - Secure Control Duplicate Register"]
181 pub misc_ctrl_dp_reg: MISC_CTRL_DP_REG,
182 #[doc = "0xffc - Secure Control Register"]
183 pub misc_ctrl_reg: MISC_CTRL_REG,
184}
185#[doc = "ROM_MEM_RULE (rw) register accessor: an alias for `Reg<ROM_MEM_RULE_SPEC>`"]
186pub type ROM_MEM_RULE = crate::Reg<rom_mem_rule::ROM_MEM_RULE_SPEC>;
187#[doc = "Memory ROM Rule(n) Register"]
188pub mod rom_mem_rule;
189#[doc = "FLEXSPI0_REGION0_RULE (rw) register accessor: an alias for `Reg<FLEXSPI0_REGION0_RULE_SPEC>`"]
190pub type FLEXSPI0_REGION0_RULE = crate::Reg<flexspi0_region0_rule::FLEXSPI0_REGION0_RULE_SPEC>;
191#[doc = "FLEXSPI0 Region 0 Rule(n) Register"]
192pub mod flexspi0_region0_rule;
193#[doc = "no description available"]
194pub use self::flexspi0_region1_4_rule::FLEXSPI0_REGION1_4_RULE;
195#[doc = r"Cluster"]
196#[doc = "no description available"]
197pub mod flexspi0_region1_4_rule;
198#[doc = "RAM00_RULE (rw) register accessor: an alias for `Reg<RAM00_RULE_SPEC>`"]
199pub type RAM00_RULE = crate::Reg<ram00_rule::RAM00_RULE_SPEC>;
200#[doc = "SRAM Partition 00 Rule(n) Register"]
201pub mod ram00_rule;
202#[doc = "RAM01_RULE (rw) register accessor: an alias for `Reg<RAM01_RULE_SPEC>`"]
203pub type RAM01_RULE = crate::Reg<ram01_rule::RAM01_RULE_SPEC>;
204#[doc = "SRAM Partition 01 Rule(n) Register"]
205pub mod ram01_rule;
206#[doc = "RAM02_RULE (rw) register accessor: an alias for `Reg<RAM02_RULE_SPEC>`"]
207pub type RAM02_RULE = crate::Reg<ram02_rule::RAM02_RULE_SPEC>;
208#[doc = "SRAM Partition 02 Rule(n) Register"]
209pub mod ram02_rule;
210#[doc = "RAM03_RULE (rw) register accessor: an alias for `Reg<RAM03_RULE_SPEC>`"]
211pub type RAM03_RULE = crate::Reg<ram03_rule::RAM03_RULE_SPEC>;
212#[doc = "SRAM Partition 03 Rule(n) Register"]
213pub mod ram03_rule;
214#[doc = "RAM04_RULE (rw) register accessor: an alias for `Reg<RAM04_RULE_SPEC>`"]
215pub type RAM04_RULE = crate::Reg<ram04_rule::RAM04_RULE_SPEC>;
216#[doc = "SRAM Partition 04 Rule(n) Register"]
217pub mod ram04_rule;
218#[doc = "RAM05_RULE (rw) register accessor: an alias for `Reg<RAM05_RULE_SPEC>`"]
219pub type RAM05_RULE = crate::Reg<ram05_rule::RAM05_RULE_SPEC>;
220#[doc = "SRAM Partition 05 Rule(n) Register"]
221pub mod ram05_rule;
222#[doc = "RAM06_RULE (rw) register accessor: an alias for `Reg<RAM06_RULE_SPEC>`"]
223pub type RAM06_RULE = crate::Reg<ram06_rule::RAM06_RULE_SPEC>;
224#[doc = "SRAM Partition 06 Rule(n) Register"]
225pub mod ram06_rule;
226#[doc = "RAM07_RULE (rw) register accessor: an alias for `Reg<RAM07_RULE_SPEC>`"]
227pub type RAM07_RULE = crate::Reg<ram07_rule::RAM07_RULE_SPEC>;
228#[doc = "SRAM Partition 07 Rule(n) Register"]
229pub mod ram07_rule;
230#[doc = "RAM08_RULE (rw) register accessor: an alias for `Reg<RAM08_RULE_SPEC>`"]
231pub type RAM08_RULE = crate::Reg<ram08_rule::RAM08_RULE_SPEC>;
232#[doc = "SRAM Partition 08 Rule(n) Register"]
233pub mod ram08_rule;
234#[doc = "RAM09_RULE (rw) register accessor: an alias for `Reg<RAM09_RULE_SPEC>`"]
235pub type RAM09_RULE = crate::Reg<ram09_rule::RAM09_RULE_SPEC>;
236#[doc = "SRAM Partition 09 Rule(n) Register"]
237pub mod ram09_rule;
238#[doc = "RAM10_RULE (rw) register accessor: an alias for `Reg<RAM10_RULE_SPEC>`"]
239pub type RAM10_RULE = crate::Reg<ram10_rule::RAM10_RULE_SPEC>;
240#[doc = "SRAM Partition 10 Rule(n) Register"]
241pub mod ram10_rule;
242#[doc = "RAM11_RULE (rw) register accessor: an alias for `Reg<RAM11_RULE_SPEC>`"]
243pub type RAM11_RULE = crate::Reg<ram11_rule::RAM11_RULE_SPEC>;
244#[doc = "SRAM Partition 11 Rule(n) Register"]
245pub mod ram11_rule;
246#[doc = "RAM12_RULE (rw) register accessor: an alias for `Reg<RAM12_RULE_SPEC>`"]
247pub type RAM12_RULE = crate::Reg<ram12_rule::RAM12_RULE_SPEC>;
248#[doc = "SRAM Partition 12 Rule(n) Register"]
249pub mod ram12_rule;
250#[doc = "RAM13_RULE (rw) register accessor: an alias for `Reg<RAM13_RULE_SPEC>`"]
251pub type RAM13_RULE = crate::Reg<ram13_rule::RAM13_RULE_SPEC>;
252#[doc = "SRAM Partition 13 Rule(n) Register"]
253pub mod ram13_rule;
254#[doc = "RAM14_RULE (rw) register accessor: an alias for `Reg<RAM14_RULE_SPEC>`"]
255pub type RAM14_RULE = crate::Reg<ram14_rule::RAM14_RULE_SPEC>;
256#[doc = "SRAM Partition 14 Rule(n) Register"]
257pub mod ram14_rule;
258#[doc = "RAM15_RULE (rw) register accessor: an alias for `Reg<RAM15_RULE_SPEC>`"]
259pub type RAM15_RULE = crate::Reg<ram15_rule::RAM15_RULE_SPEC>;
260#[doc = "SRAM Partition 15 Rule(n) Register"]
261pub mod ram15_rule;
262#[doc = "RAM16_RULE (rw) register accessor: an alias for `Reg<RAM16_RULE_SPEC>`"]
263pub type RAM16_RULE = crate::Reg<ram16_rule::RAM16_RULE_SPEC>;
264#[doc = "SRAM Partition 16 Rule(n) Register"]
265pub mod ram16_rule;
266#[doc = "RAM17_RULE (rw) register accessor: an alias for `Reg<RAM17_RULE_SPEC>`"]
267pub type RAM17_RULE = crate::Reg<ram17_rule::RAM17_RULE_SPEC>;
268#[doc = "SRAM Partition 17 Rule(n) Register"]
269pub mod ram17_rule;
270#[doc = "RAM18_RULE (rw) register accessor: an alias for `Reg<RAM18_RULE_SPEC>`"]
271pub type RAM18_RULE = crate::Reg<ram18_rule::RAM18_RULE_SPEC>;
272#[doc = "SRAM Partition 18 Rule(n) Register"]
273pub mod ram18_rule;
274#[doc = "RAM19_RULE (rw) register accessor: an alias for `Reg<RAM19_RULE_SPEC>`"]
275pub type RAM19_RULE = crate::Reg<ram19_rule::RAM19_RULE_SPEC>;
276#[doc = "SRAM Partition 19 Rule(n) Register"]
277pub mod ram19_rule;
278#[doc = "RAM20_RULE (rw) register accessor: an alias for `Reg<RAM20_RULE_SPEC>`"]
279pub type RAM20_RULE = crate::Reg<ram20_rule::RAM20_RULE_SPEC>;
280#[doc = "SRAM Partition 20 Rule(n) Register"]
281pub mod ram20_rule;
282#[doc = "RAM21_RULE (rw) register accessor: an alias for `Reg<RAM21_RULE_SPEC>`"]
283pub type RAM21_RULE = crate::Reg<ram21_rule::RAM21_RULE_SPEC>;
284#[doc = "SRAM Partition 21 Rule(n) Register"]
285pub mod ram21_rule;
286#[doc = "RAM22_RULE (rw) register accessor: an alias for `Reg<RAM22_RULE_SPEC>`"]
287pub type RAM22_RULE = crate::Reg<ram22_rule::RAM22_RULE_SPEC>;
288#[doc = "SRAM Partition 22 Rule(n) Register"]
289pub mod ram22_rule;
290#[doc = "RAM23_RULE (rw) register accessor: an alias for `Reg<RAM23_RULE_SPEC>`"]
291pub type RAM23_RULE = crate::Reg<ram23_rule::RAM23_RULE_SPEC>;
292#[doc = "SRAM Partition 23 Rule(n) Register"]
293pub mod ram23_rule;
294#[doc = "RAM24_RULE (rw) register accessor: an alias for `Reg<RAM24_RULE_SPEC>`"]
295pub type RAM24_RULE = crate::Reg<ram24_rule::RAM24_RULE_SPEC>;
296#[doc = "SRAM Partition 24 Rule(n) Register"]
297pub mod ram24_rule;
298#[doc = "RAM25_RULE (rw) register accessor: an alias for `Reg<RAM25_RULE_SPEC>`"]
299pub type RAM25_RULE = crate::Reg<ram25_rule::RAM25_RULE_SPEC>;
300#[doc = "SRAM Partition 25 Rule(n) Register"]
301pub mod ram25_rule;
302#[doc = "RAM26_RULE (rw) register accessor: an alias for `Reg<RAM26_RULE_SPEC>`"]
303pub type RAM26_RULE = crate::Reg<ram26_rule::RAM26_RULE_SPEC>;
304#[doc = "SRAM Partition 26 Rule(n) Register"]
305pub mod ram26_rule;
306#[doc = "RAM27_RULE (rw) register accessor: an alias for `Reg<RAM27_RULE_SPEC>`"]
307pub type RAM27_RULE = crate::Reg<ram27_rule::RAM27_RULE_SPEC>;
308#[doc = "SRAM Partition 27 Rule(n) Register"]
309pub mod ram27_rule;
310#[doc = "RAM28_RULE (rw) register accessor: an alias for `Reg<RAM28_RULE_SPEC>`"]
311pub type RAM28_RULE = crate::Reg<ram28_rule::RAM28_RULE_SPEC>;
312#[doc = "SRAM Partition 28 Rule(n) Register"]
313pub mod ram28_rule;
314#[doc = "RAM29_RULE (rw) register accessor: an alias for `Reg<RAM29_RULE_SPEC>`"]
315pub type RAM29_RULE = crate::Reg<ram29_rule::RAM29_RULE_SPEC>;
316#[doc = "SRAM Partition 29 Rule(n) Register"]
317pub mod ram29_rule;
318#[doc = "RAM30_RULE (rw) register accessor: an alias for `Reg<RAM30_RULE_SPEC>`"]
319pub type RAM30_RULE = crate::Reg<ram30_rule::RAM30_RULE_SPEC>;
320#[doc = "SRAM Partition 30 Rule(n) Register"]
321pub mod ram30_rule;
322#[doc = "RAM31_RULE (rw) register accessor: an alias for `Reg<RAM31_RULE_SPEC>`"]
323pub type RAM31_RULE = crate::Reg<ram31_rule::RAM31_RULE_SPEC>;
324#[doc = "SRAM Partition 31 Rule(n) Register"]
325pub mod ram31_rule;
326#[doc = "SDMA_RAM_RULE (rw) register accessor: an alias for `Reg<SDMA_RAM_RULE_SPEC>`"]
327pub type SDMA_RAM_RULE = crate::Reg<sdma_ram_rule::SDMA_RAM_RULE_SPEC>;
328#[doc = "Smart DMA (SDMA) RAM Rule(n) Register"]
329pub mod sdma_ram_rule;
330#[doc = "FLEXSPI1_REGION0_RULE (rw) register accessor: an alias for `Reg<FLEXSPI1_REGION0_RULE_SPEC>`"]
331pub type FLEXSPI1_REGION0_RULE = crate::Reg<flexspi1_region0_rule::FLEXSPI1_REGION0_RULE_SPEC>;
332#[doc = "FlexSPI1 Region 0 Rule(n) Register"]
333pub mod flexspi1_region0_rule;
334#[doc = "no description available"]
335pub use self::flexspi1_regionn_rule0::FLEXSPI1_REGIONN_RULE0;
336#[doc = r"Cluster"]
337#[doc = "no description available"]
338pub mod flexspi1_regionn_rule0;
339#[doc = "APB_BRIDGE_PER0_RULE0 (rw) register accessor: an alias for `Reg<APB_BRIDGE_PER0_RULE0_SPEC>`"]
340pub type APB_BRIDGE_PER0_RULE0 = crate::Reg<apb_bridge_per0_rule0::APB_BRIDGE_PER0_RULE0_SPEC>;
341#[doc = "APB Bridge Peripheral 0 Rule 0 Register"]
342pub mod apb_bridge_per0_rule0;
343#[doc = "APB_BRIDGE_PER0_RULE1 (rw) register accessor: an alias for `Reg<APB_BRIDGE_PER0_RULE1_SPEC>`"]
344pub type APB_BRIDGE_PER0_RULE1 = crate::Reg<apb_bridge_per0_rule1::APB_BRIDGE_PER0_RULE1_SPEC>;
345#[doc = "APB Bridge Peripheral 0 Rule 1 Register"]
346pub mod apb_bridge_per0_rule1;
347#[doc = "APB_BRIDGE_PER0_RULE3 (rw) register accessor: an alias for `Reg<APB_BRIDGE_PER0_RULE3_SPEC>`"]
348pub type APB_BRIDGE_PER0_RULE3 = crate::Reg<apb_bridge_per0_rule3::APB_BRIDGE_PER0_RULE3_SPEC>;
349#[doc = "APB Bridge Peripheral 0 Rule 3 Register"]
350pub mod apb_bridge_per0_rule3;
351#[doc = "APB_BRIDGE_PER1_RULE0 (rw) register accessor: an alias for `Reg<APB_BRIDGE_PER1_RULE0_SPEC>`"]
352pub type APB_BRIDGE_PER1_RULE0 = crate::Reg<apb_bridge_per1_rule0::APB_BRIDGE_PER1_RULE0_SPEC>;
353#[doc = "APB Bridge Peripheral 1 Rule 0 Register"]
354pub mod apb_bridge_per1_rule0;
355#[doc = "APB_BRIDGE_PER1_RULE1 (rw) register accessor: an alias for `Reg<APB_BRIDGE_PER1_RULE1_SPEC>`"]
356pub type APB_BRIDGE_PER1_RULE1 = crate::Reg<apb_bridge_per1_rule1::APB_BRIDGE_PER1_RULE1_SPEC>;
357#[doc = "APB Bridge Peripheral 1 Rule 1 Register"]
358pub mod apb_bridge_per1_rule1;
359#[doc = "APB_BRIDGE_PER1_RULE2 (rw) register accessor: an alias for `Reg<APB_BRIDGE_PER1_RULE2_SPEC>`"]
360pub type APB_BRIDGE_PER1_RULE2 = crate::Reg<apb_bridge_per1_rule2::APB_BRIDGE_PER1_RULE2_SPEC>;
361#[doc = "APB Bridge Peripheral 1 Rule 2 Register"]
362pub mod apb_bridge_per1_rule2;
363#[doc = "APB_BRIDGE_PER1_RULE3 (rw) register accessor: an alias for `Reg<APB_BRIDGE_PER1_RULE3_SPEC>`"]
364pub type APB_BRIDGE_PER1_RULE3 = crate::Reg<apb_bridge_per1_rule3::APB_BRIDGE_PER1_RULE3_SPEC>;
365#[doc = "APB Bridge Peripheral 1 Rule 3 Register"]
366pub mod apb_bridge_per1_rule3;
367#[doc = "AHB_PERIPH0_SLAVE_RULE0 (rw) register accessor: an alias for `Reg<AHB_PERIPH0_SLAVE_RULE0_SPEC>`"]
368pub type AHB_PERIPH0_SLAVE_RULE0 =
369 crate::Reg<ahb_periph0_slave_rule0::AHB_PERIPH0_SLAVE_RULE0_SPEC>;
370#[doc = "AHB Peripheral 0 Slave Rule 0 Register"]
371pub mod ahb_periph0_slave_rule0;
372#[doc = "AIPS_BRIDGE0_PER_RULE0 (rw) register accessor: an alias for `Reg<AIPS_BRIDGE0_PER_RULE0_SPEC>`"]
373pub type AIPS_BRIDGE0_PER_RULE0 = crate::Reg<aips_bridge0_per_rule0::AIPS_BRIDGE0_PER_RULE0_SPEC>;
374#[doc = "AIPS Bridge Peripheral 0 Rule 0 Register"]
375pub mod aips_bridge0_per_rule0;
376#[doc = "AHB_PERIPH1_SLAVE_RULE0 (rw) register accessor: an alias for `Reg<AHB_PERIPH1_SLAVE_RULE0_SPEC>`"]
377pub type AHB_PERIPH1_SLAVE_RULE0 =
378 crate::Reg<ahb_periph1_slave_rule0::AHB_PERIPH1_SLAVE_RULE0_SPEC>;
379#[doc = "AHB Peripheral 1 Slave Rule 0 Register"]
380pub mod ahb_periph1_slave_rule0;
381#[doc = "AHB_PERIPH1_SLAVE_RULE1 (rw) register accessor: an alias for `Reg<AHB_PERIPH1_SLAVE_RULE1_SPEC>`"]
382pub type AHB_PERIPH1_SLAVE_RULE1 =
383 crate::Reg<ahb_periph1_slave_rule1::AHB_PERIPH1_SLAVE_RULE1_SPEC>;
384#[doc = "AHB Peripheral 1 Slave Rule 1 Register"]
385pub mod ahb_periph1_slave_rule1;
386#[doc = "AIPS_BRIDGE1_PER_RULE0 (rw) register accessor: an alias for `Reg<AIPS_BRIDGE1_PER_RULE0_SPEC>`"]
387pub type AIPS_BRIDGE1_PER_RULE0 = crate::Reg<aips_bridge1_per_rule0::AIPS_BRIDGE1_PER_RULE0_SPEC>;
388#[doc = "AIPS Bridge Peripheral 1 Rule 0 Register"]
389pub mod aips_bridge1_per_rule0;
390#[doc = "AIPS_BRIDGE1_PER_RULE1 (rw) register accessor: an alias for `Reg<AIPS_BRIDGE1_PER_RULE1_SPEC>`"]
391pub type AIPS_BRIDGE1_PER_RULE1 = crate::Reg<aips_bridge1_per_rule1::AIPS_BRIDGE1_PER_RULE1_SPEC>;
392#[doc = "AIPS Bridge Peripheral 1 Rule 1 Register"]
393pub mod aips_bridge1_per_rule1;
394#[doc = "AHB_PERIPH2_SLAVE_RULE0 (rw) register accessor: an alias for `Reg<AHB_PERIPH2_SLAVE_RULE0_SPEC>`"]
395pub type AHB_PERIPH2_SLAVE_RULE0 =
396 crate::Reg<ahb_periph2_slave_rule0::AHB_PERIPH2_SLAVE_RULE0_SPEC>;
397#[doc = "AHB Peripheral 2 Slave Rule 0 Register"]
398pub mod ahb_periph2_slave_rule0;
399#[doc = "AHB_SECURE_CTRL_PERIPH_RULE0 (rw) register accessor: an alias for `Reg<AHB_SECURE_CTRL_PERIPH_RULE0_SPEC>`"]
400pub type AHB_SECURE_CTRL_PERIPH_RULE0 =
401 crate::Reg<ahb_secure_ctrl_periph_rule0::AHB_SECURE_CTRL_PERIPH_RULE0_SPEC>;
402#[doc = "AHB Secure Control Peripheral Rule 0 Register"]
403pub mod ahb_secure_ctrl_periph_rule0;
404#[doc = "AHB_PERIPH3_SLAVE_RULE0 (rw) register accessor: an alias for `Reg<AHB_PERIPH3_SLAVE_RULE0_SPEC>`"]
405pub type AHB_PERIPH3_SLAVE_RULE0 =
406 crate::Reg<ahb_periph3_slave_rule0::AHB_PERIPH3_SLAVE_RULE0_SPEC>;
407#[doc = "AHB Peripheral 3 Slave Rule 0 Register"]
408pub mod ahb_periph3_slave_rule0;
409#[doc = "AHB_PERIPH3_SLAVE_RULE1 (rw) register accessor: an alias for `Reg<AHB_PERIPH3_SLAVE_RULE1_SPEC>`"]
410pub type AHB_PERIPH3_SLAVE_RULE1 =
411 crate::Reg<ahb_periph3_slave_rule1::AHB_PERIPH3_SLAVE_RULE1_SPEC>;
412#[doc = "AHB Peripheral 3 Slave Rule 1 Register"]
413pub mod ahb_periph3_slave_rule1;
414#[doc = "SEC_VIO_ADDR (r) register accessor: an alias for `Reg<SEC_VIO_ADDR_SPEC>`"]
415pub type SEC_VIO_ADDR = crate::Reg<sec_vio_addr::SEC_VIO_ADDR_SPEC>;
416#[doc = "Security Violation Address(n) Register"]
417pub mod sec_vio_addr;
418#[doc = "SEC_VIO_MISC_INFO (r) register accessor: an alias for `Reg<SEC_VIO_MISC_INFO_SPEC>`"]
419pub type SEC_VIO_MISC_INFO = crate::Reg<sec_vio_misc_info::SEC_VIO_MISC_INFO_SPEC>;
420#[doc = "Security Violation Miscellaneous Information at Address(n) Register"]
421pub mod sec_vio_misc_info;
422#[doc = "SEC_VIO_INFO_VALID (rw) register accessor: an alias for `Reg<SEC_VIO_INFO_VALID_SPEC>`"]
423pub type SEC_VIO_INFO_VALID = crate::Reg<sec_vio_info_valid::SEC_VIO_INFO_VALID_SPEC>;
424#[doc = "Security Violation Info Validity for Address(n) Register"]
425pub mod sec_vio_info_valid;
426#[doc = "SEC_GPIO_MASK (rw) register accessor: an alias for `Reg<SEC_GPIO_MASK_SPEC>`"]
427pub type SEC_GPIO_MASK = crate::Reg<sec_gpio_mask::SEC_GPIO_MASK_SPEC>;
428#[doc = "GPIO Mask for Port index Register"]
429pub mod sec_gpio_mask;
430#[doc = "DSP_INT_MASK0 (rw) register accessor: an alias for `Reg<DSP_INT_MASK0_SPEC>`"]
431pub type DSP_INT_MASK0 = crate::Reg<dsp_int_mask0::DSP_INT_MASK0_SPEC>;
432#[doc = "Secure Interrupt Mask for DSP Register"]
433pub mod dsp_int_mask0;
434#[doc = "SEC_MASK_LOCK (rw) register accessor: an alias for `Reg<SEC_MASK_LOCK_SPEC>`"]
435pub type SEC_MASK_LOCK = crate::Reg<sec_mask_lock::SEC_MASK_LOCK_SPEC>;
436#[doc = "Secure Mask Lock Register"]
437pub mod sec_mask_lock;
438#[doc = "MASTER_SEC_LEVEL (rw) register accessor: an alias for `Reg<MASTER_SEC_LEVEL_SPEC>`"]
439pub type MASTER_SEC_LEVEL = crate::Reg<master_sec_level::MASTER_SEC_LEVEL_SPEC>;
440#[doc = "Master Secure Level Register"]
441pub mod master_sec_level;
442#[doc = "MASTER_SEC_ANTI_POL_REG (rw) register accessor: an alias for `Reg<MASTER_SEC_ANTI_POL_REG_SPEC>`"]
443pub type MASTER_SEC_ANTI_POL_REG =
444 crate::Reg<master_sec_anti_pol_reg::MASTER_SEC_ANTI_POL_REG_SPEC>;
445#[doc = "Master Secure Level Register"]
446pub mod master_sec_anti_pol_reg;
447#[doc = "CM33_LOCK_REG (rw) register accessor: an alias for `Reg<CM33_LOCK_REG_SPEC>`"]
448pub type CM33_LOCK_REG = crate::Reg<cm33_lock_reg::CM33_LOCK_REG_SPEC>;
449#[doc = "Miscellaneous CPU0 Control Signals Register"]
450pub mod cm33_lock_reg;
451#[doc = "MISC_CTRL_DP_REG (rw) register accessor: an alias for `Reg<MISC_CTRL_DP_REG_SPEC>`"]
452pub type MISC_CTRL_DP_REG = crate::Reg<misc_ctrl_dp_reg::MISC_CTRL_DP_REG_SPEC>;
453#[doc = "Secure Control Duplicate Register"]
454pub mod misc_ctrl_dp_reg;
455#[doc = "MISC_CTRL_REG (rw) register accessor: an alias for `Reg<MISC_CTRL_REG_SPEC>`"]
456pub type MISC_CTRL_REG = crate::Reg<misc_ctrl_reg::MISC_CTRL_REG_SPEC>;
457#[doc = "Secure Control Register"]
458pub mod misc_ctrl_reg;