mimxrt595s/inputmux/
dmac1_chmux_sel7.rs

1#[doc = "Register `DMAC1_CHMUX_SEL7` reader"]
2pub struct R(crate::R<DMAC1_CHMUX_SEL7_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DMAC1_CHMUX_SEL7_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DMAC1_CHMUX_SEL7_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DMAC1_CHMUX_SEL7_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DMAC1_CHMUX_SEL7` writer"]
17pub struct W(crate::W<DMAC1_CHMUX_SEL7_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DMAC1_CHMUX_SEL7_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DMAC1_CHMUX_SEL7_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DMAC1_CHMUX_SEL7_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DMAC1_CHMUX_SEL` reader - DMAC1 Channel mux select"]
38pub type DMAC1_CHMUX_SEL_R = crate::BitReader<DMAC1_CHMUX_SEL_A>;
39#[doc = "DMAC1 Channel mux select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum DMAC1_CHMUX_SEL_A {
42    #[doc = "0: DMIC_CH7_DMA"]
43    DMAC1_CHMUX_SEL_0 = 0,
44    #[doc = "1: FLEXCOM13_TX_DMA"]
45    DMAC1_CHMUX_SEL_1 = 1,
46}
47impl From<DMAC1_CHMUX_SEL_A> for bool {
48    #[inline(always)]
49    fn from(variant: DMAC1_CHMUX_SEL_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl DMAC1_CHMUX_SEL_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> DMAC1_CHMUX_SEL_A {
57        match self.bits {
58            false => DMAC1_CHMUX_SEL_A::DMAC1_CHMUX_SEL_0,
59            true => DMAC1_CHMUX_SEL_A::DMAC1_CHMUX_SEL_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `DMAC1_CHMUX_SEL_0`"]
63    #[inline(always)]
64    pub fn is_dmac1_chmux_sel_0(&self) -> bool {
65        *self == DMAC1_CHMUX_SEL_A::DMAC1_CHMUX_SEL_0
66    }
67    #[doc = "Checks if the value of the field is `DMAC1_CHMUX_SEL_1`"]
68    #[inline(always)]
69    pub fn is_dmac1_chmux_sel_1(&self) -> bool {
70        *self == DMAC1_CHMUX_SEL_A::DMAC1_CHMUX_SEL_1
71    }
72}
73#[doc = "Field `DMAC1_CHMUX_SEL` writer - DMAC1 Channel mux select"]
74pub type DMAC1_CHMUX_SEL_W<'a, const O: u8> =
75    crate::BitWriter<'a, u32, DMAC1_CHMUX_SEL7_SPEC, DMAC1_CHMUX_SEL_A, O>;
76impl<'a, const O: u8> DMAC1_CHMUX_SEL_W<'a, O> {
77    #[doc = "DMIC_CH7_DMA"]
78    #[inline(always)]
79    pub fn dmac1_chmux_sel_0(self) -> &'a mut W {
80        self.variant(DMAC1_CHMUX_SEL_A::DMAC1_CHMUX_SEL_0)
81    }
82    #[doc = "FLEXCOM13_TX_DMA"]
83    #[inline(always)]
84    pub fn dmac1_chmux_sel_1(self) -> &'a mut W {
85        self.variant(DMAC1_CHMUX_SEL_A::DMAC1_CHMUX_SEL_1)
86    }
87}
88impl R {
89    #[doc = "Bit 0 - DMAC1 Channel mux select"]
90    #[inline(always)]
91    pub fn dmac1_chmux_sel(&self) -> DMAC1_CHMUX_SEL_R {
92        DMAC1_CHMUX_SEL_R::new((self.bits & 1) != 0)
93    }
94}
95impl W {
96    #[doc = "Bit 0 - DMAC1 Channel mux select"]
97    #[inline(always)]
98    #[must_use]
99    pub fn dmac1_chmux_sel(&mut self) -> DMAC1_CHMUX_SEL_W<0> {
100        DMAC1_CHMUX_SEL_W::new(self)
101    }
102    #[doc = "Writes raw bits to the register."]
103    #[inline(always)]
104    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
105        self.0.bits(bits);
106        self
107    }
108}
109#[doc = "DMAC1 Channel mux select 7\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmac1_chmux_sel7](index.html) module"]
110pub struct DMAC1_CHMUX_SEL7_SPEC;
111impl crate::RegisterSpec for DMAC1_CHMUX_SEL7_SPEC {
112    type Ux = u32;
113}
114#[doc = "`read()` method returns [dmac1_chmux_sel7::R](R) reader structure"]
115impl crate::Readable for DMAC1_CHMUX_SEL7_SPEC {
116    type Reader = R;
117}
118#[doc = "`write(|w| ..)` method takes [dmac1_chmux_sel7::W](W) writer structure"]
119impl crate::Writable for DMAC1_CHMUX_SEL7_SPEC {
120    type Writer = W;
121    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
122    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
123}
124#[doc = "`reset()` method sets DMAC1_CHMUX_SEL7 to value 0"]
125impl crate::Resettable for DMAC1_CHMUX_SEL7_SPEC {
126    const RESET_VALUE: Self::Ux = 0;
127}
mimxrt595s/inputmux/dmac1_chmux_sel7.rs

mimxrt595s/inputmux/
dmac1_chmux_sel7.rs
