mimxrt595s/clkctl0/
frodivoen.rs

1#[doc = "Register `FRODIVOEN` reader"]
2pub struct R(crate::R<FRODIVOEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FRODIVOEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FRODIVOEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FRODIVOEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `FRODIVOEN` writer"]
17pub struct W(crate::W<FRODIVOEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FRODIVOEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FRODIVOEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FRODIVOEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `FRO_DIV1_O_EN` reader - FRO Divided-by-1 Clock Enable"]
38pub type FRO_DIV1_O_EN_R = crate::BitReader<FRO_DIV1_O_EN_A>;
39#[doc = "FRO Divided-by-1 Clock Enable\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum FRO_DIV1_O_EN_A {
42    #[doc = "0: Disable clock"]
43    CLK_DISABLE = 0,
44    #[doc = "1: Enable clock"]
45    CLK_ENABLE = 1,
46}
47impl From<FRO_DIV1_O_EN_A> for bool {
48    #[inline(always)]
49    fn from(variant: FRO_DIV1_O_EN_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl FRO_DIV1_O_EN_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> FRO_DIV1_O_EN_A {
57        match self.bits {
58            false => FRO_DIV1_O_EN_A::CLK_DISABLE,
59            true => FRO_DIV1_O_EN_A::CLK_ENABLE,
60        }
61    }
62    #[doc = "Checks if the value of the field is `CLK_DISABLE`"]
63    #[inline(always)]
64    pub fn is_clk_disable(&self) -> bool {
65        *self == FRO_DIV1_O_EN_A::CLK_DISABLE
66    }
67    #[doc = "Checks if the value of the field is `CLK_ENABLE`"]
68    #[inline(always)]
69    pub fn is_clk_enable(&self) -> bool {
70        *self == FRO_DIV1_O_EN_A::CLK_ENABLE
71    }
72}
73#[doc = "Field `FRO_DIV1_O_EN` writer - FRO Divided-by-1 Clock Enable"]
74pub type FRO_DIV1_O_EN_W<'a, const O: u8> =
75    crate::BitWriter<'a, u32, FRODIVOEN_SPEC, FRO_DIV1_O_EN_A, O>;
76impl<'a, const O: u8> FRO_DIV1_O_EN_W<'a, O> {
77    #[doc = "Disable clock"]
78    #[inline(always)]
79    pub fn clk_disable(self) -> &'a mut W {
80        self.variant(FRO_DIV1_O_EN_A::CLK_DISABLE)
81    }
82    #[doc = "Enable clock"]
83    #[inline(always)]
84    pub fn clk_enable(self) -> &'a mut W {
85        self.variant(FRO_DIV1_O_EN_A::CLK_ENABLE)
86    }
87}
88#[doc = "Field `FRO_DIV2_O_EN` reader - FRO Divided-by-2 Clock Enable"]
89pub type FRO_DIV2_O_EN_R = crate::BitReader<FRO_DIV2_O_EN_A>;
90#[doc = "FRO Divided-by-2 Clock Enable\n\nValue on reset: 0"]
91#[derive(Clone, Copy, Debug, PartialEq, Eq)]
92pub enum FRO_DIV2_O_EN_A {
93    #[doc = "0: Disable clock"]
94    CLK_DISABLE = 0,
95    #[doc = "1: Enable clock"]
96    CLK_ENABLE = 1,
97}
98impl From<FRO_DIV2_O_EN_A> for bool {
99    #[inline(always)]
100    fn from(variant: FRO_DIV2_O_EN_A) -> Self {
101        variant as u8 != 0
102    }
103}
104impl FRO_DIV2_O_EN_R {
105    #[doc = "Get enumerated values variant"]
106    #[inline(always)]
107    pub fn variant(&self) -> FRO_DIV2_O_EN_A {
108        match self.bits {
109            false => FRO_DIV2_O_EN_A::CLK_DISABLE,
110            true => FRO_DIV2_O_EN_A::CLK_ENABLE,
111        }
112    }
113    #[doc = "Checks if the value of the field is `CLK_DISABLE`"]
114    #[inline(always)]
115    pub fn is_clk_disable(&self) -> bool {
116        *self == FRO_DIV2_O_EN_A::CLK_DISABLE
117    }
118    #[doc = "Checks if the value of the field is `CLK_ENABLE`"]
119    #[inline(always)]
120    pub fn is_clk_enable(&self) -> bool {
121        *self == FRO_DIV2_O_EN_A::CLK_ENABLE
122    }
123}
124#[doc = "Field `FRO_DIV2_O_EN` writer - FRO Divided-by-2 Clock Enable"]
125pub type FRO_DIV2_O_EN_W<'a, const O: u8> =
126    crate::BitWriter<'a, u32, FRODIVOEN_SPEC, FRO_DIV2_O_EN_A, O>;
127impl<'a, const O: u8> FRO_DIV2_O_EN_W<'a, O> {
128    #[doc = "Disable clock"]
129    #[inline(always)]
130    pub fn clk_disable(self) -> &'a mut W {
131        self.variant(FRO_DIV2_O_EN_A::CLK_DISABLE)
132    }
133    #[doc = "Enable clock"]
134    #[inline(always)]
135    pub fn clk_enable(self) -> &'a mut W {
136        self.variant(FRO_DIV2_O_EN_A::CLK_ENABLE)
137    }
138}
139#[doc = "Field `FRO_DIV4_O_EN` reader - FRO Divided-by-4 Clock Enable"]
140pub type FRO_DIV4_O_EN_R = crate::BitReader<FRO_DIV4_O_EN_A>;
141#[doc = "FRO Divided-by-4 Clock Enable\n\nValue on reset: 0"]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143pub enum FRO_DIV4_O_EN_A {
144    #[doc = "0: Disable clock"]
145    CLK_DISABLE = 0,
146    #[doc = "1: Enable clock"]
147    CLK_ENABLE = 1,
148}
149impl From<FRO_DIV4_O_EN_A> for bool {
150    #[inline(always)]
151    fn from(variant: FRO_DIV4_O_EN_A) -> Self {
152        variant as u8 != 0
153    }
154}
155impl FRO_DIV4_O_EN_R {
156    #[doc = "Get enumerated values variant"]
157    #[inline(always)]
158    pub fn variant(&self) -> FRO_DIV4_O_EN_A {
159        match self.bits {
160            false => FRO_DIV4_O_EN_A::CLK_DISABLE,
161            true => FRO_DIV4_O_EN_A::CLK_ENABLE,
162        }
163    }
164    #[doc = "Checks if the value of the field is `CLK_DISABLE`"]
165    #[inline(always)]
166    pub fn is_clk_disable(&self) -> bool {
167        *self == FRO_DIV4_O_EN_A::CLK_DISABLE
168    }
169    #[doc = "Checks if the value of the field is `CLK_ENABLE`"]
170    #[inline(always)]
171    pub fn is_clk_enable(&self) -> bool {
172        *self == FRO_DIV4_O_EN_A::CLK_ENABLE
173    }
174}
175#[doc = "Field `FRO_DIV4_O_EN` writer - FRO Divided-by-4 Clock Enable"]
176pub type FRO_DIV4_O_EN_W<'a, const O: u8> =
177    crate::BitWriter<'a, u32, FRODIVOEN_SPEC, FRO_DIV4_O_EN_A, O>;
178impl<'a, const O: u8> FRO_DIV4_O_EN_W<'a, O> {
179    #[doc = "Disable clock"]
180    #[inline(always)]
181    pub fn clk_disable(self) -> &'a mut W {
182        self.variant(FRO_DIV4_O_EN_A::CLK_DISABLE)
183    }
184    #[doc = "Enable clock"]
185    #[inline(always)]
186    pub fn clk_enable(self) -> &'a mut W {
187        self.variant(FRO_DIV4_O_EN_A::CLK_ENABLE)
188    }
189}
190#[doc = "Field `FRO_DIV8_O_EN` reader - FRO Divided-by-8 Clock Enable"]
191pub type FRO_DIV8_O_EN_R = crate::BitReader<FRO_DIV8_O_EN_A>;
192#[doc = "FRO Divided-by-8 Clock Enable\n\nValue on reset: 0"]
193#[derive(Clone, Copy, Debug, PartialEq, Eq)]
194pub enum FRO_DIV8_O_EN_A {
195    #[doc = "0: Disable clock"]
196    CLK_DISABLE = 0,
197    #[doc = "1: Enable clock"]
198    CLK_ENABLE = 1,
199}
200impl From<FRO_DIV8_O_EN_A> for bool {
201    #[inline(always)]
202    fn from(variant: FRO_DIV8_O_EN_A) -> Self {
203        variant as u8 != 0
204    }
205}
206impl FRO_DIV8_O_EN_R {
207    #[doc = "Get enumerated values variant"]
208    #[inline(always)]
209    pub fn variant(&self) -> FRO_DIV8_O_EN_A {
210        match self.bits {
211            false => FRO_DIV8_O_EN_A::CLK_DISABLE,
212            true => FRO_DIV8_O_EN_A::CLK_ENABLE,
213        }
214    }
215    #[doc = "Checks if the value of the field is `CLK_DISABLE`"]
216    #[inline(always)]
217    pub fn is_clk_disable(&self) -> bool {
218        *self == FRO_DIV8_O_EN_A::CLK_DISABLE
219    }
220    #[doc = "Checks if the value of the field is `CLK_ENABLE`"]
221    #[inline(always)]
222    pub fn is_clk_enable(&self) -> bool {
223        *self == FRO_DIV8_O_EN_A::CLK_ENABLE
224    }
225}
226#[doc = "Field `FRO_DIV8_O_EN` writer - FRO Divided-by-8 Clock Enable"]
227pub type FRO_DIV8_O_EN_W<'a, const O: u8> =
228    crate::BitWriter<'a, u32, FRODIVOEN_SPEC, FRO_DIV8_O_EN_A, O>;
229impl<'a, const O: u8> FRO_DIV8_O_EN_W<'a, O> {
230    #[doc = "Disable clock"]
231    #[inline(always)]
232    pub fn clk_disable(self) -> &'a mut W {
233        self.variant(FRO_DIV8_O_EN_A::CLK_DISABLE)
234    }
235    #[doc = "Enable clock"]
236    #[inline(always)]
237    pub fn clk_enable(self) -> &'a mut W {
238        self.variant(FRO_DIV8_O_EN_A::CLK_ENABLE)
239    }
240}
241#[doc = "Field `FRO_DIV16_O_EN` reader - FRO Divided-by-16 Clock Enable"]
242pub type FRO_DIV16_O_EN_R = crate::BitReader<FRO_DIV16_O_EN_A>;
243#[doc = "FRO Divided-by-16 Clock Enable\n\nValue on reset: 0"]
244#[derive(Clone, Copy, Debug, PartialEq, Eq)]
245pub enum FRO_DIV16_O_EN_A {
246    #[doc = "0: Disable clock"]
247    CLK_DISABLE = 0,
248    #[doc = "1: Enable clock"]
249    CLK_ENABLE = 1,
250}
251impl From<FRO_DIV16_O_EN_A> for bool {
252    #[inline(always)]
253    fn from(variant: FRO_DIV16_O_EN_A) -> Self {
254        variant as u8 != 0
255    }
256}
257impl FRO_DIV16_O_EN_R {
258    #[doc = "Get enumerated values variant"]
259    #[inline(always)]
260    pub fn variant(&self) -> FRO_DIV16_O_EN_A {
261        match self.bits {
262            false => FRO_DIV16_O_EN_A::CLK_DISABLE,
263            true => FRO_DIV16_O_EN_A::CLK_ENABLE,
264        }
265    }
266    #[doc = "Checks if the value of the field is `CLK_DISABLE`"]
267    #[inline(always)]
268    pub fn is_clk_disable(&self) -> bool {
269        *self == FRO_DIV16_O_EN_A::CLK_DISABLE
270    }
271    #[doc = "Checks if the value of the field is `CLK_ENABLE`"]
272    #[inline(always)]
273    pub fn is_clk_enable(&self) -> bool {
274        *self == FRO_DIV16_O_EN_A::CLK_ENABLE
275    }
276}
277#[doc = "Field `FRO_DIV16_O_EN` writer - FRO Divided-by-16 Clock Enable"]
278pub type FRO_DIV16_O_EN_W<'a, const O: u8> =
279    crate::BitWriter<'a, u32, FRODIVOEN_SPEC, FRO_DIV16_O_EN_A, O>;
280impl<'a, const O: u8> FRO_DIV16_O_EN_W<'a, O> {
281    #[doc = "Disable clock"]
282    #[inline(always)]
283    pub fn clk_disable(self) -> &'a mut W {
284        self.variant(FRO_DIV16_O_EN_A::CLK_DISABLE)
285    }
286    #[doc = "Enable clock"]
287    #[inline(always)]
288    pub fn clk_enable(self) -> &'a mut W {
289        self.variant(FRO_DIV16_O_EN_A::CLK_ENABLE)
290    }
291}
292impl R {
293    #[doc = "Bit 0 - FRO Divided-by-1 Clock Enable"]
294    #[inline(always)]
295    pub fn fro_div1_o_en(&self) -> FRO_DIV1_O_EN_R {
296        FRO_DIV1_O_EN_R::new((self.bits & 1) != 0)
297    }
298    #[doc = "Bit 1 - FRO Divided-by-2 Clock Enable"]
299    #[inline(always)]
300    pub fn fro_div2_o_en(&self) -> FRO_DIV2_O_EN_R {
301        FRO_DIV2_O_EN_R::new(((self.bits >> 1) & 1) != 0)
302    }
303    #[doc = "Bit 2 - FRO Divided-by-4 Clock Enable"]
304    #[inline(always)]
305    pub fn fro_div4_o_en(&self) -> FRO_DIV4_O_EN_R {
306        FRO_DIV4_O_EN_R::new(((self.bits >> 2) & 1) != 0)
307    }
308    #[doc = "Bit 3 - FRO Divided-by-8 Clock Enable"]
309    #[inline(always)]
310    pub fn fro_div8_o_en(&self) -> FRO_DIV8_O_EN_R {
311        FRO_DIV8_O_EN_R::new(((self.bits >> 3) & 1) != 0)
312    }
313    #[doc = "Bit 4 - FRO Divided-by-16 Clock Enable"]
314    #[inline(always)]
315    pub fn fro_div16_o_en(&self) -> FRO_DIV16_O_EN_R {
316        FRO_DIV16_O_EN_R::new(((self.bits >> 4) & 1) != 0)
317    }
318}
319impl W {
320    #[doc = "Bit 0 - FRO Divided-by-1 Clock Enable"]
321    #[inline(always)]
322    #[must_use]
323    pub fn fro_div1_o_en(&mut self) -> FRO_DIV1_O_EN_W<0> {
324        FRO_DIV1_O_EN_W::new(self)
325    }
326    #[doc = "Bit 1 - FRO Divided-by-2 Clock Enable"]
327    #[inline(always)]
328    #[must_use]
329    pub fn fro_div2_o_en(&mut self) -> FRO_DIV2_O_EN_W<1> {
330        FRO_DIV2_O_EN_W::new(self)
331    }
332    #[doc = "Bit 2 - FRO Divided-by-4 Clock Enable"]
333    #[inline(always)]
334    #[must_use]
335    pub fn fro_div4_o_en(&mut self) -> FRO_DIV4_O_EN_W<2> {
336        FRO_DIV4_O_EN_W::new(self)
337    }
338    #[doc = "Bit 3 - FRO Divided-by-8 Clock Enable"]
339    #[inline(always)]
340    #[must_use]
341    pub fn fro_div8_o_en(&mut self) -> FRO_DIV8_O_EN_W<3> {
342        FRO_DIV8_O_EN_W::new(self)
343    }
344    #[doc = "Bit 4 - FRO Divided-by-16 Clock Enable"]
345    #[inline(always)]
346    #[must_use]
347    pub fn fro_div16_o_en(&mut self) -> FRO_DIV16_O_EN_W<4> {
348        FRO_DIV16_O_EN_W::new(self)
349    }
350    #[doc = "Writes raw bits to the register."]
351    #[inline(always)]
352    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
353        self.0.bits(bits);
354        self
355    }
356}
357#[doc = "FRO Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [frodivoen](index.html) module"]
358pub struct FRODIVOEN_SPEC;
359impl crate::RegisterSpec for FRODIVOEN_SPEC {
360    type Ux = u32;
361}
362#[doc = "`read()` method returns [frodivoen::R](R) reader structure"]
363impl crate::Readable for FRODIVOEN_SPEC {
364    type Reader = R;
365}
366#[doc = "`write(|w| ..)` method takes [frodivoen::W](W) writer structure"]
367impl crate::Writable for FRODIVOEN_SPEC {
368    type Writer = W;
369    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
370    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
371}
372#[doc = "`reset()` method sets FRODIVOEN to value 0"]
373impl crate::Resettable for FRODIVOEN_SPEC {
374    const RESET_VALUE: Self::Ux = 0;
375}
mimxrt595s/clkctl0/frodivoen.rs

mimxrt595s/clkctl0/
frodivoen.rs
