mimxrt595s/flexspi0/
mcr0.rs

1#[doc = "Register `MCR0` reader"]
2pub struct R(crate::R<MCR0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MCR0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MCR0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MCR0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MCR0` writer"]
17pub struct W(crate::W<MCR0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MCR0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MCR0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MCR0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SWRESET` reader - Software Reset"]
38pub type SWRESET_R = crate::BitReader<SWRESET_A>;
39#[doc = "Software Reset\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum SWRESET_A {
42    #[doc = "0: No impact"]
43    VAL0 = 0,
44    #[doc = "1: Software reset"]
45    VAL1 = 1,
46}
47impl From<SWRESET_A> for bool {
48    #[inline(always)]
49    fn from(variant: SWRESET_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl SWRESET_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> SWRESET_A {
57        match self.bits {
58            false => SWRESET_A::VAL0,
59            true => SWRESET_A::VAL1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `VAL0`"]
63    #[inline(always)]
64    pub fn is_val0(&self) -> bool {
65        *self == SWRESET_A::VAL0
66    }
67    #[doc = "Checks if the value of the field is `VAL1`"]
68    #[inline(always)]
69    pub fn is_val1(&self) -> bool {
70        *self == SWRESET_A::VAL1
71    }
72}
73#[doc = "Field `SWRESET` writer - Software Reset"]
74pub type SWRESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR0_SPEC, SWRESET_A, O>;
75impl<'a, const O: u8> SWRESET_W<'a, O> {
76    #[doc = "No impact"]
77    #[inline(always)]
78    pub fn val0(self) -> &'a mut W {
79        self.variant(SWRESET_A::VAL0)
80    }
81    #[doc = "Software reset"]
82    #[inline(always)]
83    pub fn val1(self) -> &'a mut W {
84        self.variant(SWRESET_A::VAL1)
85    }
86}
87#[doc = "Field `MDIS` reader - Module Disable"]
88pub type MDIS_R = crate::BitReader<MDIS_A>;
89#[doc = "Module Disable\n\nValue on reset: 1"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum MDIS_A {
92    #[doc = "0: No impact"]
93    VAL0 = 0,
94    #[doc = "1: Module disable"]
95    VAL1 = 1,
96}
97impl From<MDIS_A> for bool {
98    #[inline(always)]
99    fn from(variant: MDIS_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl MDIS_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> MDIS_A {
107        match self.bits {
108            false => MDIS_A::VAL0,
109            true => MDIS_A::VAL1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `VAL0`"]
113    #[inline(always)]
114    pub fn is_val0(&self) -> bool {
115        *self == MDIS_A::VAL0
116    }
117    #[doc = "Checks if the value of the field is `VAL1`"]
118    #[inline(always)]
119    pub fn is_val1(&self) -> bool {
120        *self == MDIS_A::VAL1
121    }
122}
123#[doc = "Field `MDIS` writer - Module Disable"]
124pub type MDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR0_SPEC, MDIS_A, O>;
125impl<'a, const O: u8> MDIS_W<'a, O> {
126    #[doc = "No impact"]
127    #[inline(always)]
128    pub fn val0(self) -> &'a mut W {
129        self.variant(MDIS_A::VAL0)
130    }
131    #[doc = "Module disable"]
132    #[inline(always)]
133    pub fn val1(self) -> &'a mut W {
134        self.variant(MDIS_A::VAL1)
135    }
136}
137#[doc = "Field `RXCLKSRC` reader - Sample Clock source selection for Flash Reading"]
138pub type RXCLKSRC_R = crate::FieldReader<u8, RXCLKSRC_A>;
139#[doc = "Sample Clock source selection for Flash Reading\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141#[repr(u8)]
142pub enum RXCLKSRC_A {
143    #[doc = "0: Dummy Read strobe generated by FlexSPI Controller and loopback internally."]
144    VAL0 = 0,
145    #[doc = "1: Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad."]
146    VAL1 = 1,
147    #[doc = "3: Flash provided Read strobe and input from DQS pad"]
148    VAL3 = 3,
149}
150impl From<RXCLKSRC_A> for u8 {
151    #[inline(always)]
152    fn from(variant: RXCLKSRC_A) -> Self {
153        variant as _
154    }
155}
156impl RXCLKSRC_R {
157    #[doc = "Get enumerated values variant"]
158    #[inline(always)]
159    pub fn variant(&self) -> Option<RXCLKSRC_A> {
160        match self.bits {
161            0 => Some(RXCLKSRC_A::VAL0),
162            1 => Some(RXCLKSRC_A::VAL1),
163            3 => Some(RXCLKSRC_A::VAL3),
164            _ => None,
165        }
166    }
167    #[doc = "Checks if the value of the field is `VAL0`"]
168    #[inline(always)]
169    pub fn is_val0(&self) -> bool {
170        *self == RXCLKSRC_A::VAL0
171    }
172    #[doc = "Checks if the value of the field is `VAL1`"]
173    #[inline(always)]
174    pub fn is_val1(&self) -> bool {
175        *self == RXCLKSRC_A::VAL1
176    }
177    #[doc = "Checks if the value of the field is `VAL3`"]
178    #[inline(always)]
179    pub fn is_val3(&self) -> bool {
180        *self == RXCLKSRC_A::VAL3
181    }
182}
183#[doc = "Field `RXCLKSRC` writer - Sample Clock source selection for Flash Reading"]
184pub type RXCLKSRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MCR0_SPEC, u8, RXCLKSRC_A, 2, O>;
185impl<'a, const O: u8> RXCLKSRC_W<'a, O> {
186    #[doc = "Dummy Read strobe generated by FlexSPI Controller and loopback internally."]
187    #[inline(always)]
188    pub fn val0(self) -> &'a mut W {
189        self.variant(RXCLKSRC_A::VAL0)
190    }
191    #[doc = "Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad."]
192    #[inline(always)]
193    pub fn val1(self) -> &'a mut W {
194        self.variant(RXCLKSRC_A::VAL1)
195    }
196    #[doc = "Flash provided Read strobe and input from DQS pad"]
197    #[inline(always)]
198    pub fn val3(self) -> &'a mut W {
199        self.variant(RXCLKSRC_A::VAL3)
200    }
201}
202#[doc = "Field `SERCLKDIV` reader - Serial root clock"]
203pub type SERCLKDIV_R = crate::FieldReader<u8, SERCLKDIV_A>;
204#[doc = "Serial root clock\n\nValue on reset: 0"]
205#[derive(Clone, Copy, Debug, PartialEq, Eq)]
206#[repr(u8)]
207pub enum SERCLKDIV_A {
208    #[doc = "0: Divided by 1"]
209    VAL0 = 0,
210    #[doc = "1: Divided by 2"]
211    VAL1 = 1,
212    #[doc = "2: Divided by 3"]
213    VAL2 = 2,
214    #[doc = "3: Divided by 4"]
215    VAL3 = 3,
216    #[doc = "4: Divided by 5"]
217    VAL4 = 4,
218    #[doc = "5: Divided by 6"]
219    VAL5 = 5,
220    #[doc = "6: Divided by 7"]
221    VAL6 = 6,
222    #[doc = "7: Divided by 8"]
223    VAL7 = 7,
224}
225impl From<SERCLKDIV_A> for u8 {
226    #[inline(always)]
227    fn from(variant: SERCLKDIV_A) -> Self {
228        variant as _
229    }
230}
231impl SERCLKDIV_R {
232    #[doc = "Get enumerated values variant"]
233    #[inline(always)]
234    pub fn variant(&self) -> SERCLKDIV_A {
235        match self.bits {
236            0 => SERCLKDIV_A::VAL0,
237            1 => SERCLKDIV_A::VAL1,
238            2 => SERCLKDIV_A::VAL2,
239            3 => SERCLKDIV_A::VAL3,
240            4 => SERCLKDIV_A::VAL4,
241            5 => SERCLKDIV_A::VAL5,
242            6 => SERCLKDIV_A::VAL6,
243            7 => SERCLKDIV_A::VAL7,
244            _ => unreachable!(),
245        }
246    }
247    #[doc = "Checks if the value of the field is `VAL0`"]
248    #[inline(always)]
249    pub fn is_val0(&self) -> bool {
250        *self == SERCLKDIV_A::VAL0
251    }
252    #[doc = "Checks if the value of the field is `VAL1`"]
253    #[inline(always)]
254    pub fn is_val1(&self) -> bool {
255        *self == SERCLKDIV_A::VAL1
256    }
257    #[doc = "Checks if the value of the field is `VAL2`"]
258    #[inline(always)]
259    pub fn is_val2(&self) -> bool {
260        *self == SERCLKDIV_A::VAL2
261    }
262    #[doc = "Checks if the value of the field is `VAL3`"]
263    #[inline(always)]
264    pub fn is_val3(&self) -> bool {
265        *self == SERCLKDIV_A::VAL3
266    }
267    #[doc = "Checks if the value of the field is `VAL4`"]
268    #[inline(always)]
269    pub fn is_val4(&self) -> bool {
270        *self == SERCLKDIV_A::VAL4
271    }
272    #[doc = "Checks if the value of the field is `VAL5`"]
273    #[inline(always)]
274    pub fn is_val5(&self) -> bool {
275        *self == SERCLKDIV_A::VAL5
276    }
277    #[doc = "Checks if the value of the field is `VAL6`"]
278    #[inline(always)]
279    pub fn is_val6(&self) -> bool {
280        *self == SERCLKDIV_A::VAL6
281    }
282    #[doc = "Checks if the value of the field is `VAL7`"]
283    #[inline(always)]
284    pub fn is_val7(&self) -> bool {
285        *self == SERCLKDIV_A::VAL7
286    }
287}
288#[doc = "Field `SERCLKDIV` writer - Serial root clock"]
289pub type SERCLKDIV_W<'a, const O: u8> =
290    crate::FieldWriterSafe<'a, u32, MCR0_SPEC, u8, SERCLKDIV_A, 3, O>;
291impl<'a, const O: u8> SERCLKDIV_W<'a, O> {
292    #[doc = "Divided by 1"]
293    #[inline(always)]
294    pub fn val0(self) -> &'a mut W {
295        self.variant(SERCLKDIV_A::VAL0)
296    }
297    #[doc = "Divided by 2"]
298    #[inline(always)]
299    pub fn val1(self) -> &'a mut W {
300        self.variant(SERCLKDIV_A::VAL1)
301    }
302    #[doc = "Divided by 3"]
303    #[inline(always)]
304    pub fn val2(self) -> &'a mut W {
305        self.variant(SERCLKDIV_A::VAL2)
306    }
307    #[doc = "Divided by 4"]
308    #[inline(always)]
309    pub fn val3(self) -> &'a mut W {
310        self.variant(SERCLKDIV_A::VAL3)
311    }
312    #[doc = "Divided by 5"]
313    #[inline(always)]
314    pub fn val4(self) -> &'a mut W {
315        self.variant(SERCLKDIV_A::VAL4)
316    }
317    #[doc = "Divided by 6"]
318    #[inline(always)]
319    pub fn val5(self) -> &'a mut W {
320        self.variant(SERCLKDIV_A::VAL5)
321    }
322    #[doc = "Divided by 7"]
323    #[inline(always)]
324    pub fn val6(self) -> &'a mut W {
325        self.variant(SERCLKDIV_A::VAL6)
326    }
327    #[doc = "Divided by 8"]
328    #[inline(always)]
329    pub fn val7(self) -> &'a mut W {
330        self.variant(SERCLKDIV_A::VAL7)
331    }
332}
333#[doc = "Field `HSEN` reader - Half Speed Serial Flash Access Enable."]
334pub type HSEN_R = crate::BitReader<HSEN_A>;
335#[doc = "Half Speed Serial Flash Access Enable.\n\nValue on reset: 0"]
336#[derive(Clone, Copy, Debug, PartialEq, Eq)]
337pub enum HSEN_A {
338    #[doc = "0: Disable divide by 2 of serial flash clock for half clock frequency."]
339    VAL0 = 0,
340    #[doc = "1: Enable divide by 2 of serial flash clock for half clock frequency."]
341    VAL1 = 1,
342}
343impl From<HSEN_A> for bool {
344    #[inline(always)]
345    fn from(variant: HSEN_A) -> Self {
346        variant as u8 != 0
347    }
348}
349impl HSEN_R {
350    #[doc = "Get enumerated values variant"]
351    #[inline(always)]
352    pub fn variant(&self) -> HSEN_A {
353        match self.bits {
354            false => HSEN_A::VAL0,
355            true => HSEN_A::VAL1,
356        }
357    }
358    #[doc = "Checks if the value of the field is `VAL0`"]
359    #[inline(always)]
360    pub fn is_val0(&self) -> bool {
361        *self == HSEN_A::VAL0
362    }
363    #[doc = "Checks if the value of the field is `VAL1`"]
364    #[inline(always)]
365    pub fn is_val1(&self) -> bool {
366        *self == HSEN_A::VAL1
367    }
368}
369#[doc = "Field `HSEN` writer - Half Speed Serial Flash Access Enable."]
370pub type HSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR0_SPEC, HSEN_A, O>;
371impl<'a, const O: u8> HSEN_W<'a, O> {
372    #[doc = "Disable divide by 2 of serial flash clock for half clock frequency."]
373    #[inline(always)]
374    pub fn val0(self) -> &'a mut W {
375        self.variant(HSEN_A::VAL0)
376    }
377    #[doc = "Enable divide by 2 of serial flash clock for half clock frequency."]
378    #[inline(always)]
379    pub fn val1(self) -> &'a mut W {
380        self.variant(HSEN_A::VAL1)
381    }
382}
383#[doc = "Field `DOZEEN` reader - Doze mode enable bit"]
384pub type DOZEEN_R = crate::BitReader<DOZEEN_A>;
385#[doc = "Doze mode enable bit\n\nValue on reset: 0"]
386#[derive(Clone, Copy, Debug, PartialEq, Eq)]
387pub enum DOZEEN_A {
388    #[doc = "0: Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system."]
389    VAL0 = 0,
390    #[doc = "1: Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system."]
391    VAL1 = 1,
392}
393impl From<DOZEEN_A> for bool {
394    #[inline(always)]
395    fn from(variant: DOZEEN_A) -> Self {
396        variant as u8 != 0
397    }
398}
399impl DOZEEN_R {
400    #[doc = "Get enumerated values variant"]
401    #[inline(always)]
402    pub fn variant(&self) -> DOZEEN_A {
403        match self.bits {
404            false => DOZEEN_A::VAL0,
405            true => DOZEEN_A::VAL1,
406        }
407    }
408    #[doc = "Checks if the value of the field is `VAL0`"]
409    #[inline(always)]
410    pub fn is_val0(&self) -> bool {
411        *self == DOZEEN_A::VAL0
412    }
413    #[doc = "Checks if the value of the field is `VAL1`"]
414    #[inline(always)]
415    pub fn is_val1(&self) -> bool {
416        *self == DOZEEN_A::VAL1
417    }
418}
419#[doc = "Field `DOZEEN` writer - Doze mode enable bit"]
420pub type DOZEEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR0_SPEC, DOZEEN_A, O>;
421impl<'a, const O: u8> DOZEEN_W<'a, O> {
422    #[doc = "Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system."]
423    #[inline(always)]
424    pub fn val0(self) -> &'a mut W {
425        self.variant(DOZEEN_A::VAL0)
426    }
427    #[doc = "Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system."]
428    #[inline(always)]
429    pub fn val1(self) -> &'a mut W {
430        self.variant(DOZEEN_A::VAL1)
431    }
432}
433#[doc = "Field `SCKFREERUNEN` reader - This bit is used to enable SCLK output free-running. For FPGA applications, the external device may use SCLK as reference clock to its internal PLL."]
434pub type SCKFREERUNEN_R = crate::BitReader<SCKFREERUNEN_A>;
435#[doc = "This bit is used to enable SCLK output free-running. For FPGA applications, the external device may use SCLK as reference clock to its internal PLL.\n\nValue on reset: 0"]
436#[derive(Clone, Copy, Debug, PartialEq, Eq)]
437pub enum SCKFREERUNEN_A {
438    #[doc = "0: Disable SCLK output free-running."]
439    DISABLE = 0,
440    #[doc = "1: Enable SCLK output free-running."]
441    ENABLE = 1,
442}
443impl From<SCKFREERUNEN_A> for bool {
444    #[inline(always)]
445    fn from(variant: SCKFREERUNEN_A) -> Self {
446        variant as u8 != 0
447    }
448}
449impl SCKFREERUNEN_R {
450    #[doc = "Get enumerated values variant"]
451    #[inline(always)]
452    pub fn variant(&self) -> SCKFREERUNEN_A {
453        match self.bits {
454            false => SCKFREERUNEN_A::DISABLE,
455            true => SCKFREERUNEN_A::ENABLE,
456        }
457    }
458    #[doc = "Checks if the value of the field is `DISABLE`"]
459    #[inline(always)]
460    pub fn is_disable(&self) -> bool {
461        *self == SCKFREERUNEN_A::DISABLE
462    }
463    #[doc = "Checks if the value of the field is `ENABLE`"]
464    #[inline(always)]
465    pub fn is_enable(&self) -> bool {
466        *self == SCKFREERUNEN_A::ENABLE
467    }
468}
469#[doc = "Field `SCKFREERUNEN` writer - This bit is used to enable SCLK output free-running. For FPGA applications, the external device may use SCLK as reference clock to its internal PLL."]
470pub type SCKFREERUNEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR0_SPEC, SCKFREERUNEN_A, O>;
471impl<'a, const O: u8> SCKFREERUNEN_W<'a, O> {
472    #[doc = "Disable SCLK output free-running."]
473    #[inline(always)]
474    pub fn disable(self) -> &'a mut W {
475        self.variant(SCKFREERUNEN_A::DISABLE)
476    }
477    #[doc = "Enable SCLK output free-running."]
478    #[inline(always)]
479    pub fn enable(self) -> &'a mut W {
480        self.variant(SCKFREERUNEN_A::ENABLE)
481    }
482}
483#[doc = "Field `LEARNEN` reader - This bit is used to enable/disable the data learning feature."]
484pub type LEARNEN_R = crate::BitReader<LEARNEN_A>;
485#[doc = "This bit is used to enable/disable the data learning feature.\n\nValue on reset: 1"]
486#[derive(Clone, Copy, Debug, PartialEq, Eq)]
487pub enum LEARNEN_A {
488    #[doc = "0: Disable the data learning feature."]
489    DISABLE = 0,
490    #[doc = "1: Enable the data learning feature."]
491    ENABLE = 1,
492}
493impl From<LEARNEN_A> for bool {
494    #[inline(always)]
495    fn from(variant: LEARNEN_A) -> Self {
496        variant as u8 != 0
497    }
498}
499impl LEARNEN_R {
500    #[doc = "Get enumerated values variant"]
501    #[inline(always)]
502    pub fn variant(&self) -> LEARNEN_A {
503        match self.bits {
504            false => LEARNEN_A::DISABLE,
505            true => LEARNEN_A::ENABLE,
506        }
507    }
508    #[doc = "Checks if the value of the field is `DISABLE`"]
509    #[inline(always)]
510    pub fn is_disable(&self) -> bool {
511        *self == LEARNEN_A::DISABLE
512    }
513    #[doc = "Checks if the value of the field is `ENABLE`"]
514    #[inline(always)]
515    pub fn is_enable(&self) -> bool {
516        *self == LEARNEN_A::ENABLE
517    }
518}
519#[doc = "Field `LEARNEN` writer - This bit is used to enable/disable the data learning feature."]
520pub type LEARNEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR0_SPEC, LEARNEN_A, O>;
521impl<'a, const O: u8> LEARNEN_W<'a, O> {
522    #[doc = "Disable the data learning feature."]
523    #[inline(always)]
524    pub fn disable(self) -> &'a mut W {
525        self.variant(LEARNEN_A::DISABLE)
526    }
527    #[doc = "Enable the data learning feature."]
528    #[inline(always)]
529    pub fn enable(self) -> &'a mut W {
530        self.variant(LEARNEN_A::ENABLE)
531    }
532}
533#[doc = "Field `IPGRANTWAIT` reader - Timeout wait cycle for IP command grant."]
534pub type IPGRANTWAIT_R = crate::FieldReader<u8, u8>;
535#[doc = "Field `IPGRANTWAIT` writer - Timeout wait cycle for IP command grant."]
536pub type IPGRANTWAIT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MCR0_SPEC, u8, u8, 8, O>;
537#[doc = "Field `AHBGRANTWAIT` reader - Timeout wait cycle for AHB command grant."]
538pub type AHBGRANTWAIT_R = crate::FieldReader<u8, u8>;
539#[doc = "Field `AHBGRANTWAIT` writer - Timeout wait cycle for AHB command grant."]
540pub type AHBGRANTWAIT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MCR0_SPEC, u8, u8, 8, O>;
541impl R {
542    #[doc = "Bit 0 - Software Reset"]
543    #[inline(always)]
544    pub fn swreset(&self) -> SWRESET_R {
545        SWRESET_R::new((self.bits & 1) != 0)
546    }
547    #[doc = "Bit 1 - Module Disable"]
548    #[inline(always)]
549    pub fn mdis(&self) -> MDIS_R {
550        MDIS_R::new(((self.bits >> 1) & 1) != 0)
551    }
552    #[doc = "Bits 4:5 - Sample Clock source selection for Flash Reading"]
553    #[inline(always)]
554    pub fn rxclksrc(&self) -> RXCLKSRC_R {
555        RXCLKSRC_R::new(((self.bits >> 4) & 3) as u8)
556    }
557    #[doc = "Bits 8:10 - Serial root clock"]
558    #[inline(always)]
559    pub fn serclkdiv(&self) -> SERCLKDIV_R {
560        SERCLKDIV_R::new(((self.bits >> 8) & 7) as u8)
561    }
562    #[doc = "Bit 11 - Half Speed Serial Flash Access Enable."]
563    #[inline(always)]
564    pub fn hsen(&self) -> HSEN_R {
565        HSEN_R::new(((self.bits >> 11) & 1) != 0)
566    }
567    #[doc = "Bit 12 - Doze mode enable bit"]
568    #[inline(always)]
569    pub fn dozeen(&self) -> DOZEEN_R {
570        DOZEEN_R::new(((self.bits >> 12) & 1) != 0)
571    }
572    #[doc = "Bit 14 - This bit is used to enable SCLK output free-running. For FPGA applications, the external device may use SCLK as reference clock to its internal PLL."]
573    #[inline(always)]
574    pub fn sckfreerunen(&self) -> SCKFREERUNEN_R {
575        SCKFREERUNEN_R::new(((self.bits >> 14) & 1) != 0)
576    }
577    #[doc = "Bit 15 - This bit is used to enable/disable the data learning feature."]
578    #[inline(always)]
579    pub fn learnen(&self) -> LEARNEN_R {
580        LEARNEN_R::new(((self.bits >> 15) & 1) != 0)
581    }
582    #[doc = "Bits 16:23 - Timeout wait cycle for IP command grant."]
583    #[inline(always)]
584    pub fn ipgrantwait(&self) -> IPGRANTWAIT_R {
585        IPGRANTWAIT_R::new(((self.bits >> 16) & 0xff) as u8)
586    }
587    #[doc = "Bits 24:31 - Timeout wait cycle for AHB command grant."]
588    #[inline(always)]
589    pub fn ahbgrantwait(&self) -> AHBGRANTWAIT_R {
590        AHBGRANTWAIT_R::new(((self.bits >> 24) & 0xff) as u8)
591    }
592}
593impl W {
594    #[doc = "Bit 0 - Software Reset"]
595    #[inline(always)]
596    #[must_use]
597    pub fn swreset(&mut self) -> SWRESET_W<0> {
598        SWRESET_W::new(self)
599    }
600    #[doc = "Bit 1 - Module Disable"]
601    #[inline(always)]
602    #[must_use]
603    pub fn mdis(&mut self) -> MDIS_W<1> {
604        MDIS_W::new(self)
605    }
606    #[doc = "Bits 4:5 - Sample Clock source selection for Flash Reading"]
607    #[inline(always)]
608    #[must_use]
609    pub fn rxclksrc(&mut self) -> RXCLKSRC_W<4> {
610        RXCLKSRC_W::new(self)
611    }
612    #[doc = "Bits 8:10 - Serial root clock"]
613    #[inline(always)]
614    #[must_use]
615    pub fn serclkdiv(&mut self) -> SERCLKDIV_W<8> {
616        SERCLKDIV_W::new(self)
617    }
618    #[doc = "Bit 11 - Half Speed Serial Flash Access Enable."]
619    #[inline(always)]
620    #[must_use]
621    pub fn hsen(&mut self) -> HSEN_W<11> {
622        HSEN_W::new(self)
623    }
624    #[doc = "Bit 12 - Doze mode enable bit"]
625    #[inline(always)]
626    #[must_use]
627    pub fn dozeen(&mut self) -> DOZEEN_W<12> {
628        DOZEEN_W::new(self)
629    }
630    #[doc = "Bit 14 - This bit is used to enable SCLK output free-running. For FPGA applications, the external device may use SCLK as reference clock to its internal PLL."]
631    #[inline(always)]
632    #[must_use]
633    pub fn sckfreerunen(&mut self) -> SCKFREERUNEN_W<14> {
634        SCKFREERUNEN_W::new(self)
635    }
636    #[doc = "Bit 15 - This bit is used to enable/disable the data learning feature."]
637    #[inline(always)]
638    #[must_use]
639    pub fn learnen(&mut self) -> LEARNEN_W<15> {
640        LEARNEN_W::new(self)
641    }
642    #[doc = "Bits 16:23 - Timeout wait cycle for IP command grant."]
643    #[inline(always)]
644    #[must_use]
645    pub fn ipgrantwait(&mut self) -> IPGRANTWAIT_W<16> {
646        IPGRANTWAIT_W::new(self)
647    }
648    #[doc = "Bits 24:31 - Timeout wait cycle for AHB command grant."]
649    #[inline(always)]
650    #[must_use]
651    pub fn ahbgrantwait(&mut self) -> AHBGRANTWAIT_W<24> {
652        AHBGRANTWAIT_W::new(self)
653    }
654    #[doc = "Writes raw bits to the register."]
655    #[inline(always)]
656    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
657        self.0.bits(bits);
658        self
659    }
660}
661#[doc = "Module Control Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr0](index.html) module"]
662pub struct MCR0_SPEC;
663impl crate::RegisterSpec for MCR0_SPEC {
664    type Ux = u32;
665}
666#[doc = "`read()` method returns [mcr0::R](R) reader structure"]
667impl crate::Readable for MCR0_SPEC {
668    type Reader = R;
669}
670#[doc = "`write(|w| ..)` method takes [mcr0::W](W) writer structure"]
671impl crate::Writable for MCR0_SPEC {
672    type Writer = W;
673    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
674    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
675}
676#[doc = "`reset()` method sets MCR0 to value 0xffff_80c2"]
677impl crate::Resettable for MCR0_SPEC {
678    const RESET_VALUE: Self::Ux = 0xffff_80c2;
679}
mimxrt595s/flexspi0/mcr0.rs

mimxrt595s/flexspi0/
mcr0.rs
