mimxrt595s/clkctl1/
frg0clksel.rs

1#[doc = "Register `FRG0CLKSEL` reader"]
2pub struct R(crate::R<FRG0CLKSEL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FRG0CLKSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FRG0CLKSEL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FRG0CLKSEL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `FRG0CLKSEL` writer"]
17pub struct W(crate::W<FRG0CLKSEL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FRG0CLKSEL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FRG0CLKSEL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FRG0CLKSEL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SEL` reader - Fractional Generator 0 Clock Source"]
38pub type SEL_R = crate::FieldReader<u8, SEL_A>;
39#[doc = "Fractional Generator 0 Clock Source\n\nValue on reset: 7"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum SEL_A {
43    #[doc = "0: Main Clock"]
44    MAIN = 0,
45    #[doc = "1: FRG PLL Clock"]
46    FRG_PLL = 1,
47    #[doc = "2: FRO_DIV4 clock"]
48    FRRO_DIV4 = 2,
49    #[doc = "7: None, output gated to reduce power"]
50    NONE = 7,
51}
52impl From<SEL_A> for u8 {
53    #[inline(always)]
54    fn from(variant: SEL_A) -> Self {
55        variant as _
56    }
57}
58impl SEL_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> Option<SEL_A> {
62        match self.bits {
63            0 => Some(SEL_A::MAIN),
64            1 => Some(SEL_A::FRG_PLL),
65            2 => Some(SEL_A::FRRO_DIV4),
66            7 => Some(SEL_A::NONE),
67            _ => None,
68        }
69    }
70    #[doc = "Checks if the value of the field is `MAIN`"]
71    #[inline(always)]
72    pub fn is_main(&self) -> bool {
73        *self == SEL_A::MAIN
74    }
75    #[doc = "Checks if the value of the field is `FRG_PLL`"]
76    #[inline(always)]
77    pub fn is_frg_pll(&self) -> bool {
78        *self == SEL_A::FRG_PLL
79    }
80    #[doc = "Checks if the value of the field is `FRRO_DIV4`"]
81    #[inline(always)]
82    pub fn is_frro_div4(&self) -> bool {
83        *self == SEL_A::FRRO_DIV4
84    }
85    #[doc = "Checks if the value of the field is `NONE`"]
86    #[inline(always)]
87    pub fn is_none(&self) -> bool {
88        *self == SEL_A::NONE
89    }
90}
91#[doc = "Field `SEL` writer - Fractional Generator 0 Clock Source"]
92pub type SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FRG0CLKSEL_SPEC, u8, SEL_A, 3, O>;
93impl<'a, const O: u8> SEL_W<'a, O> {
94    #[doc = "Main Clock"]
95    #[inline(always)]
96    pub fn main(self) -> &'a mut W {
97        self.variant(SEL_A::MAIN)
98    }
99    #[doc = "FRG PLL Clock"]
100    #[inline(always)]
101    pub fn frg_pll(self) -> &'a mut W {
102        self.variant(SEL_A::FRG_PLL)
103    }
104    #[doc = "FRO_DIV4 clock"]
105    #[inline(always)]
106    pub fn frro_div4(self) -> &'a mut W {
107        self.variant(SEL_A::FRRO_DIV4)
108    }
109    #[doc = "None, output gated to reduce power"]
110    #[inline(always)]
111    pub fn none(self) -> &'a mut W {
112        self.variant(SEL_A::NONE)
113    }
114}
115impl R {
116    #[doc = "Bits 0:2 - Fractional Generator 0 Clock Source"]
117    #[inline(always)]
118    pub fn sel(&self) -> SEL_R {
119        SEL_R::new((self.bits & 7) as u8)
120    }
121}
122impl W {
123    #[doc = "Bits 0:2 - Fractional Generator 0 Clock Source"]
124    #[inline(always)]
125    #[must_use]
126    pub fn sel(&mut self) -> SEL_W<0> {
127        SEL_W::new(self)
128    }
129    #[doc = "Writes raw bits to the register."]
130    #[inline(always)]
131    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
132        self.0.bits(bits);
133        self
134    }
135}
136#[doc = "Fractional Rate Generator 0 Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [frg0clksel](index.html) module"]
137pub struct FRG0CLKSEL_SPEC;
138impl crate::RegisterSpec for FRG0CLKSEL_SPEC {
139    type Ux = u32;
140}
141#[doc = "`read()` method returns [frg0clksel::R](R) reader structure"]
142impl crate::Readable for FRG0CLKSEL_SPEC {
143    type Reader = R;
144}
145#[doc = "`write(|w| ..)` method takes [frg0clksel::W](W) writer structure"]
146impl crate::Writable for FRG0CLKSEL_SPEC {
147    type Writer = W;
148    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
149    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
150}
151#[doc = "`reset()` method sets FRG0CLKSEL to value 0x07"]
152impl crate::Resettable for FRG0CLKSEL_SPEC {
153    const RESET_VALUE: Self::Ux = 0x07;
154}
mimxrt595s/clkctl1/frg0clksel.rs

mimxrt595s/clkctl1/
frg0clksel.rs
