#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "0x00 - DMA control"]
    pub ctrl: CTRL,
    #[doc = "0x04 - Interrupt status"]
    pub intstat: INTSTAT,
    #[doc = "0x08 - SRAM address of the channel configuration table"]
    pub srambase: SRAMBASE,
    _reserved3: [u8; 0x14],
    #[doc = "0x20 - Channel Enable read and set for all DMA channels"]
    pub enableset0: ENABLESET0,
    #[doc = "0x24 - Channel Enable read and set for all DMA channels"]
    pub enableset1: ENABLESET1,
    #[doc = "0x28 - Channel Enable Clear for all DMA channels"]
    pub enableclr0: ENABLECLR0,
    #[doc = "0x2c - Channel Enable Clear for all DMA channels"]
    pub enableclr1: ENABLECLR1,
    #[doc = "0x30 - Channel Active status for all DMA channels"]
    pub active0: ACTIVE0,
    #[doc = "0x34 - Channel Active status for all DMA channels"]
    pub active1: ACTIVE1,
    #[doc = "0x38 - Channel Busy status for all DMA channels"]
    pub busy0: BUSY0,
    #[doc = "0x3c - Channel Busy status for all DMA channels"]
    pub busy1: BUSY1,
    #[doc = "0x40 - Error Interrupt status for all DMA channels"]
    pub errint0: ERRINT0,
    #[doc = "0x44 - Error Interrupt status for all DMA channels"]
    pub errint1: ERRINT1,
    #[doc = "0x48 - Interrupt Enable read and Set for all DMA channels"]
    pub intenset0: INTENSET0,
    #[doc = "0x4c - Interrupt Enable read and Set for all DMA channels"]
    pub intenset1: INTENSET1,
    #[doc = "0x50 - Interrupt Enable Clear for all DMA channels"]
    pub intenclr0: INTENCLR0,
    #[doc = "0x54 - Interrupt Enable Clear for all DMA channels"]
    pub intenclr1: INTENCLR1,
    #[doc = "0x58 - Interrupt A status for all DMA channels"]
    pub inta0: INTA0,
    #[doc = "0x5c - Interrupt A status for all DMA channels"]
    pub inta1: INTA1,
    #[doc = "0x60 - Interrupt B status for all DMA channels"]
    pub intb0: INTB0,
    #[doc = "0x64 - Interrupt B status for all DMA channels"]
    pub intb1: INTB1,
    #[doc = "0x68 - Set ValidPending control bits for all DMA channels"]
    pub setvalid0: SETVALID0,
    #[doc = "0x6c - Set ValidPending control bits for all DMA channels"]
    pub setvalid1: SETVALID1,
    #[doc = "0x70 - Set Trigger control bits for all DMA channels"]
    pub settrig0: SETTRIG0,
    #[doc = "0x74 - Set Trigger control bits for all DMA channels"]
    pub settrig1: SETTRIG1,
    #[doc = "0x78 - Channel Abort control for all DMA channels"]
    pub abort0: ABORT0,
    #[doc = "0x7c - Channel Abort control for all DMA channels"]
    pub abort1: ABORT1,
    _reserved27: [u8; 0x0380],
    #[doc = "0x400..0x40c - no description available"]
    pub channel0: CHANNEL,
    _reserved28: [u8; 0x04],
    #[doc = "0x410..0x41c - no description available"]
    pub channel1: CHANNEL,
    _reserved29: [u8; 0x04],
    #[doc = "0x420..0x42c - no description available"]
    pub channel2: CHANNEL,
    _reserved30: [u8; 0x04],
    #[doc = "0x430..0x43c - no description available"]
    pub channel3: CHANNEL,
    _reserved31: [u8; 0x04],
    #[doc = "0x440..0x44c - no description available"]
    pub channel4: CHANNEL,
    _reserved32: [u8; 0x04],
    #[doc = "0x450..0x45c - no description available"]
    pub channel5: CHANNEL,
    _reserved33: [u8; 0x04],
    #[doc = "0x460..0x46c - no description available"]
    pub channel6: CHANNEL,
    _reserved34: [u8; 0x04],
    #[doc = "0x470..0x47c - no description available"]
    pub channel7: CHANNEL,
    _reserved35: [u8; 0x04],
    #[doc = "0x480..0x48c - no description available"]
    pub channel8: CHANNEL,
    _reserved36: [u8; 0x04],
    #[doc = "0x490..0x49c - no description available"]
    pub channel9: CHANNEL,
    _reserved37: [u8; 0x04],
    #[doc = "0x4a0..0x4ac - no description available"]
    pub channel10: CHANNEL,
    _reserved38: [u8; 0x04],
    #[doc = "0x4b0..0x4bc - no description available"]
    pub channel11: CHANNEL,
    _reserved39: [u8; 0x04],
    #[doc = "0x4c0..0x4cc - no description available"]
    pub channel12: CHANNEL,
    _reserved40: [u8; 0x04],
    #[doc = "0x4d0..0x4dc - no description available"]
    pub channel13: CHANNEL,
    _reserved41: [u8; 0x04],
    #[doc = "0x4e0..0x4ec - no description available"]
    pub channel14: CHANNEL,
    _reserved42: [u8; 0x04],
    #[doc = "0x4f0..0x4fc - no description available"]
    pub channel15: CHANNEL,
    _reserved43: [u8; 0x04],
    #[doc = "0x500..0x50c - no description available"]
    pub channel16: CHANNEL,
    _reserved44: [u8; 0x04],
    #[doc = "0x510..0x51c - no description available"]
    pub channel17: CHANNEL,
    _reserved45: [u8; 0x04],
    #[doc = "0x520..0x52c - no description available"]
    pub channel18: CHANNEL,
    _reserved46: [u8; 0x04],
    #[doc = "0x530..0x53c - no description available"]
    pub channel19: CHANNEL,
    _reserved47: [u8; 0x04],
    #[doc = "0x540..0x54c - no description available"]
    pub channel20: CHANNEL,
    _reserved48: [u8; 0x04],
    #[doc = "0x550..0x55c - no description available"]
    pub channel21: CHANNEL,
    _reserved49: [u8; 0x04],
    #[doc = "0x560..0x56c - no description available"]
    pub channel22: CHANNEL,
    _reserved50: [u8; 0x04],
    #[doc = "0x570..0x57c - no description available"]
    pub channel23: CHANNEL,
    _reserved51: [u8; 0x04],
    #[doc = "0x580..0x58c - no description available"]
    pub channel24: CHANNEL,
    _reserved52: [u8; 0x04],
    #[doc = "0x590..0x59c - no description available"]
    pub channel25: CHANNEL,
    _reserved53: [u8; 0x04],
    #[doc = "0x5a0..0x5ac - no description available"]
    pub channel26: CHANNEL,
    _reserved54: [u8; 0x04],
    #[doc = "0x5b0..0x5bc - no description available"]
    pub channel27: CHANNEL,
    _reserved55: [u8; 0x04],
    #[doc = "0x5c0..0x5cc - no description available"]
    pub channel28: CHANNEL,
    _reserved56: [u8; 0x04],
    #[doc = "0x5d0..0x5dc - no description available"]
    pub channel29: CHANNEL,
    _reserved57: [u8; 0x04],
    #[doc = "0x5e0..0x5ec - no description available"]
    pub channel30: CHANNEL,
    _reserved58: [u8; 0x04],
    #[doc = "0x5f0..0x5fc - no description available"]
    pub channel31: CHANNEL,
    _reserved59: [u8; 0x04],
    #[doc = "0x600..0x60c - no description available"]
    pub channel32: CHANNEL,
    _reserved60: [u8; 0x04],
    #[doc = "0x610..0x61c - no description available"]
    pub channel33: CHANNEL,
    _reserved61: [u8; 0x04],
    #[doc = "0x620..0x62c - no description available"]
    pub channel34: CHANNEL,
    _reserved62: [u8; 0x04],
    #[doc = "0x630..0x63c - no description available"]
    pub channel35: CHANNEL,
    _reserved63: [u8; 0x04],
    #[doc = "0x640..0x64c - no description available"]
    pub channel36: CHANNEL,
}
#[doc = "CTRL (rw) register accessor: an alias for `Reg<CTRL_SPEC>`"]
pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
#[doc = "DMA control"]
pub mod ctrl;
#[doc = "INTSTAT (r) register accessor: an alias for `Reg<INTSTAT_SPEC>`"]
pub type INTSTAT = crate::Reg<intstat::INTSTAT_SPEC>;
#[doc = "Interrupt status"]
pub mod intstat;
#[doc = "SRAMBASE (rw) register accessor: an alias for `Reg<SRAMBASE_SPEC>`"]
pub type SRAMBASE = crate::Reg<srambase::SRAMBASE_SPEC>;
#[doc = "SRAM address of the channel configuration table"]
pub mod srambase;
#[doc = "ENABLESET0 (rw) register accessor: an alias for `Reg<ENABLESET0_SPEC>`"]
pub type ENABLESET0 = crate::Reg<enableset0::ENABLESET0_SPEC>;
#[doc = "Channel Enable read and set for all DMA channels"]
pub mod enableset0;
#[doc = "ENABLESET1 (rw) register accessor: an alias for `Reg<ENABLESET1_SPEC>`"]
pub type ENABLESET1 = crate::Reg<enableset1::ENABLESET1_SPEC>;
#[doc = "Channel Enable read and set for all DMA channels"]
pub mod enableset1;
#[doc = "ENABLECLR0 (rw) register accessor: an alias for `Reg<ENABLECLR0_SPEC>`"]
pub type ENABLECLR0 = crate::Reg<enableclr0::ENABLECLR0_SPEC>;
#[doc = "Channel Enable Clear for all DMA channels"]
pub mod enableclr0;
#[doc = "ENABLECLR1 (rw) register accessor: an alias for `Reg<ENABLECLR1_SPEC>`"]
pub type ENABLECLR1 = crate::Reg<enableclr1::ENABLECLR1_SPEC>;
#[doc = "Channel Enable Clear for all DMA channels"]
pub mod enableclr1;
#[doc = "ACTIVE0 (r) register accessor: an alias for `Reg<ACTIVE0_SPEC>`"]
pub type ACTIVE0 = crate::Reg<active0::ACTIVE0_SPEC>;
#[doc = "Channel Active status for all DMA channels"]
pub mod active0;
#[doc = "ACTIVE1 (r) register accessor: an alias for `Reg<ACTIVE1_SPEC>`"]
pub type ACTIVE1 = crate::Reg<active1::ACTIVE1_SPEC>;
#[doc = "Channel Active status for all DMA channels"]
pub mod active1;
#[doc = "BUSY0 (r) register accessor: an alias for `Reg<BUSY0_SPEC>`"]
pub type BUSY0 = crate::Reg<busy0::BUSY0_SPEC>;
#[doc = "Channel Busy status for all DMA channels"]
pub mod busy0;
#[doc = "BUSY1 (r) register accessor: an alias for `Reg<BUSY1_SPEC>`"]
pub type BUSY1 = crate::Reg<busy1::BUSY1_SPEC>;
#[doc = "Channel Busy status for all DMA channels"]
pub mod busy1;
#[doc = "ERRINT0 (rw) register accessor: an alias for `Reg<ERRINT0_SPEC>`"]
pub type ERRINT0 = crate::Reg<errint0::ERRINT0_SPEC>;
#[doc = "Error Interrupt status for all DMA channels"]
pub mod errint0;
#[doc = "ERRINT1 (rw) register accessor: an alias for `Reg<ERRINT1_SPEC>`"]
pub type ERRINT1 = crate::Reg<errint1::ERRINT1_SPEC>;
#[doc = "Error Interrupt status for all DMA channels"]
pub mod errint1;
#[doc = "INTENSET0 (rw) register accessor: an alias for `Reg<INTENSET0_SPEC>`"]
pub type INTENSET0 = crate::Reg<intenset0::INTENSET0_SPEC>;
#[doc = "Interrupt Enable read and Set for all DMA channels"]
pub mod intenset0;
#[doc = "INTENSET1 (rw) register accessor: an alias for `Reg<INTENSET1_SPEC>`"]
pub type INTENSET1 = crate::Reg<intenset1::INTENSET1_SPEC>;
#[doc = "Interrupt Enable read and Set for all DMA channels"]
pub mod intenset1;
#[doc = "INTENCLR0 (w) register accessor: an alias for `Reg<INTENCLR0_SPEC>`"]
pub type INTENCLR0 = crate::Reg<intenclr0::INTENCLR0_SPEC>;
#[doc = "Interrupt Enable Clear for all DMA channels"]
pub mod intenclr0;
#[doc = "INTENCLR1 (w) register accessor: an alias for `Reg<INTENCLR1_SPEC>`"]
pub type INTENCLR1 = crate::Reg<intenclr1::INTENCLR1_SPEC>;
#[doc = "Interrupt Enable Clear for all DMA channels"]
pub mod intenclr1;
#[doc = "INTA0 (rw) register accessor: an alias for `Reg<INTA0_SPEC>`"]
pub type INTA0 = crate::Reg<inta0::INTA0_SPEC>;
#[doc = "Interrupt A status for all DMA channels"]
pub mod inta0;
#[doc = "INTA1 (rw) register accessor: an alias for `Reg<INTA1_SPEC>`"]
pub type INTA1 = crate::Reg<inta1::INTA1_SPEC>;
#[doc = "Interrupt A status for all DMA channels"]
pub mod inta1;
#[doc = "INTB0 (rw) register accessor: an alias for `Reg<INTB0_SPEC>`"]
pub type INTB0 = crate::Reg<intb0::INTB0_SPEC>;
#[doc = "Interrupt B status for all DMA channels"]
pub mod intb0;
#[doc = "INTB1 (rw) register accessor: an alias for `Reg<INTB1_SPEC>`"]
pub type INTB1 = crate::Reg<intb1::INTB1_SPEC>;
#[doc = "Interrupt B status for all DMA channels"]
pub mod intb1;
#[doc = "SETVALID0 (w) register accessor: an alias for `Reg<SETVALID0_SPEC>`"]
pub type SETVALID0 = crate::Reg<setvalid0::SETVALID0_SPEC>;
#[doc = "Set ValidPending control bits for all DMA channels"]
pub mod setvalid0;
#[doc = "SETVALID1 (w) register accessor: an alias for `Reg<SETVALID1_SPEC>`"]
pub type SETVALID1 = crate::Reg<setvalid1::SETVALID1_SPEC>;
#[doc = "Set ValidPending control bits for all DMA channels"]
pub mod setvalid1;
#[doc = "SETTRIG0 (w) register accessor: an alias for `Reg<SETTRIG0_SPEC>`"]
pub type SETTRIG0 = crate::Reg<settrig0::SETTRIG0_SPEC>;
#[doc = "Set Trigger control bits for all DMA channels"]
pub mod settrig0;
#[doc = "SETTRIG1 (w) register accessor: an alias for `Reg<SETTRIG1_SPEC>`"]
pub type SETTRIG1 = crate::Reg<settrig1::SETTRIG1_SPEC>;
#[doc = "Set Trigger control bits for all DMA channels"]
pub mod settrig1;
#[doc = "ABORT0 (w) register accessor: an alias for `Reg<ABORT0_SPEC>`"]
pub type ABORT0 = crate::Reg<abort0::ABORT0_SPEC>;
#[doc = "Channel Abort control for all DMA channels"]
pub mod abort0;
#[doc = "ABORT1 (w) register accessor: an alias for `Reg<ABORT1_SPEC>`"]
pub type ABORT1 = crate::Reg<abort1::ABORT1_SPEC>;
#[doc = "Channel Abort control for all DMA channels"]
pub mod abort1;
#[doc = "no description available"]
pub use self::channel::CHANNEL;
#[doc = r"Cluster"]
#[doc = "no description available"]
pub mod channel;