mcxn947_pac/usbphy/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `ENOTG_ID_CHG_IRQ` reader - EN ID change IRQ"]
6pub type ENOTG_ID_CHG_IRQ_R = crate::BitReader;
7#[doc = "Field `ENOTG_ID_CHG_IRQ` writer - EN ID change IRQ"]
8pub type ENOTG_ID_CHG_IRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENHOSTDISCONDETECT` reader - Disconnect detect"]
10pub type ENHOSTDISCONDETECT_R = crate::BitReader;
11#[doc = "Field `ENHOSTDISCONDETECT` writer - Disconnect detect"]
12pub type ENHOSTDISCONDETECT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ENIRQHOSTDISCON` reader - Enable IRQ for Host disconnect"]
14pub type ENIRQHOSTDISCON_R = crate::BitReader;
15#[doc = "Field `ENIRQHOSTDISCON` writer - Enable IRQ for Host disconnect"]
16pub type ENIRQHOSTDISCON_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `HOSTDISCONDETECT_IRQ` reader - Device disconnect indication"]
18pub type HOSTDISCONDETECT_IRQ_R = crate::BitReader;
19#[doc = "Field `HOSTDISCONDETECT_IRQ` writer - Device disconnect indication"]
20pub type HOSTDISCONDETECT_IRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ENDEVPLUGINDETECT` reader - Enables non-standard resistive plugged-in detection"]
22pub type ENDEVPLUGINDETECT_R = crate::BitReader<ENDEVPLUGINDETECT_A>;
23#[doc = "Enables non-standard resistive plugged-in detection\n\nValue on reset: 0"]
24#[derive(Clone, Copy, Debug, PartialEq, Eq)]
25pub enum ENDEVPLUGINDETECT_A {
26    #[doc = "0: Disables 200 kohm pullup resistors on USB_DP and USB_DM pins"]
27    PLUGIN_DISABLE = 0,
28    #[doc = "1: Enables 200 kohm pullup resistors on USB_DP and USB_DM pins"]
29    PLUGIN_ENABLE = 1,
30}
31impl From<ENDEVPLUGINDETECT_A> for bool {
32    #[inline(always)]
33    fn from(variant: ENDEVPLUGINDETECT_A) -> Self {
34        variant as u8 != 0
35    }
36}
37impl ENDEVPLUGINDETECT_R {
38    #[doc = "Get enumerated values variant"]
39    #[inline(always)]
40    pub const fn variant(&self) -> ENDEVPLUGINDETECT_A {
41        match self.bits {
42            false => ENDEVPLUGINDETECT_A::PLUGIN_DISABLE,
43            true => ENDEVPLUGINDETECT_A::PLUGIN_ENABLE,
44        }
45    }
46    #[doc = "Disables 200 kohm pullup resistors on USB_DP and USB_DM pins"]
47    #[inline(always)]
48    pub fn is_plugin_disable(&self) -> bool {
49        *self == ENDEVPLUGINDETECT_A::PLUGIN_DISABLE
50    }
51    #[doc = "Enables 200 kohm pullup resistors on USB_DP and USB_DM pins"]
52    #[inline(always)]
53    pub fn is_plugin_enable(&self) -> bool {
54        *self == ENDEVPLUGINDETECT_A::PLUGIN_ENABLE
55    }
56}
57#[doc = "Field `ENDEVPLUGINDETECT` writer - Enables non-standard resistive plugged-in detection"]
58pub type ENDEVPLUGINDETECT_W<'a, REG> = crate::BitWriter<'a, REG, ENDEVPLUGINDETECT_A>;
59impl<'a, REG> ENDEVPLUGINDETECT_W<'a, REG>
60where
61    REG: crate::Writable + crate::RegisterSpec,
62{
63    #[doc = "Disables 200 kohm pullup resistors on USB_DP and USB_DM pins"]
64    #[inline(always)]
65    pub fn plugin_disable(self) -> &'a mut crate::W<REG> {
66        self.variant(ENDEVPLUGINDETECT_A::PLUGIN_DISABLE)
67    }
68    #[doc = "Enables 200 kohm pullup resistors on USB_DP and USB_DM pins"]
69    #[inline(always)]
70    pub fn plugin_enable(self) -> &'a mut crate::W<REG> {
71        self.variant(ENDEVPLUGINDETECT_A::PLUGIN_ENABLE)
72    }
73}
74#[doc = "Field `DEVPLUGIN_POLARITY` reader - Device plugin polarity interrupt configuration for non-standard resistive plugged-in detection"]
75pub type DEVPLUGIN_POLARITY_R = crate::BitReader;
76#[doc = "Field `DEVPLUGIN_POLARITY` writer - Device plugin polarity interrupt configuration for non-standard resistive plugged-in detection"]
77pub type DEVPLUGIN_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>;
78#[doc = "Field `OTG_ID_CHG_IRQ` reader - OTG ID change IRQ"]
79pub type OTG_ID_CHG_IRQ_R = crate::BitReader;
80#[doc = "Field `OTG_ID_CHG_IRQ` writer - OTG ID change IRQ"]
81pub type OTG_ID_CHG_IRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
82#[doc = "Field `ENOTGIDDETECT` reader - Enable internal OTG ID detector"]
83pub type ENOTGIDDETECT_R = crate::BitReader<ENOTGIDDETECT_A>;
84#[doc = "Enable internal OTG ID detector\n\nValue on reset: 0"]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86pub enum ENOTGIDDETECT_A {
87    #[doc = "0: Disable the PHY's internal ID pin detection circuit"]
88    ID_DET_DISABLE = 0,
89    #[doc = "1: Enable the PHY's internal ID pin detection circuit"]
90    ID_DET_ENABLE = 1,
91}
92impl From<ENOTGIDDETECT_A> for bool {
93    #[inline(always)]
94    fn from(variant: ENOTGIDDETECT_A) -> Self {
95        variant as u8 != 0
96    }
97}
98impl ENOTGIDDETECT_R {
99    #[doc = "Get enumerated values variant"]
100    #[inline(always)]
101    pub const fn variant(&self) -> ENOTGIDDETECT_A {
102        match self.bits {
103            false => ENOTGIDDETECT_A::ID_DET_DISABLE,
104            true => ENOTGIDDETECT_A::ID_DET_ENABLE,
105        }
106    }
107    #[doc = "Disable the PHY's internal ID pin detection circuit"]
108    #[inline(always)]
109    pub fn is_id_det_disable(&self) -> bool {
110        *self == ENOTGIDDETECT_A::ID_DET_DISABLE
111    }
112    #[doc = "Enable the PHY's internal ID pin detection circuit"]
113    #[inline(always)]
114    pub fn is_id_det_enable(&self) -> bool {
115        *self == ENOTGIDDETECT_A::ID_DET_ENABLE
116    }
117}
118#[doc = "Field `ENOTGIDDETECT` writer - Enable internal OTG ID detector"]
119pub type ENOTGIDDETECT_W<'a, REG> = crate::BitWriter<'a, REG, ENOTGIDDETECT_A>;
120impl<'a, REG> ENOTGIDDETECT_W<'a, REG>
121where
122    REG: crate::Writable + crate::RegisterSpec,
123{
124    #[doc = "Disable the PHY's internal ID pin detection circuit"]
125    #[inline(always)]
126    pub fn id_det_disable(self) -> &'a mut crate::W<REG> {
127        self.variant(ENOTGIDDETECT_A::ID_DET_DISABLE)
128    }
129    #[doc = "Enable the PHY's internal ID pin detection circuit"]
130    #[inline(always)]
131    pub fn id_det_enable(self) -> &'a mut crate::W<REG> {
132        self.variant(ENOTGIDDETECT_A::ID_DET_ENABLE)
133    }
134}
135#[doc = "Field `RESUMEIRQSTICKY` reader - Resume IRQ"]
136pub type RESUMEIRQSTICKY_R = crate::BitReader;
137#[doc = "Field `RESUMEIRQSTICKY` writer - Resume IRQ"]
138pub type RESUMEIRQSTICKY_W<'a, REG> = crate::BitWriter<'a, REG>;
139#[doc = "Field `ENIRQRESUMEDETECT` reader - Enable IRQ Resume detect"]
140pub type ENIRQRESUMEDETECT_R = crate::BitReader;
141#[doc = "Field `ENIRQRESUMEDETECT` writer - Enable IRQ Resume detect"]
142pub type ENIRQRESUMEDETECT_W<'a, REG> = crate::BitWriter<'a, REG>;
143#[doc = "Field `RESUME_IRQ` reader - Resume IRQ"]
144pub type RESUME_IRQ_R = crate::BitReader;
145#[doc = "Field `RESUME_IRQ` writer - Resume IRQ"]
146pub type RESUME_IRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
147#[doc = "Field `ENIRQDEVPLUGIN` reader - Enable IRQ for non-standard resistive plugged-in detection"]
148pub type ENIRQDEVPLUGIN_R = crate::BitReader;
149#[doc = "Field `ENIRQDEVPLUGIN` writer - Enable IRQ for non-standard resistive plugged-in detection"]
150pub type ENIRQDEVPLUGIN_W<'a, REG> = crate::BitWriter<'a, REG>;
151#[doc = "Field `DEVPLUGIN_IRQ` reader - Device connected indicator for non-standard resistive plugged-in detection"]
152pub type DEVPLUGIN_IRQ_R = crate::BitReader;
153#[doc = "Field `DEVPLUGIN_IRQ` writer - Device connected indicator for non-standard resistive plugged-in detection"]
154pub type DEVPLUGIN_IRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
155#[doc = "Field `DATA_ON_LRADC` reader - APB clock switch option"]
156pub type DATA_ON_LRADC_R = crate::BitReader;
157#[doc = "Field `DATA_ON_LRADC` writer - APB clock switch option"]
158pub type DATA_ON_LRADC_W<'a, REG> = crate::BitWriter<'a, REG>;
159#[doc = "Field `ENUTMILEVEL2` reader - Enable level 2 operation"]
160pub type ENUTMILEVEL2_R = crate::BitReader;
161#[doc = "Field `ENUTMILEVEL2` writer - Enable level 2 operation"]
162pub type ENUTMILEVEL2_W<'a, REG> = crate::BitWriter<'a, REG>;
163#[doc = "Field `ENUTMILEVEL3` reader - Enable level 3 operation"]
164pub type ENUTMILEVEL3_R = crate::BitReader;
165#[doc = "Field `ENUTMILEVEL3` writer - Enable level 3 operation"]
166pub type ENUTMILEVEL3_W<'a, REG> = crate::BitWriter<'a, REG>;
167#[doc = "Field `ENIRQWAKEUP` reader - Enable Wakeup IRQ"]
168pub type ENIRQWAKEUP_R = crate::BitReader;
169#[doc = "Field `ENIRQWAKEUP` writer - Enable Wakeup IRQ"]
170pub type ENIRQWAKEUP_W<'a, REG> = crate::BitWriter<'a, REG>;
171#[doc = "Field `WAKEUP_IRQ` reader - Wakeup IRQ"]
172pub type WAKEUP_IRQ_R = crate::BitReader;
173#[doc = "Field `WAKEUP_IRQ` writer - Wakeup IRQ"]
174pub type WAKEUP_IRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
175#[doc = "Field `AUTORESUME_EN` reader - Enable autoresume"]
176pub type AUTORESUME_EN_R = crate::BitReader;
177#[doc = "Field `AUTORESUME_EN` writer - Enable autoresume"]
178pub type AUTORESUME_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
179#[doc = "Field `ENAUTOCLR_CLKGATE` reader - Autoclear clock gate"]
180pub type ENAUTOCLR_CLKGATE_R = crate::BitReader;
181#[doc = "Field `ENAUTOCLR_CLKGATE` writer - Autoclear clock gate"]
182pub type ENAUTOCLR_CLKGATE_W<'a, REG> = crate::BitWriter<'a, REG>;
183#[doc = "Field `ENAUTOCLR_PHY_PWD` reader - Autoclear PWD register bits"]
184pub type ENAUTOCLR_PHY_PWD_R = crate::BitReader;
185#[doc = "Field `ENAUTOCLR_PHY_PWD` writer - Autoclear PWD register bits"]
186pub type ENAUTOCLR_PHY_PWD_W<'a, REG> = crate::BitWriter<'a, REG>;
187#[doc = "Field `OTG_ID_VALUE` reader - ID value"]
188pub type OTG_ID_VALUE_R = crate::BitReader<OTG_ID_VALUE_A>;
189#[doc = "ID value\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum OTG_ID_VALUE_A {
192    #[doc = "0: False, when ID resistance to ground is less than Ra_Plug_ID, indicating Host (A) side"]
193    ID_HOST = 0,
194    #[doc = "1: True, when ID resistance is greater than Rb_Plug_ID, indicating Device (B) side"]
195    ID_DEVICE = 1,
196}
197impl From<OTG_ID_VALUE_A> for bool {
198    #[inline(always)]
199    fn from(variant: OTG_ID_VALUE_A) -> Self {
200        variant as u8 != 0
201    }
202}
203impl OTG_ID_VALUE_R {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub const fn variant(&self) -> OTG_ID_VALUE_A {
207        match self.bits {
208            false => OTG_ID_VALUE_A::ID_HOST,
209            true => OTG_ID_VALUE_A::ID_DEVICE,
210        }
211    }
212    #[doc = "False, when ID resistance to ground is less than Ra_Plug_ID, indicating Host (A) side"]
213    #[inline(always)]
214    pub fn is_id_host(&self) -> bool {
215        *self == OTG_ID_VALUE_A::ID_HOST
216    }
217    #[doc = "True, when ID resistance is greater than Rb_Plug_ID, indicating Device (B) side"]
218    #[inline(always)]
219    pub fn is_id_device(&self) -> bool {
220        *self == OTG_ID_VALUE_A::ID_DEVICE
221    }
222}
223#[doc = "Field `UTMI_SUSPENDM` reader - UTMI Suspend"]
224pub type UTMI_SUSPENDM_R = crate::BitReader;
225#[doc = "Field `CLKGATE` reader - UTMI clock gate"]
226pub type CLKGATE_R = crate::BitReader;
227#[doc = "Field `CLKGATE` writer - UTMI clock gate"]
228pub type CLKGATE_W<'a, REG> = crate::BitWriter<'a, REG>;
229#[doc = "Field `SFTRST` reader - Software reset"]
230pub type SFTRST_R = crate::BitReader;
231#[doc = "Field `SFTRST` writer - Software reset"]
232pub type SFTRST_W<'a, REG> = crate::BitWriter<'a, REG>;
233impl R {
234    #[doc = "Bit 0 - EN ID change IRQ"]
235    #[inline(always)]
236    pub fn enotg_id_chg_irq(&self) -> ENOTG_ID_CHG_IRQ_R {
237        ENOTG_ID_CHG_IRQ_R::new((self.bits & 1) != 0)
238    }
239    #[doc = "Bit 1 - Disconnect detect"]
240    #[inline(always)]
241    pub fn enhostdiscondetect(&self) -> ENHOSTDISCONDETECT_R {
242        ENHOSTDISCONDETECT_R::new(((self.bits >> 1) & 1) != 0)
243    }
244    #[doc = "Bit 2 - Enable IRQ for Host disconnect"]
245    #[inline(always)]
246    pub fn enirqhostdiscon(&self) -> ENIRQHOSTDISCON_R {
247        ENIRQHOSTDISCON_R::new(((self.bits >> 2) & 1) != 0)
248    }
249    #[doc = "Bit 3 - Device disconnect indication"]
250    #[inline(always)]
251    pub fn hostdiscondetect_irq(&self) -> HOSTDISCONDETECT_IRQ_R {
252        HOSTDISCONDETECT_IRQ_R::new(((self.bits >> 3) & 1) != 0)
253    }
254    #[doc = "Bit 4 - Enables non-standard resistive plugged-in detection"]
255    #[inline(always)]
256    pub fn endevplugindetect(&self) -> ENDEVPLUGINDETECT_R {
257        ENDEVPLUGINDETECT_R::new(((self.bits >> 4) & 1) != 0)
258    }
259    #[doc = "Bit 5 - Device plugin polarity interrupt configuration for non-standard resistive plugged-in detection"]
260    #[inline(always)]
261    pub fn devplugin_polarity(&self) -> DEVPLUGIN_POLARITY_R {
262        DEVPLUGIN_POLARITY_R::new(((self.bits >> 5) & 1) != 0)
263    }
264    #[doc = "Bit 6 - OTG ID change IRQ"]
265    #[inline(always)]
266    pub fn otg_id_chg_irq(&self) -> OTG_ID_CHG_IRQ_R {
267        OTG_ID_CHG_IRQ_R::new(((self.bits >> 6) & 1) != 0)
268    }
269    #[doc = "Bit 7 - Enable internal OTG ID detector"]
270    #[inline(always)]
271    pub fn enotgiddetect(&self) -> ENOTGIDDETECT_R {
272        ENOTGIDDETECT_R::new(((self.bits >> 7) & 1) != 0)
273    }
274    #[doc = "Bit 8 - Resume IRQ"]
275    #[inline(always)]
276    pub fn resumeirqsticky(&self) -> RESUMEIRQSTICKY_R {
277        RESUMEIRQSTICKY_R::new(((self.bits >> 8) & 1) != 0)
278    }
279    #[doc = "Bit 9 - Enable IRQ Resume detect"]
280    #[inline(always)]
281    pub fn enirqresumedetect(&self) -> ENIRQRESUMEDETECT_R {
282        ENIRQRESUMEDETECT_R::new(((self.bits >> 9) & 1) != 0)
283    }
284    #[doc = "Bit 10 - Resume IRQ"]
285    #[inline(always)]
286    pub fn resume_irq(&self) -> RESUME_IRQ_R {
287        RESUME_IRQ_R::new(((self.bits >> 10) & 1) != 0)
288    }
289    #[doc = "Bit 11 - Enable IRQ for non-standard resistive plugged-in detection"]
290    #[inline(always)]
291    pub fn enirqdevplugin(&self) -> ENIRQDEVPLUGIN_R {
292        ENIRQDEVPLUGIN_R::new(((self.bits >> 11) & 1) != 0)
293    }
294    #[doc = "Bit 12 - Device connected indicator for non-standard resistive plugged-in detection"]
295    #[inline(always)]
296    pub fn devplugin_irq(&self) -> DEVPLUGIN_IRQ_R {
297        DEVPLUGIN_IRQ_R::new(((self.bits >> 12) & 1) != 0)
298    }
299    #[doc = "Bit 13 - APB clock switch option"]
300    #[inline(always)]
301    pub fn data_on_lradc(&self) -> DATA_ON_LRADC_R {
302        DATA_ON_LRADC_R::new(((self.bits >> 13) & 1) != 0)
303    }
304    #[doc = "Bit 14 - Enable level 2 operation"]
305    #[inline(always)]
306    pub fn enutmilevel2(&self) -> ENUTMILEVEL2_R {
307        ENUTMILEVEL2_R::new(((self.bits >> 14) & 1) != 0)
308    }
309    #[doc = "Bit 15 - Enable level 3 operation"]
310    #[inline(always)]
311    pub fn enutmilevel3(&self) -> ENUTMILEVEL3_R {
312        ENUTMILEVEL3_R::new(((self.bits >> 15) & 1) != 0)
313    }
314    #[doc = "Bit 16 - Enable Wakeup IRQ"]
315    #[inline(always)]
316    pub fn enirqwakeup(&self) -> ENIRQWAKEUP_R {
317        ENIRQWAKEUP_R::new(((self.bits >> 16) & 1) != 0)
318    }
319    #[doc = "Bit 17 - Wakeup IRQ"]
320    #[inline(always)]
321    pub fn wakeup_irq(&self) -> WAKEUP_IRQ_R {
322        WAKEUP_IRQ_R::new(((self.bits >> 17) & 1) != 0)
323    }
324    #[doc = "Bit 18 - Enable autoresume"]
325    #[inline(always)]
326    pub fn autoresume_en(&self) -> AUTORESUME_EN_R {
327        AUTORESUME_EN_R::new(((self.bits >> 18) & 1) != 0)
328    }
329    #[doc = "Bit 19 - Autoclear clock gate"]
330    #[inline(always)]
331    pub fn enautoclr_clkgate(&self) -> ENAUTOCLR_CLKGATE_R {
332        ENAUTOCLR_CLKGATE_R::new(((self.bits >> 19) & 1) != 0)
333    }
334    #[doc = "Bit 20 - Autoclear PWD register bits"]
335    #[inline(always)]
336    pub fn enautoclr_phy_pwd(&self) -> ENAUTOCLR_PHY_PWD_R {
337        ENAUTOCLR_PHY_PWD_R::new(((self.bits >> 20) & 1) != 0)
338    }
339    #[doc = "Bit 27 - ID value"]
340    #[inline(always)]
341    pub fn otg_id_value(&self) -> OTG_ID_VALUE_R {
342        OTG_ID_VALUE_R::new(((self.bits >> 27) & 1) != 0)
343    }
344    #[doc = "Bit 29 - UTMI Suspend"]
345    #[inline(always)]
346    pub fn utmi_suspendm(&self) -> UTMI_SUSPENDM_R {
347        UTMI_SUSPENDM_R::new(((self.bits >> 29) & 1) != 0)
348    }
349    #[doc = "Bit 30 - UTMI clock gate"]
350    #[inline(always)]
351    pub fn clkgate(&self) -> CLKGATE_R {
352        CLKGATE_R::new(((self.bits >> 30) & 1) != 0)
353    }
354    #[doc = "Bit 31 - Software reset"]
355    #[inline(always)]
356    pub fn sftrst(&self) -> SFTRST_R {
357        SFTRST_R::new(((self.bits >> 31) & 1) != 0)
358    }
359}
360impl W {
361    #[doc = "Bit 0 - EN ID change IRQ"]
362    #[inline(always)]
363    #[must_use]
364    pub fn enotg_id_chg_irq(&mut self) -> ENOTG_ID_CHG_IRQ_W<CTRL_SPEC> {
365        ENOTG_ID_CHG_IRQ_W::new(self, 0)
366    }
367    #[doc = "Bit 1 - Disconnect detect"]
368    #[inline(always)]
369    #[must_use]
370    pub fn enhostdiscondetect(&mut self) -> ENHOSTDISCONDETECT_W<CTRL_SPEC> {
371        ENHOSTDISCONDETECT_W::new(self, 1)
372    }
373    #[doc = "Bit 2 - Enable IRQ for Host disconnect"]
374    #[inline(always)]
375    #[must_use]
376    pub fn enirqhostdiscon(&mut self) -> ENIRQHOSTDISCON_W<CTRL_SPEC> {
377        ENIRQHOSTDISCON_W::new(self, 2)
378    }
379    #[doc = "Bit 3 - Device disconnect indication"]
380    #[inline(always)]
381    #[must_use]
382    pub fn hostdiscondetect_irq(&mut self) -> HOSTDISCONDETECT_IRQ_W<CTRL_SPEC> {
383        HOSTDISCONDETECT_IRQ_W::new(self, 3)
384    }
385    #[doc = "Bit 4 - Enables non-standard resistive plugged-in detection"]
386    #[inline(always)]
387    #[must_use]
388    pub fn endevplugindetect(&mut self) -> ENDEVPLUGINDETECT_W<CTRL_SPEC> {
389        ENDEVPLUGINDETECT_W::new(self, 4)
390    }
391    #[doc = "Bit 5 - Device plugin polarity interrupt configuration for non-standard resistive plugged-in detection"]
392    #[inline(always)]
393    #[must_use]
394    pub fn devplugin_polarity(&mut self) -> DEVPLUGIN_POLARITY_W<CTRL_SPEC> {
395        DEVPLUGIN_POLARITY_W::new(self, 5)
396    }
397    #[doc = "Bit 6 - OTG ID change IRQ"]
398    #[inline(always)]
399    #[must_use]
400    pub fn otg_id_chg_irq(&mut self) -> OTG_ID_CHG_IRQ_W<CTRL_SPEC> {
401        OTG_ID_CHG_IRQ_W::new(self, 6)
402    }
403    #[doc = "Bit 7 - Enable internal OTG ID detector"]
404    #[inline(always)]
405    #[must_use]
406    pub fn enotgiddetect(&mut self) -> ENOTGIDDETECT_W<CTRL_SPEC> {
407        ENOTGIDDETECT_W::new(self, 7)
408    }
409    #[doc = "Bit 8 - Resume IRQ"]
410    #[inline(always)]
411    #[must_use]
412    pub fn resumeirqsticky(&mut self) -> RESUMEIRQSTICKY_W<CTRL_SPEC> {
413        RESUMEIRQSTICKY_W::new(self, 8)
414    }
415    #[doc = "Bit 9 - Enable IRQ Resume detect"]
416    #[inline(always)]
417    #[must_use]
418    pub fn enirqresumedetect(&mut self) -> ENIRQRESUMEDETECT_W<CTRL_SPEC> {
419        ENIRQRESUMEDETECT_W::new(self, 9)
420    }
421    #[doc = "Bit 10 - Resume IRQ"]
422    #[inline(always)]
423    #[must_use]
424    pub fn resume_irq(&mut self) -> RESUME_IRQ_W<CTRL_SPEC> {
425        RESUME_IRQ_W::new(self, 10)
426    }
427    #[doc = "Bit 11 - Enable IRQ for non-standard resistive plugged-in detection"]
428    #[inline(always)]
429    #[must_use]
430    pub fn enirqdevplugin(&mut self) -> ENIRQDEVPLUGIN_W<CTRL_SPEC> {
431        ENIRQDEVPLUGIN_W::new(self, 11)
432    }
433    #[doc = "Bit 12 - Device connected indicator for non-standard resistive plugged-in detection"]
434    #[inline(always)]
435    #[must_use]
436    pub fn devplugin_irq(&mut self) -> DEVPLUGIN_IRQ_W<CTRL_SPEC> {
437        DEVPLUGIN_IRQ_W::new(self, 12)
438    }
439    #[doc = "Bit 13 - APB clock switch option"]
440    #[inline(always)]
441    #[must_use]
442    pub fn data_on_lradc(&mut self) -> DATA_ON_LRADC_W<CTRL_SPEC> {
443        DATA_ON_LRADC_W::new(self, 13)
444    }
445    #[doc = "Bit 14 - Enable level 2 operation"]
446    #[inline(always)]
447    #[must_use]
448    pub fn enutmilevel2(&mut self) -> ENUTMILEVEL2_W<CTRL_SPEC> {
449        ENUTMILEVEL2_W::new(self, 14)
450    }
451    #[doc = "Bit 15 - Enable level 3 operation"]
452    #[inline(always)]
453    #[must_use]
454    pub fn enutmilevel3(&mut self) -> ENUTMILEVEL3_W<CTRL_SPEC> {
455        ENUTMILEVEL3_W::new(self, 15)
456    }
457    #[doc = "Bit 16 - Enable Wakeup IRQ"]
458    #[inline(always)]
459    #[must_use]
460    pub fn enirqwakeup(&mut self) -> ENIRQWAKEUP_W<CTRL_SPEC> {
461        ENIRQWAKEUP_W::new(self, 16)
462    }
463    #[doc = "Bit 17 - Wakeup IRQ"]
464    #[inline(always)]
465    #[must_use]
466    pub fn wakeup_irq(&mut self) -> WAKEUP_IRQ_W<CTRL_SPEC> {
467        WAKEUP_IRQ_W::new(self, 17)
468    }
469    #[doc = "Bit 18 - Enable autoresume"]
470    #[inline(always)]
471    #[must_use]
472    pub fn autoresume_en(&mut self) -> AUTORESUME_EN_W<CTRL_SPEC> {
473        AUTORESUME_EN_W::new(self, 18)
474    }
475    #[doc = "Bit 19 - Autoclear clock gate"]
476    #[inline(always)]
477    #[must_use]
478    pub fn enautoclr_clkgate(&mut self) -> ENAUTOCLR_CLKGATE_W<CTRL_SPEC> {
479        ENAUTOCLR_CLKGATE_W::new(self, 19)
480    }
481    #[doc = "Bit 20 - Autoclear PWD register bits"]
482    #[inline(always)]
483    #[must_use]
484    pub fn enautoclr_phy_pwd(&mut self) -> ENAUTOCLR_PHY_PWD_W<CTRL_SPEC> {
485        ENAUTOCLR_PHY_PWD_W::new(self, 20)
486    }
487    #[doc = "Bit 30 - UTMI clock gate"]
488    #[inline(always)]
489    #[must_use]
490    pub fn clkgate(&mut self) -> CLKGATE_W<CTRL_SPEC> {
491        CLKGATE_W::new(self, 30)
492    }
493    #[doc = "Bit 31 - Software reset"]
494    #[inline(always)]
495    #[must_use]
496    pub fn sftrst(&mut self) -> SFTRST_W<CTRL_SPEC> {
497        SFTRST_W::new(self, 31)
498    }
499    #[doc = r" Writes raw bits to the register."]
500    #[doc = r""]
501    #[doc = r" # Safety"]
502    #[doc = r""]
503    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
504    #[inline(always)]
505    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
506        self.bits = bits;
507        self
508    }
509}
510#[doc = "General Purpose Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
511pub struct CTRL_SPEC;
512impl crate::RegisterSpec for CTRL_SPEC {
513    type Ux = u32;
514}
515#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
516impl crate::Readable for CTRL_SPEC {}
517#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
518impl crate::Writable for CTRL_SPEC {
519    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
520    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
521}
522#[doc = "`reset()` method sets CTRL to value 0xc000_0000"]
523impl crate::Resettable for CTRL_SPEC {
524    const RESET_VALUE: u32 = 0xc000_0000;
525}
mcxn947_pac/usbphy/ctrl.rs

mcxn947_pac/usbphy/
ctrl.rs
