mcxn947_pac/syscon0/
ref_clk_ctrl.rs

1#[doc = "Register `REF_CLK_CTRL` reader"]
2pub type R = crate::R<REF_CLK_CTRL_SPEC>;
3#[doc = "Register `REF_CLK_CTRL` writer"]
4pub type W = crate::W<REF_CLK_CTRL_SPEC>;
5#[doc = "Field `GDET_REFCLK_EN` reader - GDET reference clock enable bit"]
6pub type GDET_REFCLK_EN_R = crate::BitReader<GDET_REFCLK_EN_A>;
7#[doc = "GDET reference clock enable bit\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum GDET_REFCLK_EN_A {
10    #[doc = "0: Disabled."]
11    DISABLE = 0,
12    #[doc = "1: Enabled"]
13    ENABLE = 1,
14}
15impl From<GDET_REFCLK_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: GDET_REFCLK_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl GDET_REFCLK_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> GDET_REFCLK_EN_A {
25        match self.bits {
26            false => GDET_REFCLK_EN_A::DISABLE,
27            true => GDET_REFCLK_EN_A::ENABLE,
28        }
29    }
30    #[doc = "Disabled."]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == GDET_REFCLK_EN_A::DISABLE
34    }
35    #[doc = "Enabled"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == GDET_REFCLK_EN_A::ENABLE
39    }
40}
41#[doc = "Field `GDET_REFCLK_EN` writer - GDET reference clock enable bit"]
42pub type GDET_REFCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG, GDET_REFCLK_EN_A>;
43impl<'a, REG> GDET_REFCLK_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disabled."]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(GDET_REFCLK_EN_A::DISABLE)
51    }
52    #[doc = "Enabled"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(GDET_REFCLK_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `TRNG_REFCLK_EN` reader - ELS TRNG reference clock enable bit"]
59pub type TRNG_REFCLK_EN_R = crate::BitReader<TRNG_REFCLK_EN_A>;
60#[doc = "ELS TRNG reference clock enable bit\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TRNG_REFCLK_EN_A {
63    #[doc = "0: Disabled."]
64    DISABLE = 0,
65    #[doc = "1: Enabled"]
66    ENABLE = 1,
67}
68impl From<TRNG_REFCLK_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: TRNG_REFCLK_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl TRNG_REFCLK_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> TRNG_REFCLK_EN_A {
78        match self.bits {
79            false => TRNG_REFCLK_EN_A::DISABLE,
80            true => TRNG_REFCLK_EN_A::ENABLE,
81        }
82    }
83    #[doc = "Disabled."]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == TRNG_REFCLK_EN_A::DISABLE
87    }
88    #[doc = "Enabled"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == TRNG_REFCLK_EN_A::ENABLE
92    }
93}
94#[doc = "Field `TRNG_REFCLK_EN` writer - ELS TRNG reference clock enable bit"]
95pub type TRNG_REFCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG, TRNG_REFCLK_EN_A>;
96impl<'a, REG> TRNG_REFCLK_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Disabled."]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(TRNG_REFCLK_EN_A::DISABLE)
104    }
105    #[doc = "Enabled"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(TRNG_REFCLK_EN_A::ENABLE)
109    }
110}
111impl R {
112    #[doc = "Bit 0 - GDET reference clock enable bit"]
113    #[inline(always)]
114    pub fn gdet_refclk_en(&self) -> GDET_REFCLK_EN_R {
115        GDET_REFCLK_EN_R::new((self.bits & 1) != 0)
116    }
117    #[doc = "Bit 1 - ELS TRNG reference clock enable bit"]
118    #[inline(always)]
119    pub fn trng_refclk_en(&self) -> TRNG_REFCLK_EN_R {
120        TRNG_REFCLK_EN_R::new(((self.bits >> 1) & 1) != 0)
121    }
122}
123impl W {
124    #[doc = "Bit 0 - GDET reference clock enable bit"]
125    #[inline(always)]
126    #[must_use]
127    pub fn gdet_refclk_en(&mut self) -> GDET_REFCLK_EN_W<REF_CLK_CTRL_SPEC> {
128        GDET_REFCLK_EN_W::new(self, 0)
129    }
130    #[doc = "Bit 1 - ELS TRNG reference clock enable bit"]
131    #[inline(always)]
132    #[must_use]
133    pub fn trng_refclk_en(&mut self) -> TRNG_REFCLK_EN_W<REF_CLK_CTRL_SPEC> {
134        TRNG_REFCLK_EN_W::new(self, 1)
135    }
136    #[doc = r" Writes raw bits to the register."]
137    #[doc = r""]
138    #[doc = r" # Safety"]
139    #[doc = r""]
140    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
141    #[inline(always)]
142    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
143        self.bits = bits;
144        self
145    }
146}
147#[doc = "FRO 48MHz Reference Clock Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ref_clk_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_clk_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
148pub struct REF_CLK_CTRL_SPEC;
149impl crate::RegisterSpec for REF_CLK_CTRL_SPEC {
150    type Ux = u32;
151}
152#[doc = "`read()` method returns [`ref_clk_ctrl::R`](R) reader structure"]
153impl crate::Readable for REF_CLK_CTRL_SPEC {}
154#[doc = "`write(|w| ..)` method takes [`ref_clk_ctrl::W`](W) writer structure"]
155impl crate::Writable for REF_CLK_CTRL_SPEC {
156    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
157    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
158}
159#[doc = "`reset()` method sets REF_CLK_CTRL to value 0"]
160impl crate::Resettable for REF_CLK_CTRL_SPEC {
161    const RESET_VALUE: u32 = 0;
162}
mcxn947_pac/syscon0/ref_clk_ctrl.rs

mcxn947_pac/syscon0/
ref_clk_ctrl.rs
