mcxa_pac/syscon/
pll1clkdiv.rs

1#[doc = "Register `PLL1CLKDIV` reader"]
2pub type R = crate::R<Pll1clkdivSpec>;
3#[doc = "Register `PLL1CLKDIV` writer"]
4pub type W = crate::W<Pll1clkdivSpec>;
5#[doc = "Field `DIV` reader - Clock divider value"]
6pub type DivR = crate::FieldReader;
7#[doc = "Field `DIV` writer - Clock divider value"]
8pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Resets the divider counter\n\nValue on reset: 0"]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12pub enum Reset {
13    #[doc = "0: Divider is not reset"]
14    Released = 0,
15    #[doc = "1: Divider is reset"]
16    Asserted = 1,
17}
18impl From<Reset> for bool {
19    #[inline(always)]
20    fn from(variant: Reset) -> Self {
21        variant as u8 != 0
22    }
23}
24#[doc = "Field `RESET` reader - Resets the divider counter"]
25pub type ResetR = crate::BitReader<Reset>;
26impl ResetR {
27    #[doc = "Get enumerated values variant"]
28    #[inline(always)]
29    pub const fn variant(&self) -> Reset {
30        match self.bits {
31            false => Reset::Released,
32            true => Reset::Asserted,
33        }
34    }
35    #[doc = "Divider is not reset"]
36    #[inline(always)]
37    pub fn is_released(&self) -> bool {
38        *self == Reset::Released
39    }
40    #[doc = "Divider is reset"]
41    #[inline(always)]
42    pub fn is_asserted(&self) -> bool {
43        *self == Reset::Asserted
44    }
45}
46#[doc = "Field `RESET` writer - Resets the divider counter"]
47pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>;
48impl<'a, REG> ResetW<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51{
52    #[doc = "Divider is not reset"]
53    #[inline(always)]
54    pub fn released(self) -> &'a mut crate::W<REG> {
55        self.variant(Reset::Released)
56    }
57    #[doc = "Divider is reset"]
58    #[inline(always)]
59    pub fn asserted(self) -> &'a mut crate::W<REG> {
60        self.variant(Reset::Asserted)
61    }
62}
63#[doc = "Halts the divider counter\n\nValue on reset: 1"]
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum Halt {
67    #[doc = "0: Divider clock is running"]
68    Run = 0,
69    #[doc = "1: Divider clock is stopped"]
70    Halt = 1,
71}
72impl From<Halt> for bool {
73    #[inline(always)]
74    fn from(variant: Halt) -> Self {
75        variant as u8 != 0
76    }
77}
78#[doc = "Field `HALT` reader - Halts the divider counter"]
79pub type HaltR = crate::BitReader<Halt>;
80impl HaltR {
81    #[doc = "Get enumerated values variant"]
82    #[inline(always)]
83    pub const fn variant(&self) -> Halt {
84        match self.bits {
85            false => Halt::Run,
86            true => Halt::Halt,
87        }
88    }
89    #[doc = "Divider clock is running"]
90    #[inline(always)]
91    pub fn is_run(&self) -> bool {
92        *self == Halt::Run
93    }
94    #[doc = "Divider clock is stopped"]
95    #[inline(always)]
96    pub fn is_halt(&self) -> bool {
97        *self == Halt::Halt
98    }
99}
100#[doc = "Field `HALT` writer - Halts the divider counter"]
101pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>;
102impl<'a, REG> HaltW<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    #[doc = "Divider clock is running"]
107    #[inline(always)]
108    pub fn run(self) -> &'a mut crate::W<REG> {
109        self.variant(Halt::Run)
110    }
111    #[doc = "Divider clock is stopped"]
112    #[inline(always)]
113    pub fn halt(self) -> &'a mut crate::W<REG> {
114        self.variant(Halt::Halt)
115    }
116}
117#[doc = "Divider status flag\n\nValue on reset: 0"]
118#[cfg_attr(feature = "defmt", derive(defmt::Format))]
119#[derive(Clone, Copy, Debug, PartialEq, Eq)]
120pub enum Unstab {
121    #[doc = "0: Divider clock is stable"]
122    Stable = 0,
123    #[doc = "1: Clock frequency is not stable"]
124    Ongoing = 1,
125}
126impl From<Unstab> for bool {
127    #[inline(always)]
128    fn from(variant: Unstab) -> Self {
129        variant as u8 != 0
130    }
131}
132#[doc = "Field `UNSTAB` reader - Divider status flag"]
133pub type UnstabR = crate::BitReader<Unstab>;
134impl UnstabR {
135    #[doc = "Get enumerated values variant"]
136    #[inline(always)]
137    pub const fn variant(&self) -> Unstab {
138        match self.bits {
139            false => Unstab::Stable,
140            true => Unstab::Ongoing,
141        }
142    }
143    #[doc = "Divider clock is stable"]
144    #[inline(always)]
145    pub fn is_stable(&self) -> bool {
146        *self == Unstab::Stable
147    }
148    #[doc = "Clock frequency is not stable"]
149    #[inline(always)]
150    pub fn is_ongoing(&self) -> bool {
151        *self == Unstab::Ongoing
152    }
153}
154impl R {
155    #[doc = "Bits 0:7 - Clock divider value"]
156    #[inline(always)]
157    pub fn div(&self) -> DivR {
158        DivR::new((self.bits & 0xff) as u8)
159    }
160    #[doc = "Bit 29 - Resets the divider counter"]
161    #[inline(always)]
162    pub fn reset(&self) -> ResetR {
163        ResetR::new(((self.bits >> 29) & 1) != 0)
164    }
165    #[doc = "Bit 30 - Halts the divider counter"]
166    #[inline(always)]
167    pub fn halt(&self) -> HaltR {
168        HaltR::new(((self.bits >> 30) & 1) != 0)
169    }
170    #[doc = "Bit 31 - Divider status flag"]
171    #[inline(always)]
172    pub fn unstab(&self) -> UnstabR {
173        UnstabR::new(((self.bits >> 31) & 1) != 0)
174    }
175}
176#[cfg(feature = "debug")]
177impl core::fmt::Debug for R {
178    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
179        f.debug_struct("PLL1CLKDIV")
180            .field("div", &self.div())
181            .field("reset", &self.reset())
182            .field("halt", &self.halt())
183            .field("unstab", &self.unstab())
184            .finish()
185    }
186}
187impl W {
188    #[doc = "Bits 0:7 - Clock divider value"]
189    #[inline(always)]
190    pub fn div(&mut self) -> DivW<'_, Pll1clkdivSpec> {
191        DivW::new(self, 0)
192    }
193    #[doc = "Bit 29 - Resets the divider counter"]
194    #[inline(always)]
195    pub fn reset(&mut self) -> ResetW<'_, Pll1clkdivSpec> {
196        ResetW::new(self, 29)
197    }
198    #[doc = "Bit 30 - Halts the divider counter"]
199    #[inline(always)]
200    pub fn halt(&mut self) -> HaltW<'_, Pll1clkdivSpec> {
201        HaltW::new(self, 30)
202    }
203}
204#[doc = "PLL1_CLK_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`pll1clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pll1clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
205pub struct Pll1clkdivSpec;
206impl crate::RegisterSpec for Pll1clkdivSpec {
207    type Ux = u32;
208}
209#[doc = "`read()` method returns [`pll1clkdiv::R`](R) reader structure"]
210impl crate::Readable for Pll1clkdivSpec {}
211#[doc = "`write(|w| ..)` method takes [`pll1clkdiv::W`](W) writer structure"]
212impl crate::Writable for Pll1clkdivSpec {
213    type Safety = crate::Unsafe;
214}
215#[doc = "`reset()` method sets PLL1CLKDIV to value 0x4000_0000"]
216impl crate::Resettable for Pll1clkdivSpec {
217    const RESET_VALUE: u32 = 0x4000_0000;
218}
mcxa_pac/syscon/pll1clkdiv.rs

mcxa_pac/syscon/
pll1clkdiv.rs
