mcxa_pac/scg0/
spllstat.rs

1#[doc = "Register `SPLLSTAT` reader"]
2pub type R = crate::R<SpllstatSpec>;
3#[doc = "Pre-divider (N) ratio change acknowledge\n\nValue on reset: 0"]
4#[cfg_attr(feature = "defmt", derive(defmt::Format))]
5#[derive(Clone, Copy, Debug, PartialEq, Eq)]
6pub enum Ndivack {
7    #[doc = "0: The Pre-divider (N) ratio change is not accepted by the analog PLL."]
8    Disabled = 0,
9    #[doc = "1: The Pre-divider (N) ratio change is accepted by the analog PLL."]
10    Enabled = 1,
11}
12impl From<Ndivack> for bool {
13    #[inline(always)]
14    fn from(variant: Ndivack) -> Self {
15        variant as u8 != 0
16    }
17}
18#[doc = "Field `NDIVACK` reader - Pre-divider (N) ratio change acknowledge"]
19pub type NdivackR = crate::BitReader<Ndivack>;
20impl NdivackR {
21    #[doc = "Get enumerated values variant"]
22    #[inline(always)]
23    pub const fn variant(&self) -> Ndivack {
24        match self.bits {
25            false => Ndivack::Disabled,
26            true => Ndivack::Enabled,
27        }
28    }
29    #[doc = "The Pre-divider (N) ratio change is not accepted by the analog PLL."]
30    #[inline(always)]
31    pub fn is_disabled(&self) -> bool {
32        *self == Ndivack::Disabled
33    }
34    #[doc = "The Pre-divider (N) ratio change is accepted by the analog PLL."]
35    #[inline(always)]
36    pub fn is_enabled(&self) -> bool {
37        *self == Ndivack::Enabled
38    }
39}
40#[doc = "Feedback (M) divider ratio change acknowledge\n\nValue on reset: 0"]
41#[cfg_attr(feature = "defmt", derive(defmt::Format))]
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum Mdivack {
44    #[doc = "0: The Feedback (M) ratio change is not accepted by the analog PLL."]
45    Disabled = 0,
46    #[doc = "1: The Feedback (M) ratio change is accepted by the analog PLL."]
47    Enabled = 1,
48}
49impl From<Mdivack> for bool {
50    #[inline(always)]
51    fn from(variant: Mdivack) -> Self {
52        variant as u8 != 0
53    }
54}
55#[doc = "Field `MDIVACK` reader - Feedback (M) divider ratio change acknowledge"]
56pub type MdivackR = crate::BitReader<Mdivack>;
57impl MdivackR {
58    #[doc = "Get enumerated values variant"]
59    #[inline(always)]
60    pub const fn variant(&self) -> Mdivack {
61        match self.bits {
62            false => Mdivack::Disabled,
63            true => Mdivack::Enabled,
64        }
65    }
66    #[doc = "The Feedback (M) ratio change is not accepted by the analog PLL."]
67    #[inline(always)]
68    pub fn is_disabled(&self) -> bool {
69        *self == Mdivack::Disabled
70    }
71    #[doc = "The Feedback (M) ratio change is accepted by the analog PLL."]
72    #[inline(always)]
73    pub fn is_enabled(&self) -> bool {
74        *self == Mdivack::Enabled
75    }
76}
77#[doc = "Post-divider (P) ratio change acknowledge\n\nValue on reset: 0"]
78#[cfg_attr(feature = "defmt", derive(defmt::Format))]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80pub enum Pdivack {
81    #[doc = "0: The Post-divider (P) ratio change is not accepted by the analog PLL"]
82    Disabled = 0,
83    #[doc = "1: The Post-divider (P) ratio change is accepted by the analog PLL"]
84    Enabled = 1,
85}
86impl From<Pdivack> for bool {
87    #[inline(always)]
88    fn from(variant: Pdivack) -> Self {
89        variant as u8 != 0
90    }
91}
92#[doc = "Field `PDIVACK` reader - Post-divider (P) ratio change acknowledge"]
93pub type PdivackR = crate::BitReader<Pdivack>;
94impl PdivackR {
95    #[doc = "Get enumerated values variant"]
96    #[inline(always)]
97    pub const fn variant(&self) -> Pdivack {
98        match self.bits {
99            false => Pdivack::Disabled,
100            true => Pdivack::Enabled,
101        }
102    }
103    #[doc = "The Post-divider (P) ratio change is not accepted by the analog PLL"]
104    #[inline(always)]
105    pub fn is_disabled(&self) -> bool {
106        *self == Pdivack::Disabled
107    }
108    #[doc = "The Post-divider (P) ratio change is accepted by the analog PLL"]
109    #[inline(always)]
110    pub fn is_enabled(&self) -> bool {
111        *self == Pdivack::Enabled
112    }
113}
114#[doc = "Free running detector (active high)\n\nValue on reset: 0"]
115#[cfg_attr(feature = "defmt", derive(defmt::Format))]
116#[derive(Clone, Copy, Debug, PartialEq, Eq)]
117pub enum Frmdet {
118    #[doc = "0: Free running is not detected"]
119    Disabled = 0,
120    #[doc = "1: Free running is detected"]
121    Enabled = 1,
122}
123impl From<Frmdet> for bool {
124    #[inline(always)]
125    fn from(variant: Frmdet) -> Self {
126        variant as u8 != 0
127    }
128}
129#[doc = "Field `FRMDET` reader - Free running detector (active high)"]
130pub type FrmdetR = crate::BitReader<Frmdet>;
131impl FrmdetR {
132    #[doc = "Get enumerated values variant"]
133    #[inline(always)]
134    pub const fn variant(&self) -> Frmdet {
135        match self.bits {
136            false => Frmdet::Disabled,
137            true => Frmdet::Enabled,
138        }
139    }
140    #[doc = "Free running is not detected"]
141    #[inline(always)]
142    pub fn is_disabled(&self) -> bool {
143        *self == Frmdet::Disabled
144    }
145    #[doc = "Free running is detected"]
146    #[inline(always)]
147    pub fn is_enabled(&self) -> bool {
148        *self == Frmdet::Enabled
149    }
150}
151impl R {
152    #[doc = "Bit 1 - Pre-divider (N) ratio change acknowledge"]
153    #[inline(always)]
154    pub fn ndivack(&self) -> NdivackR {
155        NdivackR::new(((self.bits >> 1) & 1) != 0)
156    }
157    #[doc = "Bit 2 - Feedback (M) divider ratio change acknowledge"]
158    #[inline(always)]
159    pub fn mdivack(&self) -> MdivackR {
160        MdivackR::new(((self.bits >> 2) & 1) != 0)
161    }
162    #[doc = "Bit 3 - Post-divider (P) ratio change acknowledge"]
163    #[inline(always)]
164    pub fn pdivack(&self) -> PdivackR {
165        PdivackR::new(((self.bits >> 3) & 1) != 0)
166    }
167    #[doc = "Bit 4 - Free running detector (active high)"]
168    #[inline(always)]
169    pub fn frmdet(&self) -> FrmdetR {
170        FrmdetR::new(((self.bits >> 4) & 1) != 0)
171    }
172}
173#[cfg(feature = "debug")]
174impl core::fmt::Debug for R {
175    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
176        f.debug_struct("SPLLSTAT")
177            .field("ndivack", &self.ndivack())
178            .field("mdivack", &self.mdivack())
179            .field("pdivack", &self.pdivack())
180            .field("frmdet", &self.frmdet())
181            .finish()
182    }
183}
184#[doc = "SPLL Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllstat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
185pub struct SpllstatSpec;
186impl crate::RegisterSpec for SpllstatSpec {
187    type Ux = u32;
188}
189#[doc = "`read()` method returns [`spllstat::R`](R) reader structure"]
190impl crate::Readable for SpllstatSpec {}
191#[doc = "`reset()` method sets SPLLSTAT to value 0"]
192impl crate::Resettable for SpllstatSpec {}
mcxa_pac/scg0/spllstat.rs

mcxa_pac/scg0/
spllstat.rs
