mcxa_pac/scg0/
firccsr.rs

1#[doc = "Register `FIRCCSR` reader"]
2pub type R = crate::R<FirccsrSpec>;
3#[doc = "Register `FIRCCSR` writer"]
4pub type W = crate::W<FirccsrSpec>;
5#[doc = "FIRC Enable\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Fircen {
9    #[doc = "0: FIRC is disabled"]
10    Disabled = 0,
11    #[doc = "1: FIRC is enabled"]
12    Enabled = 1,
13}
14impl From<Fircen> for bool {
15    #[inline(always)]
16    fn from(variant: Fircen) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `FIRCEN` reader - FIRC Enable"]
21pub type FircenR = crate::BitReader<Fircen>;
22impl FircenR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Fircen {
26        match self.bits {
27            false => Fircen::Disabled,
28            true => Fircen::Enabled,
29        }
30    }
31    #[doc = "FIRC is disabled"]
32    #[inline(always)]
33    pub fn is_disabled(&self) -> bool {
34        *self == Fircen::Disabled
35    }
36    #[doc = "FIRC is enabled"]
37    #[inline(always)]
38    pub fn is_enabled(&self) -> bool {
39        *self == Fircen::Enabled
40    }
41}
42#[doc = "Field `FIRCEN` writer - FIRC Enable"]
43pub type FircenW<'a, REG> = crate::BitWriter<'a, REG, Fircen>;
44impl<'a, REG> FircenW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "FIRC is disabled"]
49    #[inline(always)]
50    pub fn disabled(self) -> &'a mut crate::W<REG> {
51        self.variant(Fircen::Disabled)
52    }
53    #[doc = "FIRC is enabled"]
54    #[inline(always)]
55    pub fn enabled(self) -> &'a mut crate::W<REG> {
56        self.variant(Fircen::Enabled)
57    }
58}
59#[doc = "FIRC Stop Enable\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Fircsten {
63    #[doc = "0: FIRC is disabled in Deep Sleep mode"]
64    DisabledInStopModes = 0,
65    #[doc = "1: FIRC is enabled in Deep Sleep mode"]
66    EnabledInStopModes = 1,
67}
68impl From<Fircsten> for bool {
69    #[inline(always)]
70    fn from(variant: Fircsten) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `FIRCSTEN` reader - FIRC Stop Enable"]
75pub type FircstenR = crate::BitReader<Fircsten>;
76impl FircstenR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Fircsten {
80        match self.bits {
81            false => Fircsten::DisabledInStopModes,
82            true => Fircsten::EnabledInStopModes,
83        }
84    }
85    #[doc = "FIRC is disabled in Deep Sleep mode"]
86    #[inline(always)]
87    pub fn is_disabled_in_stop_modes(&self) -> bool {
88        *self == Fircsten::DisabledInStopModes
89    }
90    #[doc = "FIRC is enabled in Deep Sleep mode"]
91    #[inline(always)]
92    pub fn is_enabled_in_stop_modes(&self) -> bool {
93        *self == Fircsten::EnabledInStopModes
94    }
95}
96#[doc = "Field `FIRCSTEN` writer - FIRC Stop Enable"]
97pub type FircstenW<'a, REG> = crate::BitWriter<'a, REG, Fircsten>;
98impl<'a, REG> FircstenW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "FIRC is disabled in Deep Sleep mode"]
103    #[inline(always)]
104    pub fn disabled_in_stop_modes(self) -> &'a mut crate::W<REG> {
105        self.variant(Fircsten::DisabledInStopModes)
106    }
107    #[doc = "FIRC is enabled in Deep Sleep mode"]
108    #[inline(always)]
109    pub fn enabled_in_stop_modes(self) -> &'a mut crate::W<REG> {
110        self.variant(Fircsten::EnabledInStopModes)
111    }
112}
113#[doc = "FIRC 45 MHz Clock to peripherals Enable\n\nValue on reset: 1"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum FircSclkPeriphEn {
117    #[doc = "0: FIRC 45 MHz to peripherals is disabled"]
118    Disabled = 0,
119    #[doc = "1: FIRC 45 MHz to peripherals is enabled"]
120    Enabled = 1,
121}
122impl From<FircSclkPeriphEn> for bool {
123    #[inline(always)]
124    fn from(variant: FircSclkPeriphEn) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `FIRC_SCLK_PERIPH_EN` reader - FIRC 45 MHz Clock to peripherals Enable"]
129pub type FircSclkPeriphEnR = crate::BitReader<FircSclkPeriphEn>;
130impl FircSclkPeriphEnR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> FircSclkPeriphEn {
134        match self.bits {
135            false => FircSclkPeriphEn::Disabled,
136            true => FircSclkPeriphEn::Enabled,
137        }
138    }
139    #[doc = "FIRC 45 MHz to peripherals is disabled"]
140    #[inline(always)]
141    pub fn is_disabled(&self) -> bool {
142        *self == FircSclkPeriphEn::Disabled
143    }
144    #[doc = "FIRC 45 MHz to peripherals is enabled"]
145    #[inline(always)]
146    pub fn is_enabled(&self) -> bool {
147        *self == FircSclkPeriphEn::Enabled
148    }
149}
150#[doc = "Field `FIRC_SCLK_PERIPH_EN` writer - FIRC 45 MHz Clock to peripherals Enable"]
151pub type FircSclkPeriphEnW<'a, REG> = crate::BitWriter<'a, REG, FircSclkPeriphEn>;
152impl<'a, REG> FircSclkPeriphEnW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "FIRC 45 MHz to peripherals is disabled"]
157    #[inline(always)]
158    pub fn disabled(self) -> &'a mut crate::W<REG> {
159        self.variant(FircSclkPeriphEn::Disabled)
160    }
161    #[doc = "FIRC 45 MHz to peripherals is enabled"]
162    #[inline(always)]
163    pub fn enabled(self) -> &'a mut crate::W<REG> {
164        self.variant(FircSclkPeriphEn::Enabled)
165    }
166}
167#[doc = "FRO_HF Clock to peripherals Enable\n\nValue on reset: 1"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum FircFclkPeriphEn {
171    #[doc = "0: FRO_HF to peripherals is disabled"]
172    Disabled = 0,
173    #[doc = "1: FRO_HF to peripherals is enabled"]
174    Enabled = 1,
175}
176impl From<FircFclkPeriphEn> for bool {
177    #[inline(always)]
178    fn from(variant: FircFclkPeriphEn) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `FIRC_FCLK_PERIPH_EN` reader - FRO_HF Clock to peripherals Enable"]
183pub type FircFclkPeriphEnR = crate::BitReader<FircFclkPeriphEn>;
184impl FircFclkPeriphEnR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> FircFclkPeriphEn {
188        match self.bits {
189            false => FircFclkPeriphEn::Disabled,
190            true => FircFclkPeriphEn::Enabled,
191        }
192    }
193    #[doc = "FRO_HF to peripherals is disabled"]
194    #[inline(always)]
195    pub fn is_disabled(&self) -> bool {
196        *self == FircFclkPeriphEn::Disabled
197    }
198    #[doc = "FRO_HF to peripherals is enabled"]
199    #[inline(always)]
200    pub fn is_enabled(&self) -> bool {
201        *self == FircFclkPeriphEn::Enabled
202    }
203}
204#[doc = "Field `FIRC_FCLK_PERIPH_EN` writer - FRO_HF Clock to peripherals Enable"]
205pub type FircFclkPeriphEnW<'a, REG> = crate::BitWriter<'a, REG, FircFclkPeriphEn>;
206impl<'a, REG> FircFclkPeriphEnW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "FRO_HF to peripherals is disabled"]
211    #[inline(always)]
212    pub fn disabled(self) -> &'a mut crate::W<REG> {
213        self.variant(FircFclkPeriphEn::Disabled)
214    }
215    #[doc = "FRO_HF to peripherals is enabled"]
216    #[inline(always)]
217    pub fn enabled(self) -> &'a mut crate::W<REG> {
218        self.variant(FircFclkPeriphEn::Enabled)
219    }
220}
221#[doc = "Lock Register\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum Lk {
225    #[doc = "0: Control Status Register can be written"]
226    WriteEnabled = 0,
227    #[doc = "1: Control Status Register cannot be written"]
228    WriteDisabled = 1,
229}
230impl From<Lk> for bool {
231    #[inline(always)]
232    fn from(variant: Lk) -> Self {
233        variant as u8 != 0
234    }
235}
236#[doc = "Field `LK` reader - Lock Register"]
237pub type LkR = crate::BitReader<Lk>;
238impl LkR {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> Lk {
242        match self.bits {
243            false => Lk::WriteEnabled,
244            true => Lk::WriteDisabled,
245        }
246    }
247    #[doc = "Control Status Register can be written"]
248    #[inline(always)]
249    pub fn is_write_enabled(&self) -> bool {
250        *self == Lk::WriteEnabled
251    }
252    #[doc = "Control Status Register cannot be written"]
253    #[inline(always)]
254    pub fn is_write_disabled(&self) -> bool {
255        *self == Lk::WriteDisabled
256    }
257}
258#[doc = "Field `LK` writer - Lock Register"]
259pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>;
260impl<'a, REG> LkW<'a, REG>
261where
262    REG: crate::Writable + crate::RegisterSpec,
263{
264    #[doc = "Control Status Register can be written"]
265    #[inline(always)]
266    pub fn write_enabled(self) -> &'a mut crate::W<REG> {
267        self.variant(Lk::WriteEnabled)
268    }
269    #[doc = "Control Status Register cannot be written"]
270    #[inline(always)]
271    pub fn write_disabled(self) -> &'a mut crate::W<REG> {
272        self.variant(Lk::WriteDisabled)
273    }
274}
275#[doc = "FIRC Valid status\n\nValue on reset: 1"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum Fircvld {
279    #[doc = "0: FIRC is not enabled or clock is not valid."]
280    NotEnabledOrNotValid = 0,
281    #[doc = "1: FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog."]
282    EnabledAndValid = 1,
283}
284impl From<Fircvld> for bool {
285    #[inline(always)]
286    fn from(variant: Fircvld) -> Self {
287        variant as u8 != 0
288    }
289}
290#[doc = "Field `FIRCVLD` reader - FIRC Valid status"]
291pub type FircvldR = crate::BitReader<Fircvld>;
292impl FircvldR {
293    #[doc = "Get enumerated values variant"]
294    #[inline(always)]
295    pub const fn variant(&self) -> Fircvld {
296        match self.bits {
297            false => Fircvld::NotEnabledOrNotValid,
298            true => Fircvld::EnabledAndValid,
299        }
300    }
301    #[doc = "FIRC is not enabled or clock is not valid."]
302    #[inline(always)]
303    pub fn is_not_enabled_or_not_valid(&self) -> bool {
304        *self == Fircvld::NotEnabledOrNotValid
305    }
306    #[doc = "FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog."]
307    #[inline(always)]
308    pub fn is_enabled_and_valid(&self) -> bool {
309        *self == Fircvld::EnabledAndValid
310    }
311}
312#[doc = "FIRC Selected\n\nValue on reset: 1"]
313#[cfg_attr(feature = "defmt", derive(defmt::Format))]
314#[derive(Clone, Copy, Debug, PartialEq, Eq)]
315pub enum Fircsel {
316    #[doc = "0: FIRC is not the system clock source"]
317    NotFirc = 0,
318    #[doc = "1: FIRC is the system clock source"]
319    Firc = 1,
320}
321impl From<Fircsel> for bool {
322    #[inline(always)]
323    fn from(variant: Fircsel) -> Self {
324        variant as u8 != 0
325    }
326}
327#[doc = "Field `FIRCSEL` reader - FIRC Selected"]
328pub type FircselR = crate::BitReader<Fircsel>;
329impl FircselR {
330    #[doc = "Get enumerated values variant"]
331    #[inline(always)]
332    pub const fn variant(&self) -> Fircsel {
333        match self.bits {
334            false => Fircsel::NotFirc,
335            true => Fircsel::Firc,
336        }
337    }
338    #[doc = "FIRC is not the system clock source"]
339    #[inline(always)]
340    pub fn is_not_firc(&self) -> bool {
341        *self == Fircsel::NotFirc
342    }
343    #[doc = "FIRC is the system clock source"]
344    #[inline(always)]
345    pub fn is_firc(&self) -> bool {
346        *self == Fircsel::Firc
347    }
348}
349#[doc = "FIRC Clock Error\n\nValue on reset: 0"]
350#[cfg_attr(feature = "defmt", derive(defmt::Format))]
351#[derive(Clone, Copy, Debug, PartialEq, Eq)]
352pub enum Fircerr {
353    #[doc = "0: Error not detected with the FIRC trimming"]
354    ErrorNotDetected = 0,
355    #[doc = "1: Error detected with the FIRC trimming"]
356    ErrorDetected = 1,
357}
358impl From<Fircerr> for bool {
359    #[inline(always)]
360    fn from(variant: Fircerr) -> Self {
361        variant as u8 != 0
362    }
363}
364#[doc = "Field `FIRCERR` reader - FIRC Clock Error"]
365pub type FircerrR = crate::BitReader<Fircerr>;
366impl FircerrR {
367    #[doc = "Get enumerated values variant"]
368    #[inline(always)]
369    pub const fn variant(&self) -> Fircerr {
370        match self.bits {
371            false => Fircerr::ErrorNotDetected,
372            true => Fircerr::ErrorDetected,
373        }
374    }
375    #[doc = "Error not detected with the FIRC trimming"]
376    #[inline(always)]
377    pub fn is_error_not_detected(&self) -> bool {
378        *self == Fircerr::ErrorNotDetected
379    }
380    #[doc = "Error detected with the FIRC trimming"]
381    #[inline(always)]
382    pub fn is_error_detected(&self) -> bool {
383        *self == Fircerr::ErrorDetected
384    }
385}
386#[doc = "Field `FIRCERR` writer - FIRC Clock Error"]
387pub type FircerrW<'a, REG> = crate::BitWriter1C<'a, REG, Fircerr>;
388impl<'a, REG> FircerrW<'a, REG>
389where
390    REG: crate::Writable + crate::RegisterSpec,
391{
392    #[doc = "Error not detected with the FIRC trimming"]
393    #[inline(always)]
394    pub fn error_not_detected(self) -> &'a mut crate::W<REG> {
395        self.variant(Fircerr::ErrorNotDetected)
396    }
397    #[doc = "Error detected with the FIRC trimming"]
398    #[inline(always)]
399    pub fn error_detected(self) -> &'a mut crate::W<REG> {
400        self.variant(Fircerr::ErrorDetected)
401    }
402}
403#[doc = "FIRC Clock Error Interrupt Enable\n\nValue on reset: 0"]
404#[cfg_attr(feature = "defmt", derive(defmt::Format))]
405#[derive(Clone, Copy, Debug, PartialEq, Eq)]
406pub enum FircerrIe {
407    #[doc = "0: FIRCERR interrupt is not enabled"]
408    ErrorNotDetected = 0,
409    #[doc = "1: FIRCERR interrupt is enabled"]
410    ErrorDetected = 1,
411}
412impl From<FircerrIe> for bool {
413    #[inline(always)]
414    fn from(variant: FircerrIe) -> Self {
415        variant as u8 != 0
416    }
417}
418#[doc = "Field `FIRCERR_IE` reader - FIRC Clock Error Interrupt Enable"]
419pub type FircerrIeR = crate::BitReader<FircerrIe>;
420impl FircerrIeR {
421    #[doc = "Get enumerated values variant"]
422    #[inline(always)]
423    pub const fn variant(&self) -> FircerrIe {
424        match self.bits {
425            false => FircerrIe::ErrorNotDetected,
426            true => FircerrIe::ErrorDetected,
427        }
428    }
429    #[doc = "FIRCERR interrupt is not enabled"]
430    #[inline(always)]
431    pub fn is_error_not_detected(&self) -> bool {
432        *self == FircerrIe::ErrorNotDetected
433    }
434    #[doc = "FIRCERR interrupt is enabled"]
435    #[inline(always)]
436    pub fn is_error_detected(&self) -> bool {
437        *self == FircerrIe::ErrorDetected
438    }
439}
440#[doc = "Field `FIRCERR_IE` writer - FIRC Clock Error Interrupt Enable"]
441pub type FircerrIeW<'a, REG> = crate::BitWriter<'a, REG, FircerrIe>;
442impl<'a, REG> FircerrIeW<'a, REG>
443where
444    REG: crate::Writable + crate::RegisterSpec,
445{
446    #[doc = "FIRCERR interrupt is not enabled"]
447    #[inline(always)]
448    pub fn error_not_detected(self) -> &'a mut crate::W<REG> {
449        self.variant(FircerrIe::ErrorNotDetected)
450    }
451    #[doc = "FIRCERR interrupt is enabled"]
452    #[inline(always)]
453    pub fn error_detected(self) -> &'a mut crate::W<REG> {
454        self.variant(FircerrIe::ErrorDetected)
455    }
456}
457#[doc = "FIRC Accurate Interrupt Enable\n\nValue on reset: 0"]
458#[cfg_attr(feature = "defmt", derive(defmt::Format))]
459#[derive(Clone, Copy, Debug, PartialEq, Eq)]
460pub enum FircaccIe {
461    #[doc = "0: FIRCACC interrupt is not enabled"]
462    Fircaccnot = 0,
463    #[doc = "1: FIRCACC interrupt is enabled"]
464    Fircaccyes = 1,
465}
466impl From<FircaccIe> for bool {
467    #[inline(always)]
468    fn from(variant: FircaccIe) -> Self {
469        variant as u8 != 0
470    }
471}
472#[doc = "Field `FIRCACC_IE` reader - FIRC Accurate Interrupt Enable"]
473pub type FircaccIeR = crate::BitReader<FircaccIe>;
474impl FircaccIeR {
475    #[doc = "Get enumerated values variant"]
476    #[inline(always)]
477    pub const fn variant(&self) -> FircaccIe {
478        match self.bits {
479            false => FircaccIe::Fircaccnot,
480            true => FircaccIe::Fircaccyes,
481        }
482    }
483    #[doc = "FIRCACC interrupt is not enabled"]
484    #[inline(always)]
485    pub fn is_fircaccnot(&self) -> bool {
486        *self == FircaccIe::Fircaccnot
487    }
488    #[doc = "FIRCACC interrupt is enabled"]
489    #[inline(always)]
490    pub fn is_fircaccyes(&self) -> bool {
491        *self == FircaccIe::Fircaccyes
492    }
493}
494#[doc = "Field `FIRCACC_IE` writer - FIRC Accurate Interrupt Enable"]
495pub type FircaccIeW<'a, REG> = crate::BitWriter<'a, REG, FircaccIe>;
496impl<'a, REG> FircaccIeW<'a, REG>
497where
498    REG: crate::Writable + crate::RegisterSpec,
499{
500    #[doc = "FIRCACC interrupt is not enabled"]
501    #[inline(always)]
502    pub fn fircaccnot(self) -> &'a mut crate::W<REG> {
503        self.variant(FircaccIe::Fircaccnot)
504    }
505    #[doc = "FIRCACC interrupt is enabled"]
506    #[inline(always)]
507    pub fn fircaccyes(self) -> &'a mut crate::W<REG> {
508        self.variant(FircaccIe::Fircaccyes)
509    }
510}
511#[doc = "FIRC Frequency Accurate\n\nValue on reset: 0"]
512#[cfg_attr(feature = "defmt", derive(defmt::Format))]
513#[derive(Clone, Copy, Debug, PartialEq, Eq)]
514pub enum Fircacc {
515    #[doc = "0: FIRC is not enabled or clock is not accurate."]
516    NotEnabledOrNotValid = 0,
517    #[doc = "1: FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock."]
518    EnabledAndValid = 1,
519}
520impl From<Fircacc> for bool {
521    #[inline(always)]
522    fn from(variant: Fircacc) -> Self {
523        variant as u8 != 0
524    }
525}
526#[doc = "Field `FIRCACC` reader - FIRC Frequency Accurate"]
527pub type FircaccR = crate::BitReader<Fircacc>;
528impl FircaccR {
529    #[doc = "Get enumerated values variant"]
530    #[inline(always)]
531    pub const fn variant(&self) -> Fircacc {
532        match self.bits {
533            false => Fircacc::NotEnabledOrNotValid,
534            true => Fircacc::EnabledAndValid,
535        }
536    }
537    #[doc = "FIRC is not enabled or clock is not accurate."]
538    #[inline(always)]
539    pub fn is_not_enabled_or_not_valid(&self) -> bool {
540        *self == Fircacc::NotEnabledOrNotValid
541    }
542    #[doc = "FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock."]
543    #[inline(always)]
544    pub fn is_enabled_and_valid(&self) -> bool {
545        *self == Fircacc::EnabledAndValid
546    }
547}
548impl R {
549    #[doc = "Bit 0 - FIRC Enable"]
550    #[inline(always)]
551    pub fn fircen(&self) -> FircenR {
552        FircenR::new((self.bits & 1) != 0)
553    }
554    #[doc = "Bit 1 - FIRC Stop Enable"]
555    #[inline(always)]
556    pub fn fircsten(&self) -> FircstenR {
557        FircstenR::new(((self.bits >> 1) & 1) != 0)
558    }
559    #[doc = "Bit 4 - FIRC 45 MHz Clock to peripherals Enable"]
560    #[inline(always)]
561    pub fn firc_sclk_periph_en(&self) -> FircSclkPeriphEnR {
562        FircSclkPeriphEnR::new(((self.bits >> 4) & 1) != 0)
563    }
564    #[doc = "Bit 5 - FRO_HF Clock to peripherals Enable"]
565    #[inline(always)]
566    pub fn firc_fclk_periph_en(&self) -> FircFclkPeriphEnR {
567        FircFclkPeriphEnR::new(((self.bits >> 5) & 1) != 0)
568    }
569    #[doc = "Bit 23 - Lock Register"]
570    #[inline(always)]
571    pub fn lk(&self) -> LkR {
572        LkR::new(((self.bits >> 23) & 1) != 0)
573    }
574    #[doc = "Bit 24 - FIRC Valid status"]
575    #[inline(always)]
576    pub fn fircvld(&self) -> FircvldR {
577        FircvldR::new(((self.bits >> 24) & 1) != 0)
578    }
579    #[doc = "Bit 25 - FIRC Selected"]
580    #[inline(always)]
581    pub fn fircsel(&self) -> FircselR {
582        FircselR::new(((self.bits >> 25) & 1) != 0)
583    }
584    #[doc = "Bit 26 - FIRC Clock Error"]
585    #[inline(always)]
586    pub fn fircerr(&self) -> FircerrR {
587        FircerrR::new(((self.bits >> 26) & 1) != 0)
588    }
589    #[doc = "Bit 27 - FIRC Clock Error Interrupt Enable"]
590    #[inline(always)]
591    pub fn fircerr_ie(&self) -> FircerrIeR {
592        FircerrIeR::new(((self.bits >> 27) & 1) != 0)
593    }
594    #[doc = "Bit 30 - FIRC Accurate Interrupt Enable"]
595    #[inline(always)]
596    pub fn fircacc_ie(&self) -> FircaccIeR {
597        FircaccIeR::new(((self.bits >> 30) & 1) != 0)
598    }
599    #[doc = "Bit 31 - FIRC Frequency Accurate"]
600    #[inline(always)]
601    pub fn fircacc(&self) -> FircaccR {
602        FircaccR::new(((self.bits >> 31) & 1) != 0)
603    }
604}
605#[cfg(feature = "debug")]
606impl core::fmt::Debug for R {
607    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
608        f.debug_struct("FIRCCSR")
609            .field("fircen", &self.fircen())
610            .field("fircsten", &self.fircsten())
611            .field("firc_sclk_periph_en", &self.firc_sclk_periph_en())
612            .field("firc_fclk_periph_en", &self.firc_fclk_periph_en())
613            .field("lk", &self.lk())
614            .field("fircvld", &self.fircvld())
615            .field("fircsel", &self.fircsel())
616            .field("fircerr", &self.fircerr())
617            .field("fircerr_ie", &self.fircerr_ie())
618            .field("fircacc_ie", &self.fircacc_ie())
619            .field("fircacc", &self.fircacc())
620            .finish()
621    }
622}
623impl W {
624    #[doc = "Bit 0 - FIRC Enable"]
625    #[inline(always)]
626    pub fn fircen(&mut self) -> FircenW<'_, FirccsrSpec> {
627        FircenW::new(self, 0)
628    }
629    #[doc = "Bit 1 - FIRC Stop Enable"]
630    #[inline(always)]
631    pub fn fircsten(&mut self) -> FircstenW<'_, FirccsrSpec> {
632        FircstenW::new(self, 1)
633    }
634    #[doc = "Bit 4 - FIRC 45 MHz Clock to peripherals Enable"]
635    #[inline(always)]
636    pub fn firc_sclk_periph_en(&mut self) -> FircSclkPeriphEnW<'_, FirccsrSpec> {
637        FircSclkPeriphEnW::new(self, 4)
638    }
639    #[doc = "Bit 5 - FRO_HF Clock to peripherals Enable"]
640    #[inline(always)]
641    pub fn firc_fclk_periph_en(&mut self) -> FircFclkPeriphEnW<'_, FirccsrSpec> {
642        FircFclkPeriphEnW::new(self, 5)
643    }
644    #[doc = "Bit 23 - Lock Register"]
645    #[inline(always)]
646    pub fn lk(&mut self) -> LkW<'_, FirccsrSpec> {
647        LkW::new(self, 23)
648    }
649    #[doc = "Bit 26 - FIRC Clock Error"]
650    #[inline(always)]
651    pub fn fircerr(&mut self) -> FircerrW<'_, FirccsrSpec> {
652        FircerrW::new(self, 26)
653    }
654    #[doc = "Bit 27 - FIRC Clock Error Interrupt Enable"]
655    #[inline(always)]
656    pub fn fircerr_ie(&mut self) -> FircerrIeW<'_, FirccsrSpec> {
657        FircerrIeW::new(self, 27)
658    }
659    #[doc = "Bit 30 - FIRC Accurate Interrupt Enable"]
660    #[inline(always)]
661    pub fn fircacc_ie(&mut self) -> FircaccIeW<'_, FirccsrSpec> {
662        FircaccIeW::new(self, 30)
663    }
664}
665#[doc = "FIRC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firccsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firccsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
666pub struct FirccsrSpec;
667impl crate::RegisterSpec for FirccsrSpec {
668    type Ux = u32;
669}
670#[doc = "`read()` method returns [`firccsr::R`](R) reader structure"]
671impl crate::Readable for FirccsrSpec {}
672#[doc = "`write(|w| ..)` method takes [`firccsr::W`](W) writer structure"]
673impl crate::Writable for FirccsrSpec {
674    type Safety = crate::Unsafe;
675    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000;
676}
677#[doc = "`reset()` method sets FIRCCSR to value 0x0300_0031"]
678impl crate::Resettable for FirccsrSpec {
679    const RESET_VALUE: u32 = 0x0300_0031;
680}
mcxa_pac/scg0/firccsr.rs

mcxa_pac/scg0/
firccsr.rs
