mcxa_pac/
mrcc0.rs

1#[repr(C)]
2#[cfg_attr(feature = "debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    mrcc_glb_rst0: MrccGlbRst0,
6    mrcc_glb_rst0_set: MrccGlbRst0Set,
7    mrcc_glb_rst0_clr: MrccGlbRst0Clr,
8    _reserved3: [u8; 0x04],
9    mrcc_glb_rst1: MrccGlbRst1,
10    mrcc_glb_rst1_set: MrccGlbRst1Set,
11    mrcc_glb_rst1_clr: MrccGlbRst1Clr,
12    _reserved6: [u8; 0x04],
13    mrcc_glb_rst2: MrccGlbRst2,
14    mrcc_glb_rst2_set: MrccGlbRst2Set,
15    mrcc_glb_rst2_clr: MrccGlbRst2Clr,
16    _reserved9: [u8; 0x14],
17    mrcc_glb_cc0: MrccGlbCc0,
18    mrcc_glb_cc0_set: MrccGlbCc0Set,
19    mrcc_glb_cc0_clr: MrccGlbCc0Clr,
20    _reserved12: [u8; 0x04],
21    mrcc_glb_cc1: MrccGlbCc1,
22    mrcc_glb_cc1_set: MrccGlbCc1Set,
23    mrcc_glb_cc1_clr: MrccGlbCc1Clr,
24    _reserved15: [u8; 0x04],
25    mrcc_glb_cc2: MrccGlbCc2,
26    mrcc_glb_cc2_set: MrccGlbCc2Set,
27    mrcc_glb_cc2_clr: MrccGlbCc2Clr,
28    _reserved18: [u8; 0x14],
29    mrcc_glb_acc0: MrccGlbAcc0,
30    mrcc_glb_acc1: MrccGlbAcc1,
31    mrcc_glb_acc2: MrccGlbAcc2,
32    _reserved21: [u8; 0x14],
33    mrcc_i3c0_fclk_clksel: MrccI3c0FclkClksel,
34    mrcc_i3c0_fclk_clkdiv: MrccI3c0FclkClkdiv,
35    mrcc_ctimer0_clksel: MrccCtimer0Clksel,
36    mrcc_ctimer0_clkdiv: MrccCtimer0Clkdiv,
37    mrcc_ctimer1_clksel: MrccCtimer1Clksel,
38    mrcc_ctimer1_clkdiv: MrccCtimer1Clkdiv,
39    mrcc_ctimer2_clksel: MrccCtimer2Clksel,
40    mrcc_ctimer2_clkdiv: MrccCtimer2Clkdiv,
41    mrcc_ctimer3_clksel: MrccCtimer3Clksel,
42    mrcc_ctimer3_clkdiv: MrccCtimer3Clkdiv,
43    mrcc_ctimer4_clksel: MrccCtimer4Clksel,
44    mrcc_ctimer4_clkdiv: MrccCtimer4Clkdiv,
45    _reserved33: [u8; 0x04],
46    mrcc_wwdt0_clkdiv: MrccWwdt0Clkdiv,
47    mrcc_flexio0_clksel: MrccFlexio0Clksel,
48    mrcc_flexio0_clkdiv: MrccFlexio0Clkdiv,
49    mrcc_lpi2c0_clksel: MrccLpi2c0Clksel,
50    mrcc_lpi2c0_clkdiv: MrccLpi2c0Clkdiv,
51    mrcc_lpi2c1_clksel: MrccLpi2c1Clksel,
52    mrcc_lpi2c1_clkdiv: MrccLpi2c1Clkdiv,
53    mrcc_lpspi0_clksel: MrccLpspi0Clksel,
54    mrcc_lpspi0_clkdiv: MrccLpspi0Clkdiv,
55    mrcc_lpspi1_clksel: MrccLpspi1Clksel,
56    mrcc_lpspi1_clkdiv: MrccLpspi1Clkdiv,
57    mrcc_lpuart0_clksel: MrccLpuart0Clksel,
58    mrcc_lpuart0_clkdiv: MrccLpuart0Clkdiv,
59    mrcc_lpuart1_clksel: MrccLpuart1Clksel,
60    mrcc_lpuart1_clkdiv: MrccLpuart1Clkdiv,
61    mrcc_lpuart2_clksel: MrccLpuart2Clksel,
62    mrcc_lpuart2_clkdiv: MrccLpuart2Clkdiv,
63    mrcc_lpuart3_clksel: MrccLpuart3Clksel,
64    mrcc_lpuart3_clkdiv: MrccLpuart3Clkdiv,
65    mrcc_lpuart4_clksel: MrccLpuart4Clksel,
66    mrcc_lpuart4_clkdiv: MrccLpuart4Clkdiv,
67    mrcc_usb0_clksel: MrccUsb0Clksel,
68    mrcc_usb0_clkdiv: MrccUsb0Clkdiv,
69    mrcc_lptmr0_clksel: MrccLptmr0Clksel,
70    mrcc_lptmr0_clkdiv: MrccLptmr0Clkdiv,
71    mrcc_ostimer0_clksel: MrccOstimer0Clksel,
72    _reserved59: [u8; 0x04],
73    mrcc_adc_clksel: MrccAdcClksel,
74    mrcc_adc_clkdiv: MrccAdcClkdiv,
75    _reserved61: [u8; 0x04],
76    mrcc_cmp0_func_clkdiv: MrccCmp0FuncClkdiv,
77    mrcc_cmp0_rr_clksel: MrccCmp0RrClksel,
78    mrcc_cmp0_rr_clkdiv: MrccCmp0RrClkdiv,
79    _reserved64: [u8; 0x04],
80    mrcc_cmp1_func_clkdiv: MrccCmp1FuncClkdiv,
81    mrcc_cmp1_rr_clksel: MrccCmp1RrClksel,
82    mrcc_cmp1_rr_clkdiv: MrccCmp1RrClkdiv,
83    _reserved67: [u8; 0x04],
84    mrcc_cmp2_func_clkdiv: MrccCmp2FuncClkdiv,
85    mrcc_cmp2_rr_clksel: MrccCmp2RrClksel,
86    mrcc_cmp2_rr_clkdiv: MrccCmp2RrClkdiv,
87    mrcc_dac0_clksel: MrccDac0Clksel,
88    mrcc_dac0_clkdiv: MrccDac0Clkdiv,
89    mrcc_flexcan0_clksel: MrccFlexcan0Clksel,
90    mrcc_flexcan0_clkdiv: MrccFlexcan0Clkdiv,
91    mrcc_flexcan1_clksel: MrccFlexcan1Clksel,
92    mrcc_flexcan1_clkdiv: MrccFlexcan1Clkdiv,
93    mrcc_lpi2c2_clksel: MrccLpi2c2Clksel,
94    mrcc_lpi2c2_clkdiv: MrccLpi2c2Clkdiv,
95    mrcc_lpi2c3_clksel: MrccLpi2c3Clksel,
96    mrcc_lpi2c3_clkdiv: MrccLpi2c3Clkdiv,
97    mrcc_lpuart5_clksel: MrccLpuart5Clksel,
98    mrcc_lpuart5_clkdiv: MrccLpuart5Clkdiv,
99    mrcc_dbg_trace_clksel: MrccDbgTraceClksel,
100    mrcc_dbg_trace_clkdiv: MrccDbgTraceClkdiv,
101    mrcc_clkout_clksel: MrccClkoutClksel,
102    mrcc_clkout_clkdiv: MrccClkoutClkdiv,
103    mrcc_systick_clksel: MrccSystickClksel,
104    mrcc_systick_clkdiv: MrccSystickClkdiv,
105}
106impl RegisterBlock {
107    #[doc = "0x00 - Peripheral Reset Control 0"]
108    #[inline(always)]
109    pub const fn mrcc_glb_rst0(&self) -> &MrccGlbRst0 {
110        &self.mrcc_glb_rst0
111    }
112    #[doc = "0x04 - Peripheral Reset Control Set 0"]
113    #[inline(always)]
114    pub const fn mrcc_glb_rst0_set(&self) -> &MrccGlbRst0Set {
115        &self.mrcc_glb_rst0_set
116    }
117    #[doc = "0x08 - Peripheral Reset Control Clear 0"]
118    #[inline(always)]
119    pub const fn mrcc_glb_rst0_clr(&self) -> &MrccGlbRst0Clr {
120        &self.mrcc_glb_rst0_clr
121    }
122    #[doc = "0x10 - Peripheral Reset Control 1"]
123    #[inline(always)]
124    pub const fn mrcc_glb_rst1(&self) -> &MrccGlbRst1 {
125        &self.mrcc_glb_rst1
126    }
127    #[doc = "0x14 - Peripheral Reset Control Set 1"]
128    #[inline(always)]
129    pub const fn mrcc_glb_rst1_set(&self) -> &MrccGlbRst1Set {
130        &self.mrcc_glb_rst1_set
131    }
132    #[doc = "0x18 - Peripheral Reset Control Clear 1"]
133    #[inline(always)]
134    pub const fn mrcc_glb_rst1_clr(&self) -> &MrccGlbRst1Clr {
135        &self.mrcc_glb_rst1_clr
136    }
137    #[doc = "0x20 - Peripheral Reset Control 2"]
138    #[inline(always)]
139    pub const fn mrcc_glb_rst2(&self) -> &MrccGlbRst2 {
140        &self.mrcc_glb_rst2
141    }
142    #[doc = "0x24 - Peripheral Reset Control Set 2"]
143    #[inline(always)]
144    pub const fn mrcc_glb_rst2_set(&self) -> &MrccGlbRst2Set {
145        &self.mrcc_glb_rst2_set
146    }
147    #[doc = "0x28 - Peripheral Reset Control Clear 2"]
148    #[inline(always)]
149    pub const fn mrcc_glb_rst2_clr(&self) -> &MrccGlbRst2Clr {
150        &self.mrcc_glb_rst2_clr
151    }
152    #[doc = "0x40 - AHB Clock Control 0"]
153    #[inline(always)]
154    pub const fn mrcc_glb_cc0(&self) -> &MrccGlbCc0 {
155        &self.mrcc_glb_cc0
156    }
157    #[doc = "0x44 - AHB Clock Control Set 0"]
158    #[inline(always)]
159    pub const fn mrcc_glb_cc0_set(&self) -> &MrccGlbCc0Set {
160        &self.mrcc_glb_cc0_set
161    }
162    #[doc = "0x48 - AHB Clock Control Clear 0"]
163    #[inline(always)]
164    pub const fn mrcc_glb_cc0_clr(&self) -> &MrccGlbCc0Clr {
165        &self.mrcc_glb_cc0_clr
166    }
167    #[doc = "0x50 - AHB Clock Control 1"]
168    #[inline(always)]
169    pub const fn mrcc_glb_cc1(&self) -> &MrccGlbCc1 {
170        &self.mrcc_glb_cc1
171    }
172    #[doc = "0x54 - AHB Clock Control Set 1"]
173    #[inline(always)]
174    pub const fn mrcc_glb_cc1_set(&self) -> &MrccGlbCc1Set {
175        &self.mrcc_glb_cc1_set
176    }
177    #[doc = "0x58 - AHB Clock Control Clear 1"]
178    #[inline(always)]
179    pub const fn mrcc_glb_cc1_clr(&self) -> &MrccGlbCc1Clr {
180        &self.mrcc_glb_cc1_clr
181    }
182    #[doc = "0x60 - AHB Clock Control 2"]
183    #[inline(always)]
184    pub const fn mrcc_glb_cc2(&self) -> &MrccGlbCc2 {
185        &self.mrcc_glb_cc2
186    }
187    #[doc = "0x64 - AHB Clock Control Set 2"]
188    #[inline(always)]
189    pub const fn mrcc_glb_cc2_set(&self) -> &MrccGlbCc2Set {
190        &self.mrcc_glb_cc2_set
191    }
192    #[doc = "0x68 - AHB Clock Control Clear 2"]
193    #[inline(always)]
194    pub const fn mrcc_glb_cc2_clr(&self) -> &MrccGlbCc2Clr {
195        &self.mrcc_glb_cc2_clr
196    }
197    #[doc = "0x80 - Control Automatic Clock Gating 0"]
198    #[inline(always)]
199    pub const fn mrcc_glb_acc0(&self) -> &MrccGlbAcc0 {
200        &self.mrcc_glb_acc0
201    }
202    #[doc = "0x84 - Control Automatic Clock Gating 1"]
203    #[inline(always)]
204    pub const fn mrcc_glb_acc1(&self) -> &MrccGlbAcc1 {
205        &self.mrcc_glb_acc1
206    }
207    #[doc = "0x88 - Control Automatic Clock Gating 2"]
208    #[inline(always)]
209    pub const fn mrcc_glb_acc2(&self) -> &MrccGlbAcc2 {
210        &self.mrcc_glb_acc2
211    }
212    #[doc = "0xa0 - I3C0_FCLK clock selection control"]
213    #[inline(always)]
214    pub const fn mrcc_i3c0_fclk_clksel(&self) -> &MrccI3c0FclkClksel {
215        &self.mrcc_i3c0_fclk_clksel
216    }
217    #[doc = "0xa4 - I3C0_FCLK clock divider control"]
218    #[inline(always)]
219    pub const fn mrcc_i3c0_fclk_clkdiv(&self) -> &MrccI3c0FclkClkdiv {
220        &self.mrcc_i3c0_fclk_clkdiv
221    }
222    #[doc = "0xa8 - CTIMER0 clock selection control"]
223    #[inline(always)]
224    pub const fn mrcc_ctimer0_clksel(&self) -> &MrccCtimer0Clksel {
225        &self.mrcc_ctimer0_clksel
226    }
227    #[doc = "0xac - CTIMER0 clock divider control"]
228    #[inline(always)]
229    pub const fn mrcc_ctimer0_clkdiv(&self) -> &MrccCtimer0Clkdiv {
230        &self.mrcc_ctimer0_clkdiv
231    }
232    #[doc = "0xb0 - CTIMER1 clock selection control"]
233    #[inline(always)]
234    pub const fn mrcc_ctimer1_clksel(&self) -> &MrccCtimer1Clksel {
235        &self.mrcc_ctimer1_clksel
236    }
237    #[doc = "0xb4 - CTIMER1 clock divider control"]
238    #[inline(always)]
239    pub const fn mrcc_ctimer1_clkdiv(&self) -> &MrccCtimer1Clkdiv {
240        &self.mrcc_ctimer1_clkdiv
241    }
242    #[doc = "0xb8 - CTIMER2 clock selection control"]
243    #[inline(always)]
244    pub const fn mrcc_ctimer2_clksel(&self) -> &MrccCtimer2Clksel {
245        &self.mrcc_ctimer2_clksel
246    }
247    #[doc = "0xbc - CTIMER2 clock divider control"]
248    #[inline(always)]
249    pub const fn mrcc_ctimer2_clkdiv(&self) -> &MrccCtimer2Clkdiv {
250        &self.mrcc_ctimer2_clkdiv
251    }
252    #[doc = "0xc0 - CTIMER3 clock selection control"]
253    #[inline(always)]
254    pub const fn mrcc_ctimer3_clksel(&self) -> &MrccCtimer3Clksel {
255        &self.mrcc_ctimer3_clksel
256    }
257    #[doc = "0xc4 - CTIMER3 clock divider control"]
258    #[inline(always)]
259    pub const fn mrcc_ctimer3_clkdiv(&self) -> &MrccCtimer3Clkdiv {
260        &self.mrcc_ctimer3_clkdiv
261    }
262    #[doc = "0xc8 - CTIMER4 clock selection control"]
263    #[inline(always)]
264    pub const fn mrcc_ctimer4_clksel(&self) -> &MrccCtimer4Clksel {
265        &self.mrcc_ctimer4_clksel
266    }
267    #[doc = "0xcc - CTIMER4 clock divider control"]
268    #[inline(always)]
269    pub const fn mrcc_ctimer4_clkdiv(&self) -> &MrccCtimer4Clkdiv {
270        &self.mrcc_ctimer4_clkdiv
271    }
272    #[doc = "0xd4 - WWDT0 clock divider control"]
273    #[inline(always)]
274    pub const fn mrcc_wwdt0_clkdiv(&self) -> &MrccWwdt0Clkdiv {
275        &self.mrcc_wwdt0_clkdiv
276    }
277    #[doc = "0xd8 - FLEXIO0 clock selection control"]
278    #[inline(always)]
279    pub const fn mrcc_flexio0_clksel(&self) -> &MrccFlexio0Clksel {
280        &self.mrcc_flexio0_clksel
281    }
282    #[doc = "0xdc - FLEXIO0 clock divider control"]
283    #[inline(always)]
284    pub const fn mrcc_flexio0_clkdiv(&self) -> &MrccFlexio0Clkdiv {
285        &self.mrcc_flexio0_clkdiv
286    }
287    #[doc = "0xe0 - LPI2C0 clock selection control"]
288    #[inline(always)]
289    pub const fn mrcc_lpi2c0_clksel(&self) -> &MrccLpi2c0Clksel {
290        &self.mrcc_lpi2c0_clksel
291    }
292    #[doc = "0xe4 - LPI2C0 clock divider control"]
293    #[inline(always)]
294    pub const fn mrcc_lpi2c0_clkdiv(&self) -> &MrccLpi2c0Clkdiv {
295        &self.mrcc_lpi2c0_clkdiv
296    }
297    #[doc = "0xe8 - LPI2C1 clock selection control"]
298    #[inline(always)]
299    pub const fn mrcc_lpi2c1_clksel(&self) -> &MrccLpi2c1Clksel {
300        &self.mrcc_lpi2c1_clksel
301    }
302    #[doc = "0xec - LPI2C1 clock divider control"]
303    #[inline(always)]
304    pub const fn mrcc_lpi2c1_clkdiv(&self) -> &MrccLpi2c1Clkdiv {
305        &self.mrcc_lpi2c1_clkdiv
306    }
307    #[doc = "0xf0 - LPSPI0 clock selection control"]
308    #[inline(always)]
309    pub const fn mrcc_lpspi0_clksel(&self) -> &MrccLpspi0Clksel {
310        &self.mrcc_lpspi0_clksel
311    }
312    #[doc = "0xf4 - LPSPI0 clock divider control"]
313    #[inline(always)]
314    pub const fn mrcc_lpspi0_clkdiv(&self) -> &MrccLpspi0Clkdiv {
315        &self.mrcc_lpspi0_clkdiv
316    }
317    #[doc = "0xf8 - LPSPI1 clock selection control"]
318    #[inline(always)]
319    pub const fn mrcc_lpspi1_clksel(&self) -> &MrccLpspi1Clksel {
320        &self.mrcc_lpspi1_clksel
321    }
322    #[doc = "0xfc - LPSPI1 clock divider control"]
323    #[inline(always)]
324    pub const fn mrcc_lpspi1_clkdiv(&self) -> &MrccLpspi1Clkdiv {
325        &self.mrcc_lpspi1_clkdiv
326    }
327    #[doc = "0x100 - LPUART0 clock selection control"]
328    #[inline(always)]
329    pub const fn mrcc_lpuart0_clksel(&self) -> &MrccLpuart0Clksel {
330        &self.mrcc_lpuart0_clksel
331    }
332    #[doc = "0x104 - LPUART0 clock divider control"]
333    #[inline(always)]
334    pub const fn mrcc_lpuart0_clkdiv(&self) -> &MrccLpuart0Clkdiv {
335        &self.mrcc_lpuart0_clkdiv
336    }
337    #[doc = "0x108 - LPUART1 clock selection control"]
338    #[inline(always)]
339    pub const fn mrcc_lpuart1_clksel(&self) -> &MrccLpuart1Clksel {
340        &self.mrcc_lpuart1_clksel
341    }
342    #[doc = "0x10c - LPUART1 clock divider control"]
343    #[inline(always)]
344    pub const fn mrcc_lpuart1_clkdiv(&self) -> &MrccLpuart1Clkdiv {
345        &self.mrcc_lpuart1_clkdiv
346    }
347    #[doc = "0x110 - LPUART2 clock selection control"]
348    #[inline(always)]
349    pub const fn mrcc_lpuart2_clksel(&self) -> &MrccLpuart2Clksel {
350        &self.mrcc_lpuart2_clksel
351    }
352    #[doc = "0x114 - LPUART2 clock divider control"]
353    #[inline(always)]
354    pub const fn mrcc_lpuart2_clkdiv(&self) -> &MrccLpuart2Clkdiv {
355        &self.mrcc_lpuart2_clkdiv
356    }
357    #[doc = "0x118 - LPUART3 clock selection control"]
358    #[inline(always)]
359    pub const fn mrcc_lpuart3_clksel(&self) -> &MrccLpuart3Clksel {
360        &self.mrcc_lpuart3_clksel
361    }
362    #[doc = "0x11c - LPUART3 clock divider control"]
363    #[inline(always)]
364    pub const fn mrcc_lpuart3_clkdiv(&self) -> &MrccLpuart3Clkdiv {
365        &self.mrcc_lpuart3_clkdiv
366    }
367    #[doc = "0x120 - LPUART4 clock selection control"]
368    #[inline(always)]
369    pub const fn mrcc_lpuart4_clksel(&self) -> &MrccLpuart4Clksel {
370        &self.mrcc_lpuart4_clksel
371    }
372    #[doc = "0x124 - LPUART4 clock divider control"]
373    #[inline(always)]
374    pub const fn mrcc_lpuart4_clkdiv(&self) -> &MrccLpuart4Clkdiv {
375        &self.mrcc_lpuart4_clkdiv
376    }
377    #[doc = "0x128 - USB0 clock selection control"]
378    #[inline(always)]
379    pub const fn mrcc_usb0_clksel(&self) -> &MrccUsb0Clksel {
380        &self.mrcc_usb0_clksel
381    }
382    #[doc = "0x12c - USB0 clock divider control"]
383    #[inline(always)]
384    pub const fn mrcc_usb0_clkdiv(&self) -> &MrccUsb0Clkdiv {
385        &self.mrcc_usb0_clkdiv
386    }
387    #[doc = "0x130 - LPTMR0 clock selection control"]
388    #[inline(always)]
389    pub const fn mrcc_lptmr0_clksel(&self) -> &MrccLptmr0Clksel {
390        &self.mrcc_lptmr0_clksel
391    }
392    #[doc = "0x134 - LPTMR0 clock divider control"]
393    #[inline(always)]
394    pub const fn mrcc_lptmr0_clkdiv(&self) -> &MrccLptmr0Clkdiv {
395        &self.mrcc_lptmr0_clkdiv
396    }
397    #[doc = "0x138 - OSTIMER0 clock selection control"]
398    #[inline(always)]
399    pub const fn mrcc_ostimer0_clksel(&self) -> &MrccOstimer0Clksel {
400        &self.mrcc_ostimer0_clksel
401    }
402    #[doc = "0x140 - ADCx clock selection control"]
403    #[inline(always)]
404    pub const fn mrcc_adc_clksel(&self) -> &MrccAdcClksel {
405        &self.mrcc_adc_clksel
406    }
407    #[doc = "0x144 - ADCx clock divider control"]
408    #[inline(always)]
409    pub const fn mrcc_adc_clkdiv(&self) -> &MrccAdcClkdiv {
410        &self.mrcc_adc_clkdiv
411    }
412    #[doc = "0x14c - CMP0_FUNC clock divider control"]
413    #[inline(always)]
414    pub const fn mrcc_cmp0_func_clkdiv(&self) -> &MrccCmp0FuncClkdiv {
415        &self.mrcc_cmp0_func_clkdiv
416    }
417    #[doc = "0x150 - CMP0_RR clock selection control"]
418    #[inline(always)]
419    pub const fn mrcc_cmp0_rr_clksel(&self) -> &MrccCmp0RrClksel {
420        &self.mrcc_cmp0_rr_clksel
421    }
422    #[doc = "0x154 - CMP0_RR clock divider control"]
423    #[inline(always)]
424    pub const fn mrcc_cmp0_rr_clkdiv(&self) -> &MrccCmp0RrClkdiv {
425        &self.mrcc_cmp0_rr_clkdiv
426    }
427    #[doc = "0x15c - CMP1_FUNC clock divider control"]
428    #[inline(always)]
429    pub const fn mrcc_cmp1_func_clkdiv(&self) -> &MrccCmp1FuncClkdiv {
430        &self.mrcc_cmp1_func_clkdiv
431    }
432    #[doc = "0x160 - CMP1_RR clock selection control"]
433    #[inline(always)]
434    pub const fn mrcc_cmp1_rr_clksel(&self) -> &MrccCmp1RrClksel {
435        &self.mrcc_cmp1_rr_clksel
436    }
437    #[doc = "0x164 - CMP1_RR clock divider control"]
438    #[inline(always)]
439    pub const fn mrcc_cmp1_rr_clkdiv(&self) -> &MrccCmp1RrClkdiv {
440        &self.mrcc_cmp1_rr_clkdiv
441    }
442    #[doc = "0x16c - CMP2_FUNC clock divider control"]
443    #[inline(always)]
444    pub const fn mrcc_cmp2_func_clkdiv(&self) -> &MrccCmp2FuncClkdiv {
445        &self.mrcc_cmp2_func_clkdiv
446    }
447    #[doc = "0x170 - CMP2_RR clock selection control"]
448    #[inline(always)]
449    pub const fn mrcc_cmp2_rr_clksel(&self) -> &MrccCmp2RrClksel {
450        &self.mrcc_cmp2_rr_clksel
451    }
452    #[doc = "0x174 - CMP2_RR clock divider control"]
453    #[inline(always)]
454    pub const fn mrcc_cmp2_rr_clkdiv(&self) -> &MrccCmp2RrClkdiv {
455        &self.mrcc_cmp2_rr_clkdiv
456    }
457    #[doc = "0x178 - DAC0 clock selection control"]
458    #[inline(always)]
459    pub const fn mrcc_dac0_clksel(&self) -> &MrccDac0Clksel {
460        &self.mrcc_dac0_clksel
461    }
462    #[doc = "0x17c - DAC0 clock divider control"]
463    #[inline(always)]
464    pub const fn mrcc_dac0_clkdiv(&self) -> &MrccDac0Clkdiv {
465        &self.mrcc_dac0_clkdiv
466    }
467    #[doc = "0x180 - FLEXCAN0 clock selection control"]
468    #[inline(always)]
469    pub const fn mrcc_flexcan0_clksel(&self) -> &MrccFlexcan0Clksel {
470        &self.mrcc_flexcan0_clksel
471    }
472    #[doc = "0x184 - FLEXCAN0 clock divider control"]
473    #[inline(always)]
474    pub const fn mrcc_flexcan0_clkdiv(&self) -> &MrccFlexcan0Clkdiv {
475        &self.mrcc_flexcan0_clkdiv
476    }
477    #[doc = "0x188 - FLEXCAN1 clock selection control"]
478    #[inline(always)]
479    pub const fn mrcc_flexcan1_clksel(&self) -> &MrccFlexcan1Clksel {
480        &self.mrcc_flexcan1_clksel
481    }
482    #[doc = "0x18c - FLEXCAN1 clock divider control"]
483    #[inline(always)]
484    pub const fn mrcc_flexcan1_clkdiv(&self) -> &MrccFlexcan1Clkdiv {
485        &self.mrcc_flexcan1_clkdiv
486    }
487    #[doc = "0x190 - LPI2C2 clock selection control"]
488    #[inline(always)]
489    pub const fn mrcc_lpi2c2_clksel(&self) -> &MrccLpi2c2Clksel {
490        &self.mrcc_lpi2c2_clksel
491    }
492    #[doc = "0x194 - LPI2C2 clock divider control"]
493    #[inline(always)]
494    pub const fn mrcc_lpi2c2_clkdiv(&self) -> &MrccLpi2c2Clkdiv {
495        &self.mrcc_lpi2c2_clkdiv
496    }
497    #[doc = "0x198 - LPI2C3 clock selection control"]
498    #[inline(always)]
499    pub const fn mrcc_lpi2c3_clksel(&self) -> &MrccLpi2c3Clksel {
500        &self.mrcc_lpi2c3_clksel
501    }
502    #[doc = "0x19c - LPI2C3 clock divider control"]
503    #[inline(always)]
504    pub const fn mrcc_lpi2c3_clkdiv(&self) -> &MrccLpi2c3Clkdiv {
505        &self.mrcc_lpi2c3_clkdiv
506    }
507    #[doc = "0x1a0 - LPUART5 clock selection control"]
508    #[inline(always)]
509    pub const fn mrcc_lpuart5_clksel(&self) -> &MrccLpuart5Clksel {
510        &self.mrcc_lpuart5_clksel
511    }
512    #[doc = "0x1a4 - LPUART5 clock divider control"]
513    #[inline(always)]
514    pub const fn mrcc_lpuart5_clkdiv(&self) -> &MrccLpuart5Clkdiv {
515        &self.mrcc_lpuart5_clkdiv
516    }
517    #[doc = "0x1a8 - DBG_TRACE clock selection control"]
518    #[inline(always)]
519    pub const fn mrcc_dbg_trace_clksel(&self) -> &MrccDbgTraceClksel {
520        &self.mrcc_dbg_trace_clksel
521    }
522    #[doc = "0x1ac - DBG_TRACE clock divider control"]
523    #[inline(always)]
524    pub const fn mrcc_dbg_trace_clkdiv(&self) -> &MrccDbgTraceClkdiv {
525        &self.mrcc_dbg_trace_clkdiv
526    }
527    #[doc = "0x1b0 - CLKOUT clock selection control"]
528    #[inline(always)]
529    pub const fn mrcc_clkout_clksel(&self) -> &MrccClkoutClksel {
530        &self.mrcc_clkout_clksel
531    }
532    #[doc = "0x1b4 - CLKOUT clock divider control"]
533    #[inline(always)]
534    pub const fn mrcc_clkout_clkdiv(&self) -> &MrccClkoutClkdiv {
535        &self.mrcc_clkout_clkdiv
536    }
537    #[doc = "0x1b8 - SYSTICK clock selection control"]
538    #[inline(always)]
539    pub const fn mrcc_systick_clksel(&self) -> &MrccSystickClksel {
540        &self.mrcc_systick_clksel
541    }
542    #[doc = "0x1bc - SYSTICK clock divider control"]
543    #[inline(always)]
544    pub const fn mrcc_systick_clkdiv(&self) -> &MrccSystickClkdiv {
545        &self.mrcc_systick_clkdiv
546    }
547}
548#[doc = "MRCC_GLB_RST0 (rw) register accessor: Peripheral Reset Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst0`] module"]
549#[doc(alias = "MRCC_GLB_RST0")]
550pub type MrccGlbRst0 = crate::Reg<mrcc_glb_rst0::MrccGlbRst0Spec>;
551#[doc = "Peripheral Reset Control 0"]
552pub mod mrcc_glb_rst0;
553#[doc = "MRCC_GLB_RST0_SET (w) register accessor: Peripheral Reset Control Set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst0_set`] module"]
554#[doc(alias = "MRCC_GLB_RST0_SET")]
555pub type MrccGlbRst0Set = crate::Reg<mrcc_glb_rst0_set::MrccGlbRst0SetSpec>;
556#[doc = "Peripheral Reset Control Set 0"]
557pub mod mrcc_glb_rst0_set;
558#[doc = "MRCC_GLB_RST0_CLR (w) register accessor: Peripheral Reset Control Clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst0_clr`] module"]
559#[doc(alias = "MRCC_GLB_RST0_CLR")]
560pub type MrccGlbRst0Clr = crate::Reg<mrcc_glb_rst0_clr::MrccGlbRst0ClrSpec>;
561#[doc = "Peripheral Reset Control Clear 0"]
562pub mod mrcc_glb_rst0_clr;
563#[doc = "MRCC_GLB_RST1 (rw) register accessor: Peripheral Reset Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst1`] module"]
564#[doc(alias = "MRCC_GLB_RST1")]
565pub type MrccGlbRst1 = crate::Reg<mrcc_glb_rst1::MrccGlbRst1Spec>;
566#[doc = "Peripheral Reset Control 1"]
567pub mod mrcc_glb_rst1;
568#[doc = "MRCC_GLB_RST1_SET (w) register accessor: Peripheral Reset Control Set 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst1_set`] module"]
569#[doc(alias = "MRCC_GLB_RST1_SET")]
570pub type MrccGlbRst1Set = crate::Reg<mrcc_glb_rst1_set::MrccGlbRst1SetSpec>;
571#[doc = "Peripheral Reset Control Set 1"]
572pub mod mrcc_glb_rst1_set;
573#[doc = "MRCC_GLB_RST1_CLR (w) register accessor: Peripheral Reset Control Clear 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst1_clr`] module"]
574#[doc(alias = "MRCC_GLB_RST1_CLR")]
575pub type MrccGlbRst1Clr = crate::Reg<mrcc_glb_rst1_clr::MrccGlbRst1ClrSpec>;
576#[doc = "Peripheral Reset Control Clear 1"]
577pub mod mrcc_glb_rst1_clr;
578#[doc = "MRCC_GLB_RST2 (rw) register accessor: Peripheral Reset Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst2`] module"]
579#[doc(alias = "MRCC_GLB_RST2")]
580pub type MrccGlbRst2 = crate::Reg<mrcc_glb_rst2::MrccGlbRst2Spec>;
581#[doc = "Peripheral Reset Control 2"]
582pub mod mrcc_glb_rst2;
583#[doc = "MRCC_GLB_RST2_SET (w) register accessor: Peripheral Reset Control Set 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst2_set`] module"]
584#[doc(alias = "MRCC_GLB_RST2_SET")]
585pub type MrccGlbRst2Set = crate::Reg<mrcc_glb_rst2_set::MrccGlbRst2SetSpec>;
586#[doc = "Peripheral Reset Control Set 2"]
587pub mod mrcc_glb_rst2_set;
588#[doc = "MRCC_GLB_RST2_CLR (w) register accessor: Peripheral Reset Control Clear 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst2_clr`] module"]
589#[doc(alias = "MRCC_GLB_RST2_CLR")]
590pub type MrccGlbRst2Clr = crate::Reg<mrcc_glb_rst2_clr::MrccGlbRst2ClrSpec>;
591#[doc = "Peripheral Reset Control Clear 2"]
592pub mod mrcc_glb_rst2_clr;
593#[doc = "MRCC_GLB_CC0 (rw) register accessor: AHB Clock Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc0`] module"]
594#[doc(alias = "MRCC_GLB_CC0")]
595pub type MrccGlbCc0 = crate::Reg<mrcc_glb_cc0::MrccGlbCc0Spec>;
596#[doc = "AHB Clock Control 0"]
597pub mod mrcc_glb_cc0;
598#[doc = "MRCC_GLB_CC0_SET (w) register accessor: AHB Clock Control Set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc0_set`] module"]
599#[doc(alias = "MRCC_GLB_CC0_SET")]
600pub type MrccGlbCc0Set = crate::Reg<mrcc_glb_cc0_set::MrccGlbCc0SetSpec>;
601#[doc = "AHB Clock Control Set 0"]
602pub mod mrcc_glb_cc0_set;
603#[doc = "MRCC_GLB_CC0_CLR (w) register accessor: AHB Clock Control Clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc0_clr`] module"]
604#[doc(alias = "MRCC_GLB_CC0_CLR")]
605pub type MrccGlbCc0Clr = crate::Reg<mrcc_glb_cc0_clr::MrccGlbCc0ClrSpec>;
606#[doc = "AHB Clock Control Clear 0"]
607pub mod mrcc_glb_cc0_clr;
608#[doc = "MRCC_GLB_CC1 (rw) register accessor: AHB Clock Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc1`] module"]
609#[doc(alias = "MRCC_GLB_CC1")]
610pub type MrccGlbCc1 = crate::Reg<mrcc_glb_cc1::MrccGlbCc1Spec>;
611#[doc = "AHB Clock Control 1"]
612pub mod mrcc_glb_cc1;
613#[doc = "MRCC_GLB_CC1_SET (w) register accessor: AHB Clock Control Set 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc1_set`] module"]
614#[doc(alias = "MRCC_GLB_CC1_SET")]
615pub type MrccGlbCc1Set = crate::Reg<mrcc_glb_cc1_set::MrccGlbCc1SetSpec>;
616#[doc = "AHB Clock Control Set 1"]
617pub mod mrcc_glb_cc1_set;
618#[doc = "MRCC_GLB_CC1_CLR (w) register accessor: AHB Clock Control Clear 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc1_clr`] module"]
619#[doc(alias = "MRCC_GLB_CC1_CLR")]
620pub type MrccGlbCc1Clr = crate::Reg<mrcc_glb_cc1_clr::MrccGlbCc1ClrSpec>;
621#[doc = "AHB Clock Control Clear 1"]
622pub mod mrcc_glb_cc1_clr;
623#[doc = "MRCC_GLB_CC2 (rw) register accessor: AHB Clock Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc2`] module"]
624#[doc(alias = "MRCC_GLB_CC2")]
625pub type MrccGlbCc2 = crate::Reg<mrcc_glb_cc2::MrccGlbCc2Spec>;
626#[doc = "AHB Clock Control 2"]
627pub mod mrcc_glb_cc2;
628#[doc = "MRCC_GLB_CC2_SET (w) register accessor: AHB Clock Control Set 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc2_set`] module"]
629#[doc(alias = "MRCC_GLB_CC2_SET")]
630pub type MrccGlbCc2Set = crate::Reg<mrcc_glb_cc2_set::MrccGlbCc2SetSpec>;
631#[doc = "AHB Clock Control Set 2"]
632pub mod mrcc_glb_cc2_set;
633#[doc = "MRCC_GLB_CC2_CLR (w) register accessor: AHB Clock Control Clear 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc2_clr`] module"]
634#[doc(alias = "MRCC_GLB_CC2_CLR")]
635pub type MrccGlbCc2Clr = crate::Reg<mrcc_glb_cc2_clr::MrccGlbCc2ClrSpec>;
636#[doc = "AHB Clock Control Clear 2"]
637pub mod mrcc_glb_cc2_clr;
638#[doc = "MRCC_GLB_ACC0 (rw) register accessor: Control Automatic Clock Gating 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_acc0`] module"]
639#[doc(alias = "MRCC_GLB_ACC0")]
640pub type MrccGlbAcc0 = crate::Reg<mrcc_glb_acc0::MrccGlbAcc0Spec>;
641#[doc = "Control Automatic Clock Gating 0"]
642pub mod mrcc_glb_acc0;
643#[doc = "MRCC_GLB_ACC1 (rw) register accessor: Control Automatic Clock Gating 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_acc1`] module"]
644#[doc(alias = "MRCC_GLB_ACC1")]
645pub type MrccGlbAcc1 = crate::Reg<mrcc_glb_acc1::MrccGlbAcc1Spec>;
646#[doc = "Control Automatic Clock Gating 1"]
647pub mod mrcc_glb_acc1;
648#[doc = "MRCC_GLB_ACC2 (rw) register accessor: Control Automatic Clock Gating 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_acc2`] module"]
649#[doc(alias = "MRCC_GLB_ACC2")]
650pub type MrccGlbAcc2 = crate::Reg<mrcc_glb_acc2::MrccGlbAcc2Spec>;
651#[doc = "Control Automatic Clock Gating 2"]
652pub mod mrcc_glb_acc2;
653#[doc = "MRCC_I3C0_FCLK_CLKSEL (rw) register accessor: I3C0_FCLK clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_i3c0_fclk_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_i3c0_fclk_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_i3c0_fclk_clksel`] module"]
654#[doc(alias = "MRCC_I3C0_FCLK_CLKSEL")]
655pub type MrccI3c0FclkClksel = crate::Reg<mrcc_i3c0_fclk_clksel::MrccI3c0FclkClkselSpec>;
656#[doc = "I3C0_FCLK clock selection control"]
657pub mod mrcc_i3c0_fclk_clksel;
658#[doc = "MRCC_I3C0_FCLK_CLKDIV (rw) register accessor: I3C0_FCLK clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_i3c0_fclk_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_i3c0_fclk_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_i3c0_fclk_clkdiv`] module"]
659#[doc(alias = "MRCC_I3C0_FCLK_CLKDIV")]
660pub type MrccI3c0FclkClkdiv = crate::Reg<mrcc_i3c0_fclk_clkdiv::MrccI3c0FclkClkdivSpec>;
661#[doc = "I3C0_FCLK clock divider control"]
662pub mod mrcc_i3c0_fclk_clkdiv;
663#[doc = "MRCC_CTIMER0_CLKSEL (rw) register accessor: CTIMER0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer0_clksel`] module"]
664#[doc(alias = "MRCC_CTIMER0_CLKSEL")]
665pub type MrccCtimer0Clksel = crate::Reg<mrcc_ctimer0_clksel::MrccCtimer0ClkselSpec>;
666#[doc = "CTIMER0 clock selection control"]
667pub mod mrcc_ctimer0_clksel;
668#[doc = "MRCC_CTIMER0_CLKDIV (rw) register accessor: CTIMER0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer0_clkdiv`] module"]
669#[doc(alias = "MRCC_CTIMER0_CLKDIV")]
670pub type MrccCtimer0Clkdiv = crate::Reg<mrcc_ctimer0_clkdiv::MrccCtimer0ClkdivSpec>;
671#[doc = "CTIMER0 clock divider control"]
672pub mod mrcc_ctimer0_clkdiv;
673pub use mrcc_ctimer0_clkdiv as mrcc_ctimer1_clkdiv;
674pub use mrcc_ctimer0_clkdiv as mrcc_ctimer2_clkdiv;
675pub use mrcc_ctimer0_clkdiv as mrcc_ctimer3_clkdiv;
676pub use mrcc_ctimer0_clkdiv as mrcc_ctimer4_clkdiv;
677pub use mrcc_ctimer0_clksel as mrcc_ctimer1_clksel;
678pub use mrcc_ctimer0_clksel as mrcc_ctimer2_clksel;
679pub use mrcc_ctimer0_clksel as mrcc_ctimer3_clksel;
680pub use mrcc_ctimer0_clksel as mrcc_ctimer4_clksel;
681pub use MrccCtimer0Clkdiv as MrccCtimer1Clkdiv;
682pub use MrccCtimer0Clkdiv as MrccCtimer2Clkdiv;
683pub use MrccCtimer0Clkdiv as MrccCtimer3Clkdiv;
684pub use MrccCtimer0Clkdiv as MrccCtimer4Clkdiv;
685pub use MrccCtimer0Clksel as MrccCtimer1Clksel;
686pub use MrccCtimer0Clksel as MrccCtimer2Clksel;
687pub use MrccCtimer0Clksel as MrccCtimer3Clksel;
688pub use MrccCtimer0Clksel as MrccCtimer4Clksel;
689#[doc = "MRCC_WWDT0_CLKDIV (rw) register accessor: WWDT0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_wwdt0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_wwdt0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_wwdt0_clkdiv`] module"]
690#[doc(alias = "MRCC_WWDT0_CLKDIV")]
691pub type MrccWwdt0Clkdiv = crate::Reg<mrcc_wwdt0_clkdiv::MrccWwdt0ClkdivSpec>;
692#[doc = "WWDT0 clock divider control"]
693pub mod mrcc_wwdt0_clkdiv;
694#[doc = "MRCC_FLEXIO0_CLKSEL (rw) register accessor: FLEXIO0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexio0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexio0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexio0_clksel`] module"]
695#[doc(alias = "MRCC_FLEXIO0_CLKSEL")]
696pub type MrccFlexio0Clksel = crate::Reg<mrcc_flexio0_clksel::MrccFlexio0ClkselSpec>;
697#[doc = "FLEXIO0 clock selection control"]
698pub mod mrcc_flexio0_clksel;
699#[doc = "MRCC_FLEXIO0_CLKDIV (rw) register accessor: FLEXIO0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexio0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexio0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexio0_clkdiv`] module"]
700#[doc(alias = "MRCC_FLEXIO0_CLKDIV")]
701pub type MrccFlexio0Clkdiv = crate::Reg<mrcc_flexio0_clkdiv::MrccFlexio0ClkdivSpec>;
702#[doc = "FLEXIO0 clock divider control"]
703pub mod mrcc_flexio0_clkdiv;
704#[doc = "MRCC_LPI2C0_CLKSEL (rw) register accessor: LPI2C0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c0_clksel`] module"]
705#[doc(alias = "MRCC_LPI2C0_CLKSEL")]
706pub type MrccLpi2c0Clksel = crate::Reg<mrcc_lpi2c0_clksel::MrccLpi2c0ClkselSpec>;
707#[doc = "LPI2C0 clock selection control"]
708pub mod mrcc_lpi2c0_clksel;
709#[doc = "MRCC_LPI2C0_CLKDIV (rw) register accessor: LPI2C0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c0_clkdiv`] module"]
710#[doc(alias = "MRCC_LPI2C0_CLKDIV")]
711pub type MrccLpi2c0Clkdiv = crate::Reg<mrcc_lpi2c0_clkdiv::MrccLpi2c0ClkdivSpec>;
712#[doc = "LPI2C0 clock divider control"]
713pub mod mrcc_lpi2c0_clkdiv;
714pub use mrcc_lpi2c0_clkdiv as mrcc_lpi2c1_clkdiv;
715pub use mrcc_lpi2c0_clksel as mrcc_lpi2c1_clksel;
716pub use MrccLpi2c0Clkdiv as MrccLpi2c1Clkdiv;
717pub use MrccLpi2c0Clksel as MrccLpi2c1Clksel;
718#[doc = "MRCC_LPSPI0_CLKSEL (rw) register accessor: LPSPI0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpspi0_clksel`] module"]
719#[doc(alias = "MRCC_LPSPI0_CLKSEL")]
720pub type MrccLpspi0Clksel = crate::Reg<mrcc_lpspi0_clksel::MrccLpspi0ClkselSpec>;
721#[doc = "LPSPI0 clock selection control"]
722pub mod mrcc_lpspi0_clksel;
723#[doc = "MRCC_LPSPI0_CLKDIV (rw) register accessor: LPSPI0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpspi0_clkdiv`] module"]
724#[doc(alias = "MRCC_LPSPI0_CLKDIV")]
725pub type MrccLpspi0Clkdiv = crate::Reg<mrcc_lpspi0_clkdiv::MrccLpspi0ClkdivSpec>;
726#[doc = "LPSPI0 clock divider control"]
727pub mod mrcc_lpspi0_clkdiv;
728pub use mrcc_lpspi0_clkdiv as mrcc_lpspi1_clkdiv;
729pub use mrcc_lpspi0_clksel as mrcc_lpspi1_clksel;
730pub use MrccLpspi0Clkdiv as MrccLpspi1Clkdiv;
731pub use MrccLpspi0Clksel as MrccLpspi1Clksel;
732#[doc = "MRCC_LPUART0_CLKSEL (rw) register accessor: LPUART0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart0_clksel`] module"]
733#[doc(alias = "MRCC_LPUART0_CLKSEL")]
734pub type MrccLpuart0Clksel = crate::Reg<mrcc_lpuart0_clksel::MrccLpuart0ClkselSpec>;
735#[doc = "LPUART0 clock selection control"]
736pub mod mrcc_lpuart0_clksel;
737#[doc = "MRCC_LPUART0_CLKDIV (rw) register accessor: LPUART0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart0_clkdiv`] module"]
738#[doc(alias = "MRCC_LPUART0_CLKDIV")]
739pub type MrccLpuart0Clkdiv = crate::Reg<mrcc_lpuart0_clkdiv::MrccLpuart0ClkdivSpec>;
740#[doc = "LPUART0 clock divider control"]
741pub mod mrcc_lpuart0_clkdiv;
742pub use mrcc_lpuart0_clkdiv as mrcc_lpuart1_clkdiv;
743pub use mrcc_lpuart0_clkdiv as mrcc_lpuart2_clkdiv;
744pub use mrcc_lpuart0_clkdiv as mrcc_lpuart3_clkdiv;
745pub use mrcc_lpuart0_clkdiv as mrcc_lpuart4_clkdiv;
746pub use mrcc_lpuart0_clksel as mrcc_lpuart1_clksel;
747pub use mrcc_lpuart0_clksel as mrcc_lpuart2_clksel;
748pub use mrcc_lpuart0_clksel as mrcc_lpuart3_clksel;
749pub use mrcc_lpuart0_clksel as mrcc_lpuart4_clksel;
750pub use MrccLpuart0Clkdiv as MrccLpuart1Clkdiv;
751pub use MrccLpuart0Clkdiv as MrccLpuart2Clkdiv;
752pub use MrccLpuart0Clkdiv as MrccLpuart3Clkdiv;
753pub use MrccLpuart0Clkdiv as MrccLpuart4Clkdiv;
754pub use MrccLpuart0Clksel as MrccLpuart1Clksel;
755pub use MrccLpuart0Clksel as MrccLpuart2Clksel;
756pub use MrccLpuart0Clksel as MrccLpuart3Clksel;
757pub use MrccLpuart0Clksel as MrccLpuart4Clksel;
758#[doc = "MRCC_USB0_CLKSEL (rw) register accessor: USB0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_usb0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_usb0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_usb0_clksel`] module"]
759#[doc(alias = "MRCC_USB0_CLKSEL")]
760pub type MrccUsb0Clksel = crate::Reg<mrcc_usb0_clksel::MrccUsb0ClkselSpec>;
761#[doc = "USB0 clock selection control"]
762pub mod mrcc_usb0_clksel;
763#[doc = "MRCC_USB0_CLKDIV (rw) register accessor: USB0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_usb0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_usb0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_usb0_clkdiv`] module"]
764#[doc(alias = "MRCC_USB0_CLKDIV")]
765pub type MrccUsb0Clkdiv = crate::Reg<mrcc_usb0_clkdiv::MrccUsb0ClkdivSpec>;
766#[doc = "USB0 clock divider control"]
767pub mod mrcc_usb0_clkdiv;
768#[doc = "MRCC_LPTMR0_CLKSEL (rw) register accessor: LPTMR0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lptmr0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lptmr0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lptmr0_clksel`] module"]
769#[doc(alias = "MRCC_LPTMR0_CLKSEL")]
770pub type MrccLptmr0Clksel = crate::Reg<mrcc_lptmr0_clksel::MrccLptmr0ClkselSpec>;
771#[doc = "LPTMR0 clock selection control"]
772pub mod mrcc_lptmr0_clksel;
773#[doc = "MRCC_LPTMR0_CLKDIV (rw) register accessor: LPTMR0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lptmr0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lptmr0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lptmr0_clkdiv`] module"]
774#[doc(alias = "MRCC_LPTMR0_CLKDIV")]
775pub type MrccLptmr0Clkdiv = crate::Reg<mrcc_lptmr0_clkdiv::MrccLptmr0ClkdivSpec>;
776#[doc = "LPTMR0 clock divider control"]
777pub mod mrcc_lptmr0_clkdiv;
778#[doc = "MRCC_OSTIMER0_CLKSEL (rw) register accessor: OSTIMER0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ostimer0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ostimer0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ostimer0_clksel`] module"]
779#[doc(alias = "MRCC_OSTIMER0_CLKSEL")]
780pub type MrccOstimer0Clksel = crate::Reg<mrcc_ostimer0_clksel::MrccOstimer0ClkselSpec>;
781#[doc = "OSTIMER0 clock selection control"]
782pub mod mrcc_ostimer0_clksel;
783#[doc = "MRCC_ADC_CLKSEL (rw) register accessor: ADCx clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_adc_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_adc_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_adc_clksel`] module"]
784#[doc(alias = "MRCC_ADC_CLKSEL")]
785pub type MrccAdcClksel = crate::Reg<mrcc_adc_clksel::MrccAdcClkselSpec>;
786#[doc = "ADCx clock selection control"]
787pub mod mrcc_adc_clksel;
788#[doc = "MRCC_ADC_CLKDIV (rw) register accessor: ADCx clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_adc_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_adc_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_adc_clkdiv`] module"]
789#[doc(alias = "MRCC_ADC_CLKDIV")]
790pub type MrccAdcClkdiv = crate::Reg<mrcc_adc_clkdiv::MrccAdcClkdivSpec>;
791#[doc = "ADCx clock divider control"]
792pub mod mrcc_adc_clkdiv;
793#[doc = "MRCC_CMP0_FUNC_CLKDIV (rw) register accessor: CMP0_FUNC clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_func_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_func_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp0_func_clkdiv`] module"]
794#[doc(alias = "MRCC_CMP0_FUNC_CLKDIV")]
795pub type MrccCmp0FuncClkdiv = crate::Reg<mrcc_cmp0_func_clkdiv::MrccCmp0FuncClkdivSpec>;
796#[doc = "CMP0_FUNC clock divider control"]
797pub mod mrcc_cmp0_func_clkdiv;
798#[doc = "MRCC_CMP0_RR_CLKSEL (rw) register accessor: CMP0_RR clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_rr_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_rr_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp0_rr_clksel`] module"]
799#[doc(alias = "MRCC_CMP0_RR_CLKSEL")]
800pub type MrccCmp0RrClksel = crate::Reg<mrcc_cmp0_rr_clksel::MrccCmp0RrClkselSpec>;
801#[doc = "CMP0_RR clock selection control"]
802pub mod mrcc_cmp0_rr_clksel;
803#[doc = "MRCC_CMP0_RR_CLKDIV (rw) register accessor: CMP0_RR clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_rr_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_rr_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp0_rr_clkdiv`] module"]
804#[doc(alias = "MRCC_CMP0_RR_CLKDIV")]
805pub type MrccCmp0RrClkdiv = crate::Reg<mrcc_cmp0_rr_clkdiv::MrccCmp0RrClkdivSpec>;
806#[doc = "CMP0_RR clock divider control"]
807pub mod mrcc_cmp0_rr_clkdiv;
808pub use mrcc_cmp0_func_clkdiv as mrcc_cmp1_func_clkdiv;
809pub use mrcc_cmp0_func_clkdiv as mrcc_cmp2_func_clkdiv;
810pub use mrcc_cmp0_rr_clkdiv as mrcc_cmp1_rr_clkdiv;
811pub use mrcc_cmp0_rr_clkdiv as mrcc_cmp2_rr_clkdiv;
812pub use mrcc_cmp0_rr_clksel as mrcc_cmp1_rr_clksel;
813pub use mrcc_cmp0_rr_clksel as mrcc_cmp2_rr_clksel;
814pub use MrccCmp0FuncClkdiv as MrccCmp1FuncClkdiv;
815pub use MrccCmp0FuncClkdiv as MrccCmp2FuncClkdiv;
816pub use MrccCmp0RrClkdiv as MrccCmp1RrClkdiv;
817pub use MrccCmp0RrClkdiv as MrccCmp2RrClkdiv;
818pub use MrccCmp0RrClksel as MrccCmp1RrClksel;
819pub use MrccCmp0RrClksel as MrccCmp2RrClksel;
820#[doc = "MRCC_DAC0_CLKSEL (rw) register accessor: DAC0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dac0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dac0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_dac0_clksel`] module"]
821#[doc(alias = "MRCC_DAC0_CLKSEL")]
822pub type MrccDac0Clksel = crate::Reg<mrcc_dac0_clksel::MrccDac0ClkselSpec>;
823#[doc = "DAC0 clock selection control"]
824pub mod mrcc_dac0_clksel;
825#[doc = "MRCC_DAC0_CLKDIV (rw) register accessor: DAC0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dac0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dac0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_dac0_clkdiv`] module"]
826#[doc(alias = "MRCC_DAC0_CLKDIV")]
827pub type MrccDac0Clkdiv = crate::Reg<mrcc_dac0_clkdiv::MrccDac0ClkdivSpec>;
828#[doc = "DAC0 clock divider control"]
829pub mod mrcc_dac0_clkdiv;
830#[doc = "MRCC_FLEXCAN0_CLKSEL (rw) register accessor: FLEXCAN0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexcan0_clksel`] module"]
831#[doc(alias = "MRCC_FLEXCAN0_CLKSEL")]
832pub type MrccFlexcan0Clksel = crate::Reg<mrcc_flexcan0_clksel::MrccFlexcan0ClkselSpec>;
833#[doc = "FLEXCAN0 clock selection control"]
834pub mod mrcc_flexcan0_clksel;
835#[doc = "MRCC_FLEXCAN0_CLKDIV (rw) register accessor: FLEXCAN0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexcan0_clkdiv`] module"]
836#[doc(alias = "MRCC_FLEXCAN0_CLKDIV")]
837pub type MrccFlexcan0Clkdiv = crate::Reg<mrcc_flexcan0_clkdiv::MrccFlexcan0ClkdivSpec>;
838#[doc = "FLEXCAN0 clock divider control"]
839pub mod mrcc_flexcan0_clkdiv;
840pub use mrcc_flexcan0_clkdiv as mrcc_flexcan1_clkdiv;
841pub use mrcc_flexcan0_clksel as mrcc_flexcan1_clksel;
842pub use mrcc_lpi2c0_clkdiv as mrcc_lpi2c2_clkdiv;
843pub use mrcc_lpi2c0_clkdiv as mrcc_lpi2c3_clkdiv;
844pub use mrcc_lpi2c0_clksel as mrcc_lpi2c2_clksel;
845pub use mrcc_lpi2c0_clksel as mrcc_lpi2c3_clksel;
846pub use mrcc_lpuart0_clkdiv as mrcc_lpuart5_clkdiv;
847pub use mrcc_lpuart0_clksel as mrcc_lpuart5_clksel;
848pub use MrccFlexcan0Clkdiv as MrccFlexcan1Clkdiv;
849pub use MrccFlexcan0Clksel as MrccFlexcan1Clksel;
850pub use MrccLpi2c0Clkdiv as MrccLpi2c2Clkdiv;
851pub use MrccLpi2c0Clkdiv as MrccLpi2c3Clkdiv;
852pub use MrccLpi2c0Clksel as MrccLpi2c2Clksel;
853pub use MrccLpi2c0Clksel as MrccLpi2c3Clksel;
854pub use MrccLpuart0Clkdiv as MrccLpuart5Clkdiv;
855pub use MrccLpuart0Clksel as MrccLpuart5Clksel;
856#[doc = "MRCC_DBG_TRACE_CLKSEL (rw) register accessor: DBG_TRACE clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dbg_trace_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dbg_trace_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_dbg_trace_clksel`] module"]
857#[doc(alias = "MRCC_DBG_TRACE_CLKSEL")]
858pub type MrccDbgTraceClksel = crate::Reg<mrcc_dbg_trace_clksel::MrccDbgTraceClkselSpec>;
859#[doc = "DBG_TRACE clock selection control"]
860pub mod mrcc_dbg_trace_clksel;
861#[doc = "MRCC_DBG_TRACE_CLKDIV (rw) register accessor: DBG_TRACE clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dbg_trace_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dbg_trace_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_dbg_trace_clkdiv`] module"]
862#[doc(alias = "MRCC_DBG_TRACE_CLKDIV")]
863pub type MrccDbgTraceClkdiv = crate::Reg<mrcc_dbg_trace_clkdiv::MrccDbgTraceClkdivSpec>;
864#[doc = "DBG_TRACE clock divider control"]
865pub mod mrcc_dbg_trace_clkdiv;
866#[doc = "MRCC_CLKOUT_CLKSEL (rw) register accessor: CLKOUT clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_clkout_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_clkout_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_clkout_clksel`] module"]
867#[doc(alias = "MRCC_CLKOUT_CLKSEL")]
868pub type MrccClkoutClksel = crate::Reg<mrcc_clkout_clksel::MrccClkoutClkselSpec>;
869#[doc = "CLKOUT clock selection control"]
870pub mod mrcc_clkout_clksel;
871#[doc = "MRCC_CLKOUT_CLKDIV (rw) register accessor: CLKOUT clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_clkout_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_clkout_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_clkout_clkdiv`] module"]
872#[doc(alias = "MRCC_CLKOUT_CLKDIV")]
873pub type MrccClkoutClkdiv = crate::Reg<mrcc_clkout_clkdiv::MrccClkoutClkdivSpec>;
874#[doc = "CLKOUT clock divider control"]
875pub mod mrcc_clkout_clkdiv;
876#[doc = "MRCC_SYSTICK_CLKSEL (rw) register accessor: SYSTICK clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_systick_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_systick_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_systick_clksel`] module"]
877#[doc(alias = "MRCC_SYSTICK_CLKSEL")]
878pub type MrccSystickClksel = crate::Reg<mrcc_systick_clksel::MrccSystickClkselSpec>;
879#[doc = "SYSTICK clock selection control"]
880pub mod mrcc_systick_clksel;
881#[doc = "MRCC_SYSTICK_CLKDIV (rw) register accessor: SYSTICK clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_systick_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_systick_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_systick_clkdiv`] module"]
882#[doc(alias = "MRCC_SYSTICK_CLKDIV")]
883pub type MrccSystickClkdiv = crate::Reg<mrcc_systick_clkdiv::MrccSystickClkdivSpec>;
884#[doc = "SYSTICK clock divider control"]
885pub mod mrcc_systick_clkdiv;
mcxa_pac/mrcc0.rs

mcxa_pac/
mrcc0.rs
