mcxa_pac/lpspi0/
ccr.rs

1#[doc = "Register `CCR` reader"]
2pub type R = crate::R<CcrSpec>;
3#[doc = "Register `CCR` writer"]
4pub type W = crate::W<CcrSpec>;
5#[doc = "Field `SCKDIV` reader - SCK Divider"]
6pub type SckdivR = crate::FieldReader;
7#[doc = "Field `SCKDIV` writer - SCK Divider"]
8pub type SckdivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `DBT` reader - Delay Between Transfers"]
10pub type DbtR = crate::FieldReader;
11#[doc = "Field `DBT` writer - Delay Between Transfers"]
12pub type DbtW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `PCSSCK` reader - PCS-to-SCK Delay"]
14pub type PcssckR = crate::FieldReader;
15#[doc = "Field `PCSSCK` writer - PCS-to-SCK Delay"]
16pub type PcssckW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17#[doc = "Field `SCKPCS` reader - SCK-to-PCS Delay"]
18pub type SckpcsR = crate::FieldReader;
19#[doc = "Field `SCKPCS` writer - SCK-to-PCS Delay"]
20pub type SckpcsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
21impl R {
22    #[doc = "Bits 0:7 - SCK Divider"]
23    #[inline(always)]
24    pub fn sckdiv(&self) -> SckdivR {
25        SckdivR::new((self.bits & 0xff) as u8)
26    }
27    #[doc = "Bits 8:15 - Delay Between Transfers"]
28    #[inline(always)]
29    pub fn dbt(&self) -> DbtR {
30        DbtR::new(((self.bits >> 8) & 0xff) as u8)
31    }
32    #[doc = "Bits 16:23 - PCS-to-SCK Delay"]
33    #[inline(always)]
34    pub fn pcssck(&self) -> PcssckR {
35        PcssckR::new(((self.bits >> 16) & 0xff) as u8)
36    }
37    #[doc = "Bits 24:31 - SCK-to-PCS Delay"]
38    #[inline(always)]
39    pub fn sckpcs(&self) -> SckpcsR {
40        SckpcsR::new(((self.bits >> 24) & 0xff) as u8)
41    }
42}
43#[cfg(feature = "debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("CCR")
47            .field("sckdiv", &self.sckdiv())
48            .field("dbt", &self.dbt())
49            .field("pcssck", &self.pcssck())
50            .field("sckpcs", &self.sckpcs())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:7 - SCK Divider"]
56    #[inline(always)]
57    pub fn sckdiv(&mut self) -> SckdivW<'_, CcrSpec> {
58        SckdivW::new(self, 0)
59    }
60    #[doc = "Bits 8:15 - Delay Between Transfers"]
61    #[inline(always)]
62    pub fn dbt(&mut self) -> DbtW<'_, CcrSpec> {
63        DbtW::new(self, 8)
64    }
65    #[doc = "Bits 16:23 - PCS-to-SCK Delay"]
66    #[inline(always)]
67    pub fn pcssck(&mut self) -> PcssckW<'_, CcrSpec> {
68        PcssckW::new(self, 16)
69    }
70    #[doc = "Bits 24:31 - SCK-to-PCS Delay"]
71    #[inline(always)]
72    pub fn sckpcs(&mut self) -> SckpcsW<'_, CcrSpec> {
73        SckpcsW::new(self, 24)
74    }
75}
76#[doc = "Clock Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct CcrSpec;
78impl crate::RegisterSpec for CcrSpec {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`ccr::R`](R) reader structure"]
82impl crate::Readable for CcrSpec {}
83#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"]
84impl crate::Writable for CcrSpec {
85    type Safety = crate::Unsafe;
86}
87#[doc = "`reset()` method sets CCR to value 0"]
88impl crate::Resettable for CcrSpec {}
mcxa_pac/lpspi0/ccr.rs

mcxa_pac/lpspi0/
ccr.rs
