mcxa_pac/lpi2c0/
scfgr2.rs

1#[doc = "Register `SCFGR2` reader"]
2pub type R = crate::R<Scfgr2Spec>;
3#[doc = "Register `SCFGR2` writer"]
4pub type W = crate::W<Scfgr2Spec>;
5#[doc = "Field `CLKHOLD` reader - Clock Hold Time"]
6pub type ClkholdR = crate::FieldReader;
7#[doc = "Field `CLKHOLD` writer - Clock Hold Time"]
8pub type ClkholdW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `DATAVD` reader - Data Valid Delay"]
10pub type DatavdR = crate::FieldReader;
11#[doc = "Field `DATAVD` writer - Data Valid Delay"]
12pub type DatavdW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `FILTSCL` reader - Glitch Filter SCL"]
14pub type FiltsclR = crate::FieldReader;
15#[doc = "Field `FILTSCL` writer - Glitch Filter SCL"]
16pub type FiltsclW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17#[doc = "Field `FILTSDA` reader - Glitch Filter SDA"]
18pub type FiltsdaR = crate::FieldReader;
19#[doc = "Field `FILTSDA` writer - Glitch Filter SDA"]
20pub type FiltsdaW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21impl R {
22    #[doc = "Bits 0:3 - Clock Hold Time"]
23    #[inline(always)]
24    pub fn clkhold(&self) -> ClkholdR {
25        ClkholdR::new((self.bits & 0x0f) as u8)
26    }
27    #[doc = "Bits 8:13 - Data Valid Delay"]
28    #[inline(always)]
29    pub fn datavd(&self) -> DatavdR {
30        DatavdR::new(((self.bits >> 8) & 0x3f) as u8)
31    }
32    #[doc = "Bits 16:19 - Glitch Filter SCL"]
33    #[inline(always)]
34    pub fn filtscl(&self) -> FiltsclR {
35        FiltsclR::new(((self.bits >> 16) & 0x0f) as u8)
36    }
37    #[doc = "Bits 24:27 - Glitch Filter SDA"]
38    #[inline(always)]
39    pub fn filtsda(&self) -> FiltsdaR {
40        FiltsdaR::new(((self.bits >> 24) & 0x0f) as u8)
41    }
42}
43#[cfg(feature = "debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("SCFGR2")
47            .field("clkhold", &self.clkhold())
48            .field("datavd", &self.datavd())
49            .field("filtscl", &self.filtscl())
50            .field("filtsda", &self.filtsda())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:3 - Clock Hold Time"]
56    #[inline(always)]
57    pub fn clkhold(&mut self) -> ClkholdW<'_, Scfgr2Spec> {
58        ClkholdW::new(self, 0)
59    }
60    #[doc = "Bits 8:13 - Data Valid Delay"]
61    #[inline(always)]
62    pub fn datavd(&mut self) -> DatavdW<'_, Scfgr2Spec> {
63        DatavdW::new(self, 8)
64    }
65    #[doc = "Bits 16:19 - Glitch Filter SCL"]
66    #[inline(always)]
67    pub fn filtscl(&mut self) -> FiltsclW<'_, Scfgr2Spec> {
68        FiltsclW::new(self, 16)
69    }
70    #[doc = "Bits 24:27 - Glitch Filter SDA"]
71    #[inline(always)]
72    pub fn filtsda(&mut self) -> FiltsdaW<'_, Scfgr2Spec> {
73        FiltsdaW::new(self, 24)
74    }
75}
76#[doc = "Target Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct Scfgr2Spec;
78impl crate::RegisterSpec for Scfgr2Spec {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`scfgr2::R`](R) reader structure"]
82impl crate::Readable for Scfgr2Spec {}
83#[doc = "`write(|w| ..)` method takes [`scfgr2::W`](W) writer structure"]
84impl crate::Writable for Scfgr2Spec {
85    type Safety = crate::Unsafe;
86}
87#[doc = "`reset()` method sets SCFGR2 to value 0"]
88impl crate::Resettable for Scfgr2Spec {}
mcxa_pac/lpi2c0/scfgr2.rs

mcxa_pac/lpi2c0/
scfgr2.rs
