mcxa_pac/flexpwm0/
sm2ctrl2.rs

1#[doc = "Register `SM2CTRL2` reader"]
2pub type R = crate::R<Sm2ctrl2Spec>;
3#[doc = "Register `SM2CTRL2` writer"]
4pub type W = crate::W<Sm2ctrl2Spec>;
5#[doc = "Clock Source Select\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum ClkSel {
10    #[doc = "0: The IPBus clock is used as the clock for the local prescaler and counter."]
11    Ipbus = 0,
12    #[doc = "1: EXT_CLK is used as the clock for the local prescaler and counter."]
13    ExtClk = 1,
14    #[doc = "2: Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."]
15    AuxClk = 2,
16}
17impl From<ClkSel> for u8 {
18    #[inline(always)]
19    fn from(variant: ClkSel) -> Self {
20        variant as _
21    }
22}
23impl crate::FieldSpec for ClkSel {
24    type Ux = u8;
25}
26impl crate::IsEnum for ClkSel {}
27#[doc = "Field `CLK_SEL` reader - Clock Source Select"]
28pub type ClkSelR = crate::FieldReader<ClkSel>;
29impl ClkSelR {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> Option<ClkSel> {
33        match self.bits {
34            0 => Some(ClkSel::Ipbus),
35            1 => Some(ClkSel::ExtClk),
36            2 => Some(ClkSel::AuxClk),
37            _ => None,
38        }
39    }
40    #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."]
41    #[inline(always)]
42    pub fn is_ipbus(&self) -> bool {
43        *self == ClkSel::Ipbus
44    }
45    #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."]
46    #[inline(always)]
47    pub fn is_ext_clk(&self) -> bool {
48        *self == ClkSel::ExtClk
49    }
50    #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."]
51    #[inline(always)]
52    pub fn is_aux_clk(&self) -> bool {
53        *self == ClkSel::AuxClk
54    }
55}
56#[doc = "Field `CLK_SEL` writer - Clock Source Select"]
57pub type ClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, ClkSel>;
58impl<'a, REG> ClkSelW<'a, REG>
59where
60    REG: crate::Writable + crate::RegisterSpec,
61    REG::Ux: From<u8>,
62{
63    #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."]
64    #[inline(always)]
65    pub fn ipbus(self) -> &'a mut crate::W<REG> {
66        self.variant(ClkSel::Ipbus)
67    }
68    #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."]
69    #[inline(always)]
70    pub fn ext_clk(self) -> &'a mut crate::W<REG> {
71        self.variant(ClkSel::ExtClk)
72    }
73    #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."]
74    #[inline(always)]
75    pub fn aux_clk(self) -> &'a mut crate::W<REG> {
76        self.variant(ClkSel::AuxClk)
77    }
78}
79#[doc = "Reload Source Select\n\nValue on reset: 0"]
80#[cfg_attr(feature = "defmt", derive(defmt::Format))]
81#[derive(Clone, Copy, Debug, PartialEq, Eq)]
82pub enum ReloadSel {
83    #[doc = "0: The local RELOAD signal is used to reload registers."]
84    Local = 0,
85    #[doc = "1: The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."]
86    Master = 1,
87}
88impl From<ReloadSel> for bool {
89    #[inline(always)]
90    fn from(variant: ReloadSel) -> Self {
91        variant as u8 != 0
92    }
93}
94#[doc = "Field `RELOAD_SEL` reader - Reload Source Select"]
95pub type ReloadSelR = crate::BitReader<ReloadSel>;
96impl ReloadSelR {
97    #[doc = "Get enumerated values variant"]
98    #[inline(always)]
99    pub const fn variant(&self) -> ReloadSel {
100        match self.bits {
101            false => ReloadSel::Local,
102            true => ReloadSel::Master,
103        }
104    }
105    #[doc = "The local RELOAD signal is used to reload registers."]
106    #[inline(always)]
107    pub fn is_local(&self) -> bool {
108        *self == ReloadSel::Local
109    }
110    #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."]
111    #[inline(always)]
112    pub fn is_master(&self) -> bool {
113        *self == ReloadSel::Master
114    }
115}
116#[doc = "Field `RELOAD_SEL` writer - Reload Source Select"]
117pub type ReloadSelW<'a, REG> = crate::BitWriter<'a, REG, ReloadSel>;
118impl<'a, REG> ReloadSelW<'a, REG>
119where
120    REG: crate::Writable + crate::RegisterSpec,
121{
122    #[doc = "The local RELOAD signal is used to reload registers."]
123    #[inline(always)]
124    pub fn local(self) -> &'a mut crate::W<REG> {
125        self.variant(ReloadSel::Local)
126    }
127    #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."]
128    #[inline(always)]
129    pub fn master(self) -> &'a mut crate::W<REG> {
130        self.variant(ReloadSel::Master)
131    }
132}
133#[doc = "Force Select\n\nValue on reset: 0"]
134#[cfg_attr(feature = "defmt", derive(defmt::Format))]
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136#[repr(u8)]
137pub enum ForceSel {
138    #[doc = "0: The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."]
139    Local = 0,
140    #[doc = "1: The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."]
141    Master = 1,
142    #[doc = "2: The local reload signal from this submodule is used to force updates without regard to the state of LDOK."]
143    LocalReload = 2,
144    #[doc = "3: The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."]
145    MasterReload = 3,
146    #[doc = "4: The local sync signal from this submodule is used to force updates."]
147    LocalSync = 4,
148    #[doc = "5: The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."]
149    MasterSync = 5,
150    #[doc = "6: The external force signal, EXT_FORCE, from outside the PWM module causes updates."]
151    ExtForce = 6,
152    #[doc = "7: The external sync signal, EXT_SYNC, from outside the PWM module causes updates."]
153    ExtSync = 7,
154}
155impl From<ForceSel> for u8 {
156    #[inline(always)]
157    fn from(variant: ForceSel) -> Self {
158        variant as _
159    }
160}
161impl crate::FieldSpec for ForceSel {
162    type Ux = u8;
163}
164impl crate::IsEnum for ForceSel {}
165#[doc = "Field `FORCE_SEL` reader - Force Select"]
166pub type ForceSelR = crate::FieldReader<ForceSel>;
167impl ForceSelR {
168    #[doc = "Get enumerated values variant"]
169    #[inline(always)]
170    pub const fn variant(&self) -> ForceSel {
171        match self.bits {
172            0 => ForceSel::Local,
173            1 => ForceSel::Master,
174            2 => ForceSel::LocalReload,
175            3 => ForceSel::MasterReload,
176            4 => ForceSel::LocalSync,
177            5 => ForceSel::MasterSync,
178            6 => ForceSel::ExtForce,
179            7 => ForceSel::ExtSync,
180            _ => unreachable!(),
181        }
182    }
183    #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."]
184    #[inline(always)]
185    pub fn is_local(&self) -> bool {
186        *self == ForceSel::Local
187    }
188    #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."]
189    #[inline(always)]
190    pub fn is_master(&self) -> bool {
191        *self == ForceSel::Master
192    }
193    #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."]
194    #[inline(always)]
195    pub fn is_local_reload(&self) -> bool {
196        *self == ForceSel::LocalReload
197    }
198    #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."]
199    #[inline(always)]
200    pub fn is_master_reload(&self) -> bool {
201        *self == ForceSel::MasterReload
202    }
203    #[doc = "The local sync signal from this submodule is used to force updates."]
204    #[inline(always)]
205    pub fn is_local_sync(&self) -> bool {
206        *self == ForceSel::LocalSync
207    }
208    #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."]
209    #[inline(always)]
210    pub fn is_master_sync(&self) -> bool {
211        *self == ForceSel::MasterSync
212    }
213    #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."]
214    #[inline(always)]
215    pub fn is_ext_force(&self) -> bool {
216        *self == ForceSel::ExtForce
217    }
218    #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."]
219    #[inline(always)]
220    pub fn is_ext_sync(&self) -> bool {
221        *self == ForceSel::ExtSync
222    }
223}
224#[doc = "Field `FORCE_SEL` writer - Force Select"]
225pub type ForceSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, ForceSel, crate::Safe>;
226impl<'a, REG> ForceSelW<'a, REG>
227where
228    REG: crate::Writable + crate::RegisterSpec,
229    REG::Ux: From<u8>,
230{
231    #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."]
232    #[inline(always)]
233    pub fn local(self) -> &'a mut crate::W<REG> {
234        self.variant(ForceSel::Local)
235    }
236    #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."]
237    #[inline(always)]
238    pub fn master(self) -> &'a mut crate::W<REG> {
239        self.variant(ForceSel::Master)
240    }
241    #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."]
242    #[inline(always)]
243    pub fn local_reload(self) -> &'a mut crate::W<REG> {
244        self.variant(ForceSel::LocalReload)
245    }
246    #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."]
247    #[inline(always)]
248    pub fn master_reload(self) -> &'a mut crate::W<REG> {
249        self.variant(ForceSel::MasterReload)
250    }
251    #[doc = "The local sync signal from this submodule is used to force updates."]
252    #[inline(always)]
253    pub fn local_sync(self) -> &'a mut crate::W<REG> {
254        self.variant(ForceSel::LocalSync)
255    }
256    #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."]
257    #[inline(always)]
258    pub fn master_sync(self) -> &'a mut crate::W<REG> {
259        self.variant(ForceSel::MasterSync)
260    }
261    #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."]
262    #[inline(always)]
263    pub fn ext_force(self) -> &'a mut crate::W<REG> {
264        self.variant(ForceSel::ExtForce)
265    }
266    #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."]
267    #[inline(always)]
268    pub fn ext_sync(self) -> &'a mut crate::W<REG> {
269        self.variant(ForceSel::ExtSync)
270    }
271}
272#[doc = "Field `FORCE` reader - Force Initialization"]
273pub type ForceR = crate::BitReader;
274#[doc = "Field `FORCE` writer - Force Initialization"]
275pub type ForceW<'a, REG> = crate::BitWriter<'a, REG>;
276#[doc = "Force Enable\n\nValue on reset: 0"]
277#[cfg_attr(feature = "defmt", derive(defmt::Format))]
278#[derive(Clone, Copy, Debug, PartialEq, Eq)]
279pub enum Frcen {
280    #[doc = "0: Initialization from a FORCE_OUT is disabled."]
281    Disabled = 0,
282    #[doc = "1: Initialization from a FORCE_OUT is enabled."]
283    Enabled = 1,
284}
285impl From<Frcen> for bool {
286    #[inline(always)]
287    fn from(variant: Frcen) -> Self {
288        variant as u8 != 0
289    }
290}
291#[doc = "Field `FRCEN` reader - Force Enable"]
292pub type FrcenR = crate::BitReader<Frcen>;
293impl FrcenR {
294    #[doc = "Get enumerated values variant"]
295    #[inline(always)]
296    pub const fn variant(&self) -> Frcen {
297        match self.bits {
298            false => Frcen::Disabled,
299            true => Frcen::Enabled,
300        }
301    }
302    #[doc = "Initialization from a FORCE_OUT is disabled."]
303    #[inline(always)]
304    pub fn is_disabled(&self) -> bool {
305        *self == Frcen::Disabled
306    }
307    #[doc = "Initialization from a FORCE_OUT is enabled."]
308    #[inline(always)]
309    pub fn is_enabled(&self) -> bool {
310        *self == Frcen::Enabled
311    }
312}
313#[doc = "Field `FRCEN` writer - Force Enable"]
314pub type FrcenW<'a, REG> = crate::BitWriter<'a, REG, Frcen>;
315impl<'a, REG> FrcenW<'a, REG>
316where
317    REG: crate::Writable + crate::RegisterSpec,
318{
319    #[doc = "Initialization from a FORCE_OUT is disabled."]
320    #[inline(always)]
321    pub fn disabled(self) -> &'a mut crate::W<REG> {
322        self.variant(Frcen::Disabled)
323    }
324    #[doc = "Initialization from a FORCE_OUT is enabled."]
325    #[inline(always)]
326    pub fn enabled(self) -> &'a mut crate::W<REG> {
327        self.variant(Frcen::Enabled)
328    }
329}
330#[doc = "Initialization Control Select\n\nValue on reset: 0"]
331#[cfg_attr(feature = "defmt", derive(defmt::Format))]
332#[derive(Clone, Copy, Debug, PartialEq, Eq)]
333#[repr(u8)]
334pub enum InitSel {
335    #[doc = "0: Local sync (PWM_X) causes initialization."]
336    PwmX = 0,
337    #[doc = "1: Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."]
338    MasterReload = 1,
339    #[doc = "2: Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."]
340    MasterSync = 2,
341    #[doc = "3: EXT_SYNC causes initialization."]
342    ExtSync = 3,
343}
344impl From<InitSel> for u8 {
345    #[inline(always)]
346    fn from(variant: InitSel) -> Self {
347        variant as _
348    }
349}
350impl crate::FieldSpec for InitSel {
351    type Ux = u8;
352}
353impl crate::IsEnum for InitSel {}
354#[doc = "Field `INIT_SEL` reader - Initialization Control Select"]
355pub type InitSelR = crate::FieldReader<InitSel>;
356impl InitSelR {
357    #[doc = "Get enumerated values variant"]
358    #[inline(always)]
359    pub const fn variant(&self) -> InitSel {
360        match self.bits {
361            0 => InitSel::PwmX,
362            1 => InitSel::MasterReload,
363            2 => InitSel::MasterSync,
364            3 => InitSel::ExtSync,
365            _ => unreachable!(),
366        }
367    }
368    #[doc = "Local sync (PWM_X) causes initialization."]
369    #[inline(always)]
370    pub fn is_pwm_x(&self) -> bool {
371        *self == InitSel::PwmX
372    }
373    #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."]
374    #[inline(always)]
375    pub fn is_master_reload(&self) -> bool {
376        *self == InitSel::MasterReload
377    }
378    #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."]
379    #[inline(always)]
380    pub fn is_master_sync(&self) -> bool {
381        *self == InitSel::MasterSync
382    }
383    #[doc = "EXT_SYNC causes initialization."]
384    #[inline(always)]
385    pub fn is_ext_sync(&self) -> bool {
386        *self == InitSel::ExtSync
387    }
388}
389#[doc = "Field `INIT_SEL` writer - Initialization Control Select"]
390pub type InitSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, InitSel, crate::Safe>;
391impl<'a, REG> InitSelW<'a, REG>
392where
393    REG: crate::Writable + crate::RegisterSpec,
394    REG::Ux: From<u8>,
395{
396    #[doc = "Local sync (PWM_X) causes initialization."]
397    #[inline(always)]
398    pub fn pwm_x(self) -> &'a mut crate::W<REG> {
399        self.variant(InitSel::PwmX)
400    }
401    #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."]
402    #[inline(always)]
403    pub fn master_reload(self) -> &'a mut crate::W<REG> {
404        self.variant(InitSel::MasterReload)
405    }
406    #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."]
407    #[inline(always)]
408    pub fn master_sync(self) -> &'a mut crate::W<REG> {
409        self.variant(InitSel::MasterSync)
410    }
411    #[doc = "EXT_SYNC causes initialization."]
412    #[inline(always)]
413    pub fn ext_sync(self) -> &'a mut crate::W<REG> {
414        self.variant(InitSel::ExtSync)
415    }
416}
417#[doc = "Field `PWMX_INIT` reader - PWM_X Initial Value"]
418pub type PwmxInitR = crate::BitReader;
419#[doc = "Field `PWMX_INIT` writer - PWM_X Initial Value"]
420pub type PwmxInitW<'a, REG> = crate::BitWriter<'a, REG>;
421#[doc = "Field `PWM45_INIT` reader - PWM45 Initial Value"]
422pub type Pwm45InitR = crate::BitReader;
423#[doc = "Field `PWM45_INIT` writer - PWM45 Initial Value"]
424pub type Pwm45InitW<'a, REG> = crate::BitWriter<'a, REG>;
425#[doc = "Field `PWM23_INIT` reader - PWM23 Initial Value"]
426pub type Pwm23InitR = crate::BitReader;
427#[doc = "Field `PWM23_INIT` writer - PWM23 Initial Value"]
428pub type Pwm23InitW<'a, REG> = crate::BitWriter<'a, REG>;
429#[doc = "Independent or Complementary Pair Operation\n\nValue on reset: 0"]
430#[cfg_attr(feature = "defmt", derive(defmt::Format))]
431#[derive(Clone, Copy, Debug, PartialEq, Eq)]
432pub enum Indep {
433    #[doc = "0: PWM_A and PWM_B form a complementary PWM pair."]
434    Complementary = 0,
435    #[doc = "1: PWM_A and PWM_B outputs are independent PWMs."]
436    Independent = 1,
437}
438impl From<Indep> for bool {
439    #[inline(always)]
440    fn from(variant: Indep) -> Self {
441        variant as u8 != 0
442    }
443}
444#[doc = "Field `INDEP` reader - Independent or Complementary Pair Operation"]
445pub type IndepR = crate::BitReader<Indep>;
446impl IndepR {
447    #[doc = "Get enumerated values variant"]
448    #[inline(always)]
449    pub const fn variant(&self) -> Indep {
450        match self.bits {
451            false => Indep::Complementary,
452            true => Indep::Independent,
453        }
454    }
455    #[doc = "PWM_A and PWM_B form a complementary PWM pair."]
456    #[inline(always)]
457    pub fn is_complementary(&self) -> bool {
458        *self == Indep::Complementary
459    }
460    #[doc = "PWM_A and PWM_B outputs are independent PWMs."]
461    #[inline(always)]
462    pub fn is_independent(&self) -> bool {
463        *self == Indep::Independent
464    }
465}
466#[doc = "Field `INDEP` writer - Independent or Complementary Pair Operation"]
467pub type IndepW<'a, REG> = crate::BitWriter<'a, REG, Indep>;
468impl<'a, REG> IndepW<'a, REG>
469where
470    REG: crate::Writable + crate::RegisterSpec,
471{
472    #[doc = "PWM_A and PWM_B form a complementary PWM pair."]
473    #[inline(always)]
474    pub fn complementary(self) -> &'a mut crate::W<REG> {
475        self.variant(Indep::Complementary)
476    }
477    #[doc = "PWM_A and PWM_B outputs are independent PWMs."]
478    #[inline(always)]
479    pub fn independent(self) -> &'a mut crate::W<REG> {
480        self.variant(Indep::Independent)
481    }
482}
483#[doc = "Field `DBGEN` reader - Debug Enable"]
484pub type DbgenR = crate::BitReader;
485#[doc = "Field `DBGEN` writer - Debug Enable"]
486pub type DbgenW<'a, REG> = crate::BitWriter<'a, REG>;
487impl R {
488    #[doc = "Bits 0:1 - Clock Source Select"]
489    #[inline(always)]
490    pub fn clk_sel(&self) -> ClkSelR {
491        ClkSelR::new((self.bits & 3) as u8)
492    }
493    #[doc = "Bit 2 - Reload Source Select"]
494    #[inline(always)]
495    pub fn reload_sel(&self) -> ReloadSelR {
496        ReloadSelR::new(((self.bits >> 2) & 1) != 0)
497    }
498    #[doc = "Bits 3:5 - Force Select"]
499    #[inline(always)]
500    pub fn force_sel(&self) -> ForceSelR {
501        ForceSelR::new(((self.bits >> 3) & 7) as u8)
502    }
503    #[doc = "Bit 6 - Force Initialization"]
504    #[inline(always)]
505    pub fn force(&self) -> ForceR {
506        ForceR::new(((self.bits >> 6) & 1) != 0)
507    }
508    #[doc = "Bit 7 - Force Enable"]
509    #[inline(always)]
510    pub fn frcen(&self) -> FrcenR {
511        FrcenR::new(((self.bits >> 7) & 1) != 0)
512    }
513    #[doc = "Bits 8:9 - Initialization Control Select"]
514    #[inline(always)]
515    pub fn init_sel(&self) -> InitSelR {
516        InitSelR::new(((self.bits >> 8) & 3) as u8)
517    }
518    #[doc = "Bit 10 - PWM_X Initial Value"]
519    #[inline(always)]
520    pub fn pwmx_init(&self) -> PwmxInitR {
521        PwmxInitR::new(((self.bits >> 10) & 1) != 0)
522    }
523    #[doc = "Bit 11 - PWM45 Initial Value"]
524    #[inline(always)]
525    pub fn pwm45_init(&self) -> Pwm45InitR {
526        Pwm45InitR::new(((self.bits >> 11) & 1) != 0)
527    }
528    #[doc = "Bit 12 - PWM23 Initial Value"]
529    #[inline(always)]
530    pub fn pwm23_init(&self) -> Pwm23InitR {
531        Pwm23InitR::new(((self.bits >> 12) & 1) != 0)
532    }
533    #[doc = "Bit 13 - Independent or Complementary Pair Operation"]
534    #[inline(always)]
535    pub fn indep(&self) -> IndepR {
536        IndepR::new(((self.bits >> 13) & 1) != 0)
537    }
538    #[doc = "Bit 15 - Debug Enable"]
539    #[inline(always)]
540    pub fn dbgen(&self) -> DbgenR {
541        DbgenR::new(((self.bits >> 15) & 1) != 0)
542    }
543}
544#[cfg(feature = "debug")]
545impl core::fmt::Debug for R {
546    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
547        f.debug_struct("SM2CTRL2")
548            .field("clk_sel", &self.clk_sel())
549            .field("reload_sel", &self.reload_sel())
550            .field("force_sel", &self.force_sel())
551            .field("force", &self.force())
552            .field("frcen", &self.frcen())
553            .field("init_sel", &self.init_sel())
554            .field("pwmx_init", &self.pwmx_init())
555            .field("pwm45_init", &self.pwm45_init())
556            .field("pwm23_init", &self.pwm23_init())
557            .field("indep", &self.indep())
558            .field("dbgen", &self.dbgen())
559            .finish()
560    }
561}
562impl W {
563    #[doc = "Bits 0:1 - Clock Source Select"]
564    #[inline(always)]
565    pub fn clk_sel(&mut self) -> ClkSelW<'_, Sm2ctrl2Spec> {
566        ClkSelW::new(self, 0)
567    }
568    #[doc = "Bit 2 - Reload Source Select"]
569    #[inline(always)]
570    pub fn reload_sel(&mut self) -> ReloadSelW<'_, Sm2ctrl2Spec> {
571        ReloadSelW::new(self, 2)
572    }
573    #[doc = "Bits 3:5 - Force Select"]
574    #[inline(always)]
575    pub fn force_sel(&mut self) -> ForceSelW<'_, Sm2ctrl2Spec> {
576        ForceSelW::new(self, 3)
577    }
578    #[doc = "Bit 6 - Force Initialization"]
579    #[inline(always)]
580    pub fn force(&mut self) -> ForceW<'_, Sm2ctrl2Spec> {
581        ForceW::new(self, 6)
582    }
583    #[doc = "Bit 7 - Force Enable"]
584    #[inline(always)]
585    pub fn frcen(&mut self) -> FrcenW<'_, Sm2ctrl2Spec> {
586        FrcenW::new(self, 7)
587    }
588    #[doc = "Bits 8:9 - Initialization Control Select"]
589    #[inline(always)]
590    pub fn init_sel(&mut self) -> InitSelW<'_, Sm2ctrl2Spec> {
591        InitSelW::new(self, 8)
592    }
593    #[doc = "Bit 10 - PWM_X Initial Value"]
594    #[inline(always)]
595    pub fn pwmx_init(&mut self) -> PwmxInitW<'_, Sm2ctrl2Spec> {
596        PwmxInitW::new(self, 10)
597    }
598    #[doc = "Bit 11 - PWM45 Initial Value"]
599    #[inline(always)]
600    pub fn pwm45_init(&mut self) -> Pwm45InitW<'_, Sm2ctrl2Spec> {
601        Pwm45InitW::new(self, 11)
602    }
603    #[doc = "Bit 12 - PWM23 Initial Value"]
604    #[inline(always)]
605    pub fn pwm23_init(&mut self) -> Pwm23InitW<'_, Sm2ctrl2Spec> {
606        Pwm23InitW::new(self, 12)
607    }
608    #[doc = "Bit 13 - Independent or Complementary Pair Operation"]
609    #[inline(always)]
610    pub fn indep(&mut self) -> IndepW<'_, Sm2ctrl2Spec> {
611        IndepW::new(self, 13)
612    }
613    #[doc = "Bit 15 - Debug Enable"]
614    #[inline(always)]
615    pub fn dbgen(&mut self) -> DbgenW<'_, Sm2ctrl2Spec> {
616        DbgenW::new(self, 15)
617    }
618}
619#[doc = "Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
620pub struct Sm2ctrl2Spec;
621impl crate::RegisterSpec for Sm2ctrl2Spec {
622    type Ux = u16;
623}
624#[doc = "`read()` method returns [`sm2ctrl2::R`](R) reader structure"]
625impl crate::Readable for Sm2ctrl2Spec {}
626#[doc = "`write(|w| ..)` method takes [`sm2ctrl2::W`](W) writer structure"]
627impl crate::Writable for Sm2ctrl2Spec {
628    type Safety = crate::Unsafe;
629}
630#[doc = "`reset()` method sets SM2CTRL2 to value 0"]
631impl crate::Resettable for Sm2ctrl2Spec {}
mcxa_pac/flexpwm0/sm2ctrl2.rs

mcxa_pac/flexpwm0/
sm2ctrl2.rs
