mcxa_pac/cdog0/
add256.rs

1#[doc = "Register `ADD256` writer"]
2pub type W = crate::W<Add256Spec>;
3#[doc = "Field `AD256` writer - ADD 256"]
4pub type Ad256W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
5#[cfg(feature = "debug")]
6impl core::fmt::Debug for crate::generic::Reg<Add256Spec> {
7    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
8        write!(f, "(not readable)")
9    }
10}
11impl W {
12    #[doc = "Bits 0:31 - ADD 256"]
13    #[inline(always)]
14    pub fn ad256(&mut self) -> Ad256W<'_, Add256Spec> {
15        Ad256W::new(self, 0)
16    }
17}
18#[doc = "ADD256 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add256::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19pub struct Add256Spec;
20impl crate::RegisterSpec for Add256Spec {
21    type Ux = u32;
22}
23#[doc = "`write(|w| ..)` method takes [`add256::W`](W) writer structure"]
24impl crate::Writable for Add256Spec {
25    type Safety = crate::Unsafe;
26}
27#[doc = "`reset()` method sets ADD256 to value 0"]
28impl crate::Resettable for Add256Spec {}
mcxa_pac/cdog0/add256.rs

mcxa_pac/cdog0/
add256.rs
