mcxa_pac/can0/
fdctrl.rs

1#[doc = "Register `FDCTRL` reader"]
2pub type R = crate::R<FdctrlSpec>;
3#[doc = "Register `FDCTRL` writer"]
4pub type W = crate::W<FdctrlSpec>;
5#[doc = "Field `TDCVAL` reader - Transceiver Delay Compensation Value"]
6pub type TdcvalR = crate::FieldReader;
7#[doc = "Field `TDCOFF` reader - Transceiver Delay Compensation Offset"]
8pub type TdcoffR = crate::FieldReader;
9#[doc = "Field `TDCOFF` writer - Transceiver Delay Compensation Offset"]
10pub type TdcoffW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
11#[doc = "Transceiver Delay Compensation Fail\n\nValue on reset: 0"]
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14pub enum Tdcfail {
15    #[doc = "0: In range"]
16    InRange = 0,
17    #[doc = "1: Out of range"]
18    OutOfRange = 1,
19}
20impl From<Tdcfail> for bool {
21    #[inline(always)]
22    fn from(variant: Tdcfail) -> Self {
23        variant as u8 != 0
24    }
25}
26#[doc = "Field `TDCFAIL` reader - Transceiver Delay Compensation Fail"]
27pub type TdcfailR = crate::BitReader<Tdcfail>;
28impl TdcfailR {
29    #[doc = "Get enumerated values variant"]
30    #[inline(always)]
31    pub const fn variant(&self) -> Tdcfail {
32        match self.bits {
33            false => Tdcfail::InRange,
34            true => Tdcfail::OutOfRange,
35        }
36    }
37    #[doc = "In range"]
38    #[inline(always)]
39    pub fn is_in_range(&self) -> bool {
40        *self == Tdcfail::InRange
41    }
42    #[doc = "Out of range"]
43    #[inline(always)]
44    pub fn is_out_of_range(&self) -> bool {
45        *self == Tdcfail::OutOfRange
46    }
47}
48#[doc = "Field `TDCFAIL` writer - Transceiver Delay Compensation Fail"]
49pub type TdcfailW<'a, REG> = crate::BitWriter1C<'a, REG, Tdcfail>;
50impl<'a, REG> TdcfailW<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    #[doc = "In range"]
55    #[inline(always)]
56    pub fn in_range(self) -> &'a mut crate::W<REG> {
57        self.variant(Tdcfail::InRange)
58    }
59    #[doc = "Out of range"]
60    #[inline(always)]
61    pub fn out_of_range(self) -> &'a mut crate::W<REG> {
62        self.variant(Tdcfail::OutOfRange)
63    }
64}
65#[doc = "Transceiver Delay Compensation Enable\n\nValue on reset: 0"]
66#[cfg_attr(feature = "defmt", derive(defmt::Format))]
67#[derive(Clone, Copy, Debug, PartialEq, Eq)]
68pub enum Tdcen {
69    #[doc = "0: Disable"]
70    Disable = 0,
71    #[doc = "1: Enable"]
72    Enable = 1,
73}
74impl From<Tdcen> for bool {
75    #[inline(always)]
76    fn from(variant: Tdcen) -> Self {
77        variant as u8 != 0
78    }
79}
80#[doc = "Field `TDCEN` reader - Transceiver Delay Compensation Enable"]
81pub type TdcenR = crate::BitReader<Tdcen>;
82impl TdcenR {
83    #[doc = "Get enumerated values variant"]
84    #[inline(always)]
85    pub const fn variant(&self) -> Tdcen {
86        match self.bits {
87            false => Tdcen::Disable,
88            true => Tdcen::Enable,
89        }
90    }
91    #[doc = "Disable"]
92    #[inline(always)]
93    pub fn is_disable(&self) -> bool {
94        *self == Tdcen::Disable
95    }
96    #[doc = "Enable"]
97    #[inline(always)]
98    pub fn is_enable(&self) -> bool {
99        *self == Tdcen::Enable
100    }
101}
102#[doc = "Field `TDCEN` writer - Transceiver Delay Compensation Enable"]
103pub type TdcenW<'a, REG> = crate::BitWriter<'a, REG, Tdcen>;
104impl<'a, REG> TdcenW<'a, REG>
105where
106    REG: crate::Writable + crate::RegisterSpec,
107{
108    #[doc = "Disable"]
109    #[inline(always)]
110    pub fn disable(self) -> &'a mut crate::W<REG> {
111        self.variant(Tdcen::Disable)
112    }
113    #[doc = "Enable"]
114    #[inline(always)]
115    pub fn enable(self) -> &'a mut crate::W<REG> {
116        self.variant(Tdcen::Enable)
117    }
118}
119#[doc = "Message Buffer Data Size for Region 0\n\nValue on reset: 0"]
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122#[repr(u8)]
123pub enum Mbdsr0 {
124    #[doc = "0: 8 bytes"]
125    R0_8Bytes = 0,
126    #[doc = "1: 16 bytes"]
127    R0_16Bytes = 1,
128    #[doc = "2: 32 bytes"]
129    R0_32Bytes = 2,
130    #[doc = "3: 64 bytes"]
131    R0_64Bytes = 3,
132}
133impl From<Mbdsr0> for u8 {
134    #[inline(always)]
135    fn from(variant: Mbdsr0) -> Self {
136        variant as _
137    }
138}
139impl crate::FieldSpec for Mbdsr0 {
140    type Ux = u8;
141}
142impl crate::IsEnum for Mbdsr0 {}
143#[doc = "Field `MBDSR0` reader - Message Buffer Data Size for Region 0"]
144pub type Mbdsr0R = crate::FieldReader<Mbdsr0>;
145impl Mbdsr0R {
146    #[doc = "Get enumerated values variant"]
147    #[inline(always)]
148    pub const fn variant(&self) -> Mbdsr0 {
149        match self.bits {
150            0 => Mbdsr0::R0_8Bytes,
151            1 => Mbdsr0::R0_16Bytes,
152            2 => Mbdsr0::R0_32Bytes,
153            3 => Mbdsr0::R0_64Bytes,
154            _ => unreachable!(),
155        }
156    }
157    #[doc = "8 bytes"]
158    #[inline(always)]
159    pub fn is_r0_8_bytes(&self) -> bool {
160        *self == Mbdsr0::R0_8Bytes
161    }
162    #[doc = "16 bytes"]
163    #[inline(always)]
164    pub fn is_r0_16_bytes(&self) -> bool {
165        *self == Mbdsr0::R0_16Bytes
166    }
167    #[doc = "32 bytes"]
168    #[inline(always)]
169    pub fn is_r0_32_bytes(&self) -> bool {
170        *self == Mbdsr0::R0_32Bytes
171    }
172    #[doc = "64 bytes"]
173    #[inline(always)]
174    pub fn is_r0_64_bytes(&self) -> bool {
175        *self == Mbdsr0::R0_64Bytes
176    }
177}
178#[doc = "Field `MBDSR0` writer - Message Buffer Data Size for Region 0"]
179pub type Mbdsr0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Mbdsr0, crate::Safe>;
180impl<'a, REG> Mbdsr0W<'a, REG>
181where
182    REG: crate::Writable + crate::RegisterSpec,
183    REG::Ux: From<u8>,
184{
185    #[doc = "8 bytes"]
186    #[inline(always)]
187    pub fn r0_8_bytes(self) -> &'a mut crate::W<REG> {
188        self.variant(Mbdsr0::R0_8Bytes)
189    }
190    #[doc = "16 bytes"]
191    #[inline(always)]
192    pub fn r0_16_bytes(self) -> &'a mut crate::W<REG> {
193        self.variant(Mbdsr0::R0_16Bytes)
194    }
195    #[doc = "32 bytes"]
196    #[inline(always)]
197    pub fn r0_32_bytes(self) -> &'a mut crate::W<REG> {
198        self.variant(Mbdsr0::R0_32Bytes)
199    }
200    #[doc = "64 bytes"]
201    #[inline(always)]
202    pub fn r0_64_bytes(self) -> &'a mut crate::W<REG> {
203        self.variant(Mbdsr0::R0_64Bytes)
204    }
205}
206#[doc = "Bit Rate Switch Enable\n\nValue on reset: 1"]
207#[cfg_attr(feature = "defmt", derive(defmt::Format))]
208#[derive(Clone, Copy, Debug, PartialEq, Eq)]
209pub enum Fdrate {
210    #[doc = "0: Disable"]
211    Nominal = 0,
212    #[doc = "1: Enable"]
213    BitRateSwitching = 1,
214}
215impl From<Fdrate> for bool {
216    #[inline(always)]
217    fn from(variant: Fdrate) -> Self {
218        variant as u8 != 0
219    }
220}
221#[doc = "Field `FDRATE` reader - Bit Rate Switch Enable"]
222pub type FdrateR = crate::BitReader<Fdrate>;
223impl FdrateR {
224    #[doc = "Get enumerated values variant"]
225    #[inline(always)]
226    pub const fn variant(&self) -> Fdrate {
227        match self.bits {
228            false => Fdrate::Nominal,
229            true => Fdrate::BitRateSwitching,
230        }
231    }
232    #[doc = "Disable"]
233    #[inline(always)]
234    pub fn is_nominal(&self) -> bool {
235        *self == Fdrate::Nominal
236    }
237    #[doc = "Enable"]
238    #[inline(always)]
239    pub fn is_bit_rate_switching(&self) -> bool {
240        *self == Fdrate::BitRateSwitching
241    }
242}
243#[doc = "Field `FDRATE` writer - Bit Rate Switch Enable"]
244pub type FdrateW<'a, REG> = crate::BitWriter<'a, REG, Fdrate>;
245impl<'a, REG> FdrateW<'a, REG>
246where
247    REG: crate::Writable + crate::RegisterSpec,
248{
249    #[doc = "Disable"]
250    #[inline(always)]
251    pub fn nominal(self) -> &'a mut crate::W<REG> {
252        self.variant(Fdrate::Nominal)
253    }
254    #[doc = "Enable"]
255    #[inline(always)]
256    pub fn bit_rate_switching(self) -> &'a mut crate::W<REG> {
257        self.variant(Fdrate::BitRateSwitching)
258    }
259}
260impl R {
261    #[doc = "Bits 0:5 - Transceiver Delay Compensation Value"]
262    #[inline(always)]
263    pub fn tdcval(&self) -> TdcvalR {
264        TdcvalR::new((self.bits & 0x3f) as u8)
265    }
266    #[doc = "Bits 8:12 - Transceiver Delay Compensation Offset"]
267    #[inline(always)]
268    pub fn tdcoff(&self) -> TdcoffR {
269        TdcoffR::new(((self.bits >> 8) & 0x1f) as u8)
270    }
271    #[doc = "Bit 14 - Transceiver Delay Compensation Fail"]
272    #[inline(always)]
273    pub fn tdcfail(&self) -> TdcfailR {
274        TdcfailR::new(((self.bits >> 14) & 1) != 0)
275    }
276    #[doc = "Bit 15 - Transceiver Delay Compensation Enable"]
277    #[inline(always)]
278    pub fn tdcen(&self) -> TdcenR {
279        TdcenR::new(((self.bits >> 15) & 1) != 0)
280    }
281    #[doc = "Bits 16:17 - Message Buffer Data Size for Region 0"]
282    #[inline(always)]
283    pub fn mbdsr0(&self) -> Mbdsr0R {
284        Mbdsr0R::new(((self.bits >> 16) & 3) as u8)
285    }
286    #[doc = "Bit 31 - Bit Rate Switch Enable"]
287    #[inline(always)]
288    pub fn fdrate(&self) -> FdrateR {
289        FdrateR::new(((self.bits >> 31) & 1) != 0)
290    }
291}
292#[cfg(feature = "debug")]
293impl core::fmt::Debug for R {
294    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
295        f.debug_struct("FDCTRL")
296            .field("tdcval", &self.tdcval())
297            .field("tdcoff", &self.tdcoff())
298            .field("tdcfail", &self.tdcfail())
299            .field("tdcen", &self.tdcen())
300            .field("mbdsr0", &self.mbdsr0())
301            .field("fdrate", &self.fdrate())
302            .finish()
303    }
304}
305impl W {
306    #[doc = "Bits 8:12 - Transceiver Delay Compensation Offset"]
307    #[inline(always)]
308    pub fn tdcoff(&mut self) -> TdcoffW<'_, FdctrlSpec> {
309        TdcoffW::new(self, 8)
310    }
311    #[doc = "Bit 14 - Transceiver Delay Compensation Fail"]
312    #[inline(always)]
313    pub fn tdcfail(&mut self) -> TdcfailW<'_, FdctrlSpec> {
314        TdcfailW::new(self, 14)
315    }
316    #[doc = "Bit 15 - Transceiver Delay Compensation Enable"]
317    #[inline(always)]
318    pub fn tdcen(&mut self) -> TdcenW<'_, FdctrlSpec> {
319        TdcenW::new(self, 15)
320    }
321    #[doc = "Bits 16:17 - Message Buffer Data Size for Region 0"]
322    #[inline(always)]
323    pub fn mbdsr0(&mut self) -> Mbdsr0W<'_, FdctrlSpec> {
324        Mbdsr0W::new(self, 16)
325    }
326    #[doc = "Bit 31 - Bit Rate Switch Enable"]
327    #[inline(always)]
328    pub fn fdrate(&mut self) -> FdrateW<'_, FdctrlSpec> {
329        FdrateW::new(self, 31)
330    }
331}
332#[doc = "CAN FD Control\n\nYou can [`read`](crate::Reg::read) this register and get [`fdctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
333pub struct FdctrlSpec;
334impl crate::RegisterSpec for FdctrlSpec {
335    type Ux = u32;
336}
337#[doc = "`read()` method returns [`fdctrl::R`](R) reader structure"]
338impl crate::Readable for FdctrlSpec {}
339#[doc = "`write(|w| ..)` method takes [`fdctrl::W`](W) writer structure"]
340impl crate::Writable for FdctrlSpec {
341    type Safety = crate::Unsafe;
342    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x4000;
343}
344#[doc = "`reset()` method sets FDCTRL to value 0x8000_0100"]
345impl crate::Resettable for FdctrlSpec {
346    const RESET_VALUE: u32 = 0x8000_0100;
347}
mcxa_pac/can0/fdctrl.rs

mcxa_pac/can0/
fdctrl.rs
