1#[doc = "Register `CBT` reader"]
2pub type R = crate::R<CbtSpec>;
3#[doc = "Register `CBT` writer"]
4pub type W = crate::W<CbtSpec>;
5#[doc = "Field `EPSEG2` reader - Extended Phase Segment 2"]
6pub type Epseg2R = crate::FieldReader;
7#[doc = "Field `EPSEG2` writer - Extended Phase Segment 2"]
8pub type Epseg2W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `EPSEG1` reader - Extended Phase Segment 1"]
10pub type Epseg1R = crate::FieldReader;
11#[doc = "Field `EPSEG1` writer - Extended Phase Segment 1"]
12pub type Epseg1W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Field `EPROPSEG` reader - Extended Propagation Segment"]
14pub type EpropsegR = crate::FieldReader;
15#[doc = "Field `EPROPSEG` writer - Extended Propagation Segment"]
16pub type EpropsegW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17#[doc = "Field `ERJW` reader - Extended Resync Jump Width"]
18pub type ErjwR = crate::FieldReader;
19#[doc = "Field `ERJW` writer - Extended Resync Jump Width"]
20pub type ErjwW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
21#[doc = "Field `EPRESDIV` reader - Extended Prescaler Division Factor"]
22pub type EpresdivR = crate::FieldReader<u16>;
23#[doc = "Field `EPRESDIV` writer - Extended Prescaler Division Factor"]
24pub type EpresdivW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
25#[doc = "Bit Timing Format Enable\n\nValue on reset: 0"]
26#[cfg_attr(feature = "defmt", derive(defmt::Format))]
27#[derive(Clone, Copy, Debug, PartialEq, Eq)]
28pub enum Btf {
29 #[doc = "0: Disable"]
30 Disable = 0,
31 #[doc = "1: Enable"]
32 Enable = 1,
33}
34impl From<Btf> for bool {
35 #[inline(always)]
36 fn from(variant: Btf) -> Self {
37 variant as u8 != 0
38 }
39}
40#[doc = "Field `BTF` reader - Bit Timing Format Enable"]
41pub type BtfR = crate::BitReader<Btf>;
42impl BtfR {
43 #[doc = "Get enumerated values variant"]
44 #[inline(always)]
45 pub const fn variant(&self) -> Btf {
46 match self.bits {
47 false => Btf::Disable,
48 true => Btf::Enable,
49 }
50 }
51 #[doc = "Disable"]
52 #[inline(always)]
53 pub fn is_disable(&self) -> bool {
54 *self == Btf::Disable
55 }
56 #[doc = "Enable"]
57 #[inline(always)]
58 pub fn is_enable(&self) -> bool {
59 *self == Btf::Enable
60 }
61}
62#[doc = "Field `BTF` writer - Bit Timing Format Enable"]
63pub type BtfW<'a, REG> = crate::BitWriter<'a, REG, Btf>;
64impl<'a, REG> BtfW<'a, REG>
65where
66 REG: crate::Writable + crate::RegisterSpec,
67{
68 #[doc = "Disable"]
69 #[inline(always)]
70 pub fn disable(self) -> &'a mut crate::W<REG> {
71 self.variant(Btf::Disable)
72 }
73 #[doc = "Enable"]
74 #[inline(always)]
75 pub fn enable(self) -> &'a mut crate::W<REG> {
76 self.variant(Btf::Enable)
77 }
78}
79impl R {
80 #[doc = "Bits 0:4 - Extended Phase Segment 2"]
81 #[inline(always)]
82 pub fn epseg2(&self) -> Epseg2R {
83 Epseg2R::new((self.bits & 0x1f) as u8)
84 }
85 #[doc = "Bits 5:9 - Extended Phase Segment 1"]
86 #[inline(always)]
87 pub fn epseg1(&self) -> Epseg1R {
88 Epseg1R::new(((self.bits >> 5) & 0x1f) as u8)
89 }
90 #[doc = "Bits 10:15 - Extended Propagation Segment"]
91 #[inline(always)]
92 pub fn epropseg(&self) -> EpropsegR {
93 EpropsegR::new(((self.bits >> 10) & 0x3f) as u8)
94 }
95 #[doc = "Bits 16:20 - Extended Resync Jump Width"]
96 #[inline(always)]
97 pub fn erjw(&self) -> ErjwR {
98 ErjwR::new(((self.bits >> 16) & 0x1f) as u8)
99 }
100 #[doc = "Bits 21:30 - Extended Prescaler Division Factor"]
101 #[inline(always)]
102 pub fn epresdiv(&self) -> EpresdivR {
103 EpresdivR::new(((self.bits >> 21) & 0x03ff) as u16)
104 }
105 #[doc = "Bit 31 - Bit Timing Format Enable"]
106 #[inline(always)]
107 pub fn btf(&self) -> BtfR {
108 BtfR::new(((self.bits >> 31) & 1) != 0)
109 }
110}
111#[cfg(feature = "debug")]
112impl core::fmt::Debug for R {
113 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
114 f.debug_struct("CBT")
115 .field("epseg2", &self.epseg2())
116 .field("epseg1", &self.epseg1())
117 .field("epropseg", &self.epropseg())
118 .field("erjw", &self.erjw())
119 .field("epresdiv", &self.epresdiv())
120 .field("btf", &self.btf())
121 .finish()
122 }
123}
124impl W {
125 #[doc = "Bits 0:4 - Extended Phase Segment 2"]
126 #[inline(always)]
127 pub fn epseg2(&mut self) -> Epseg2W<'_, CbtSpec> {
128 Epseg2W::new(self, 0)
129 }
130 #[doc = "Bits 5:9 - Extended Phase Segment 1"]
131 #[inline(always)]
132 pub fn epseg1(&mut self) -> Epseg1W<'_, CbtSpec> {
133 Epseg1W::new(self, 5)
134 }
135 #[doc = "Bits 10:15 - Extended Propagation Segment"]
136 #[inline(always)]
137 pub fn epropseg(&mut self) -> EpropsegW<'_, CbtSpec> {
138 EpropsegW::new(self, 10)
139 }
140 #[doc = "Bits 16:20 - Extended Resync Jump Width"]
141 #[inline(always)]
142 pub fn erjw(&mut self) -> ErjwW<'_, CbtSpec> {
143 ErjwW::new(self, 16)
144 }
145 #[doc = "Bits 21:30 - Extended Prescaler Division Factor"]
146 #[inline(always)]
147 pub fn epresdiv(&mut self) -> EpresdivW<'_, CbtSpec> {
148 EpresdivW::new(self, 21)
149 }
150 #[doc = "Bit 31 - Bit Timing Format Enable"]
151 #[inline(always)]
152 pub fn btf(&mut self) -> BtfW<'_, CbtSpec> {
153 BtfW::new(self, 31)
154 }
155}
156#[doc = "CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`cbt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cbt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
157pub struct CbtSpec;
158impl crate::RegisterSpec for CbtSpec {
159 type Ux = u32;
160}
161#[doc = "`read()` method returns [`cbt::R`](R) reader structure"]
162impl crate::Readable for CbtSpec {}
163#[doc = "`write(|w| ..)` method takes [`cbt::W`](W) writer structure"]
164impl crate::Writable for CbtSpec {
165 type Safety = crate::Unsafe;
166}
167#[doc = "`reset()` method sets CBT to value 0"]
168impl crate::Resettable for CbtSpec {}