mcxa_pac/usb0/
usbctrl.rs

1#[doc = "Register `USBCTRL` reader"]
2pub type R = crate::R<UsbctrlSpec>;
3#[doc = "Register `USBCTRL` writer"]
4pub type W = crate::W<UsbctrlSpec>;
5#[doc = "DP and DM Lane Reversal Control\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum DpdmLaneReverse {
9    #[doc = "0: Standard USB DP and DM package pin assignment"]
10    DpDmStandard = 0,
11    #[doc = "1: Reverse roles of USB DP and DM package pins"]
12    DpDmReversed = 1,
13}
14impl From<DpdmLaneReverse> for bool {
15    #[inline(always)]
16    fn from(variant: DpdmLaneReverse) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `DPDM_LANE_REVERSE` reader - DP and DM Lane Reversal Control"]
21pub type DpdmLaneReverseR = crate::BitReader<DpdmLaneReverse>;
22impl DpdmLaneReverseR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> DpdmLaneReverse {
26        match self.bits {
27            false => DpdmLaneReverse::DpDmStandard,
28            true => DpdmLaneReverse::DpDmReversed,
29        }
30    }
31    #[doc = "Standard USB DP and DM package pin assignment"]
32    #[inline(always)]
33    pub fn is_dp_dm_standard(&self) -> bool {
34        *self == DpdmLaneReverse::DpDmStandard
35    }
36    #[doc = "Reverse roles of USB DP and DM package pins"]
37    #[inline(always)]
38    pub fn is_dp_dm_reversed(&self) -> bool {
39        *self == DpdmLaneReverse::DpDmReversed
40    }
41}
42#[doc = "Field `DPDM_LANE_REVERSE` writer - DP and DM Lane Reversal Control"]
43pub type DpdmLaneReverseW<'a, REG> = crate::BitWriter<'a, REG, DpdmLaneReverse>;
44impl<'a, REG> DpdmLaneReverseW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Standard USB DP and DM package pin assignment"]
49    #[inline(always)]
50    pub fn dp_dm_standard(self) -> &'a mut crate::W<REG> {
51        self.variant(DpdmLaneReverse::DpDmStandard)
52    }
53    #[doc = "Reverse roles of USB DP and DM package pins"]
54    #[inline(always)]
55    pub fn dp_dm_reversed(self) -> &'a mut crate::W<REG> {
56        self.variant(DpdmLaneReverse::DpDmReversed)
57    }
58}
59#[doc = "Host-Mode-Only Low-Speed Device EOP Signaling\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum HostLsEop {
63    #[doc = "0: Full-speed device or a low-speed device through a hub"]
64    HostFsResumeEop = 0,
65    #[doc = "1: Directly-connected low-speed device"]
66    HostLsResumeEop = 1,
67}
68impl From<HostLsEop> for bool {
69    #[inline(always)]
70    fn from(variant: HostLsEop) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `HOST_LS_EOP` reader - Host-Mode-Only Low-Speed Device EOP Signaling"]
75pub type HostLsEopR = crate::BitReader<HostLsEop>;
76impl HostLsEopR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> HostLsEop {
80        match self.bits {
81            false => HostLsEop::HostFsResumeEop,
82            true => HostLsEop::HostLsResumeEop,
83        }
84    }
85    #[doc = "Full-speed device or a low-speed device through a hub"]
86    #[inline(always)]
87    pub fn is_host_fs_resume_eop(&self) -> bool {
88        *self == HostLsEop::HostFsResumeEop
89    }
90    #[doc = "Directly-connected low-speed device"]
91    #[inline(always)]
92    pub fn is_host_ls_resume_eop(&self) -> bool {
93        *self == HostLsEop::HostLsResumeEop
94    }
95}
96#[doc = "Field `HOST_LS_EOP` writer - Host-Mode-Only Low-Speed Device EOP Signaling"]
97pub type HostLsEopW<'a, REG> = crate::BitWriter<'a, REG, HostLsEop>;
98impl<'a, REG> HostLsEopW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Full-speed device or a low-speed device through a hub"]
103    #[inline(always)]
104    pub fn host_fs_resume_eop(self) -> &'a mut crate::W<REG> {
105        self.variant(HostLsEop::HostFsResumeEop)
106    }
107    #[doc = "Directly-connected low-speed device"]
108    #[inline(always)]
109    pub fn host_ls_resume_eop(self) -> &'a mut crate::W<REG> {
110        self.variant(HostLsEop::HostLsResumeEop)
111    }
112}
113#[doc = "UART Select\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Uartsel {
117    #[doc = "0: USB DP and DM external package pins are used for USB signaling."]
118    UsbMode = 0,
119    #[doc = "1: USB DP and DM external package pins are used for UART signaling."]
120    UartMode = 1,
121}
122impl From<Uartsel> for bool {
123    #[inline(always)]
124    fn from(variant: Uartsel) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `UARTSEL` reader - UART Select"]
129pub type UartselR = crate::BitReader<Uartsel>;
130impl UartselR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Uartsel {
134        match self.bits {
135            false => Uartsel::UsbMode,
136            true => Uartsel::UartMode,
137        }
138    }
139    #[doc = "USB DP and DM external package pins are used for USB signaling."]
140    #[inline(always)]
141    pub fn is_usb_mode(&self) -> bool {
142        *self == Uartsel::UsbMode
143    }
144    #[doc = "USB DP and DM external package pins are used for UART signaling."]
145    #[inline(always)]
146    pub fn is_uart_mode(&self) -> bool {
147        *self == Uartsel::UartMode
148    }
149}
150#[doc = "Field `UARTSEL` writer - UART Select"]
151pub type UartselW<'a, REG> = crate::BitWriter<'a, REG, Uartsel>;
152impl<'a, REG> UartselW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "USB DP and DM external package pins are used for USB signaling."]
157    #[inline(always)]
158    pub fn usb_mode(self) -> &'a mut crate::W<REG> {
159        self.variant(Uartsel::UsbMode)
160    }
161    #[doc = "USB DP and DM external package pins are used for UART signaling."]
162    #[inline(always)]
163    pub fn uart_mode(self) -> &'a mut crate::W<REG> {
164        self.variant(Uartsel::UartMode)
165    }
166}
167#[doc = "UART Signal Channel Select\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Uartchls {
171    #[doc = "0: USB DP and DM signals are used as UART TX/RX."]
172    UartDpTx = 0,
173    #[doc = "1: USB DP and DM signals are used as UART RX/TX."]
174    UartDmTx = 1,
175}
176impl From<Uartchls> for bool {
177    #[inline(always)]
178    fn from(variant: Uartchls) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `UARTCHLS` reader - UART Signal Channel Select"]
183pub type UartchlsR = crate::BitReader<Uartchls>;
184impl UartchlsR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Uartchls {
188        match self.bits {
189            false => Uartchls::UartDpTx,
190            true => Uartchls::UartDmTx,
191        }
192    }
193    #[doc = "USB DP and DM signals are used as UART TX/RX."]
194    #[inline(always)]
195    pub fn is_uart_dp_tx(&self) -> bool {
196        *self == Uartchls::UartDpTx
197    }
198    #[doc = "USB DP and DM signals are used as UART RX/TX."]
199    #[inline(always)]
200    pub fn is_uart_dm_tx(&self) -> bool {
201        *self == Uartchls::UartDmTx
202    }
203}
204#[doc = "Field `UARTCHLS` writer - UART Signal Channel Select"]
205pub type UartchlsW<'a, REG> = crate::BitWriter<'a, REG, Uartchls>;
206impl<'a, REG> UartchlsW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "USB DP and DM signals are used as UART TX/RX."]
211    #[inline(always)]
212    pub fn uart_dp_tx(self) -> &'a mut crate::W<REG> {
213        self.variant(Uartchls::UartDpTx)
214    }
215    #[doc = "USB DP and DM signals are used as UART RX/TX."]
216    #[inline(always)]
217    pub fn uart_dm_tx(self) -> &'a mut crate::W<REG> {
218        self.variant(Uartchls::UartDmTx)
219    }
220}
221#[doc = "Pulldown Enable\n\nValue on reset: 1"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum Pde {
225    #[doc = "0: Disable on D+ and D-"]
226    DisPulldowns = 0,
227    #[doc = "1: Enable on D+ and D-"]
228    EnPulldowns = 1,
229}
230impl From<Pde> for bool {
231    #[inline(always)]
232    fn from(variant: Pde) -> Self {
233        variant as u8 != 0
234    }
235}
236#[doc = "Field `PDE` reader - Pulldown Enable"]
237pub type PdeR = crate::BitReader<Pde>;
238impl PdeR {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> Pde {
242        match self.bits {
243            false => Pde::DisPulldowns,
244            true => Pde::EnPulldowns,
245        }
246    }
247    #[doc = "Disable on D+ and D-"]
248    #[inline(always)]
249    pub fn is_dis_pulldowns(&self) -> bool {
250        *self == Pde::DisPulldowns
251    }
252    #[doc = "Enable on D+ and D-"]
253    #[inline(always)]
254    pub fn is_en_pulldowns(&self) -> bool {
255        *self == Pde::EnPulldowns
256    }
257}
258#[doc = "Field `PDE` writer - Pulldown Enable"]
259pub type PdeW<'a, REG> = crate::BitWriter<'a, REG, Pde>;
260impl<'a, REG> PdeW<'a, REG>
261where
262    REG: crate::Writable + crate::RegisterSpec,
263{
264    #[doc = "Disable on D+ and D-"]
265    #[inline(always)]
266    pub fn dis_pulldowns(self) -> &'a mut crate::W<REG> {
267        self.variant(Pde::DisPulldowns)
268    }
269    #[doc = "Enable on D+ and D-"]
270    #[inline(always)]
271    pub fn en_pulldowns(self) -> &'a mut crate::W<REG> {
272        self.variant(Pde::EnPulldowns)
273    }
274}
275#[doc = "Suspend\n\nValue on reset: 1"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum Susp {
279    #[doc = "0: Not in Suspend state"]
280    XcvrNotSuspend = 0,
281    #[doc = "1: In Suspend state"]
282    XcvrSuspend = 1,
283}
284impl From<Susp> for bool {
285    #[inline(always)]
286    fn from(variant: Susp) -> Self {
287        variant as u8 != 0
288    }
289}
290#[doc = "Field `SUSP` reader - Suspend"]
291pub type SuspR = crate::BitReader<Susp>;
292impl SuspR {
293    #[doc = "Get enumerated values variant"]
294    #[inline(always)]
295    pub const fn variant(&self) -> Susp {
296        match self.bits {
297            false => Susp::XcvrNotSuspend,
298            true => Susp::XcvrSuspend,
299        }
300    }
301    #[doc = "Not in Suspend state"]
302    #[inline(always)]
303    pub fn is_xcvr_not_suspend(&self) -> bool {
304        *self == Susp::XcvrNotSuspend
305    }
306    #[doc = "In Suspend state"]
307    #[inline(always)]
308    pub fn is_xcvr_suspend(&self) -> bool {
309        *self == Susp::XcvrSuspend
310    }
311}
312#[doc = "Field `SUSP` writer - Suspend"]
313pub type SuspW<'a, REG> = crate::BitWriter<'a, REG, Susp>;
314impl<'a, REG> SuspW<'a, REG>
315where
316    REG: crate::Writable + crate::RegisterSpec,
317{
318    #[doc = "Not in Suspend state"]
319    #[inline(always)]
320    pub fn xcvr_not_suspend(self) -> &'a mut crate::W<REG> {
321        self.variant(Susp::XcvrNotSuspend)
322    }
323    #[doc = "In Suspend state"]
324    #[inline(always)]
325    pub fn xcvr_suspend(self) -> &'a mut crate::W<REG> {
326        self.variant(Susp::XcvrSuspend)
327    }
328}
329impl R {
330    #[doc = "Bit 2 - DP and DM Lane Reversal Control"]
331    #[inline(always)]
332    pub fn dpdm_lane_reverse(&self) -> DpdmLaneReverseR {
333        DpdmLaneReverseR::new(((self.bits >> 2) & 1) != 0)
334    }
335    #[doc = "Bit 3 - Host-Mode-Only Low-Speed Device EOP Signaling"]
336    #[inline(always)]
337    pub fn host_ls_eop(&self) -> HostLsEopR {
338        HostLsEopR::new(((self.bits >> 3) & 1) != 0)
339    }
340    #[doc = "Bit 4 - UART Select"]
341    #[inline(always)]
342    pub fn uartsel(&self) -> UartselR {
343        UartselR::new(((self.bits >> 4) & 1) != 0)
344    }
345    #[doc = "Bit 5 - UART Signal Channel Select"]
346    #[inline(always)]
347    pub fn uartchls(&self) -> UartchlsR {
348        UartchlsR::new(((self.bits >> 5) & 1) != 0)
349    }
350    #[doc = "Bit 6 - Pulldown Enable"]
351    #[inline(always)]
352    pub fn pde(&self) -> PdeR {
353        PdeR::new(((self.bits >> 6) & 1) != 0)
354    }
355    #[doc = "Bit 7 - Suspend"]
356    #[inline(always)]
357    pub fn susp(&self) -> SuspR {
358        SuspR::new(((self.bits >> 7) & 1) != 0)
359    }
360}
361#[cfg(feature = "debug")]
362impl core::fmt::Debug for R {
363    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
364        f.debug_struct("USBCTRL")
365            .field("dpdm_lane_reverse", &self.dpdm_lane_reverse())
366            .field("host_ls_eop", &self.host_ls_eop())
367            .field("uartsel", &self.uartsel())
368            .field("uartchls", &self.uartchls())
369            .field("pde", &self.pde())
370            .field("susp", &self.susp())
371            .finish()
372    }
373}
374impl W {
375    #[doc = "Bit 2 - DP and DM Lane Reversal Control"]
376    #[inline(always)]
377    pub fn dpdm_lane_reverse(&mut self) -> DpdmLaneReverseW<'_, UsbctrlSpec> {
378        DpdmLaneReverseW::new(self, 2)
379    }
380    #[doc = "Bit 3 - Host-Mode-Only Low-Speed Device EOP Signaling"]
381    #[inline(always)]
382    pub fn host_ls_eop(&mut self) -> HostLsEopW<'_, UsbctrlSpec> {
383        HostLsEopW::new(self, 3)
384    }
385    #[doc = "Bit 4 - UART Select"]
386    #[inline(always)]
387    pub fn uartsel(&mut self) -> UartselW<'_, UsbctrlSpec> {
388        UartselW::new(self, 4)
389    }
390    #[doc = "Bit 5 - UART Signal Channel Select"]
391    #[inline(always)]
392    pub fn uartchls(&mut self) -> UartchlsW<'_, UsbctrlSpec> {
393        UartchlsW::new(self, 5)
394    }
395    #[doc = "Bit 6 - Pulldown Enable"]
396    #[inline(always)]
397    pub fn pde(&mut self) -> PdeW<'_, UsbctrlSpec> {
398        PdeW::new(self, 6)
399    }
400    #[doc = "Bit 7 - Suspend"]
401    #[inline(always)]
402    pub fn susp(&mut self) -> SuspW<'_, UsbctrlSpec> {
403        SuspW::new(self, 7)
404    }
405}
406#[doc = "USB Control\n\nYou can [`read`](crate::Reg::read) this register and get [`usbctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
407pub struct UsbctrlSpec;
408impl crate::RegisterSpec for UsbctrlSpec {
409    type Ux = u8;
410}
411#[doc = "`read()` method returns [`usbctrl::R`](R) reader structure"]
412impl crate::Readable for UsbctrlSpec {}
413#[doc = "`write(|w| ..)` method takes [`usbctrl::W`](W) writer structure"]
414impl crate::Writable for UsbctrlSpec {
415    type Safety = crate::Unsafe;
416}
417#[doc = "`reset()` method sets USBCTRL to value 0xc0"]
418impl crate::Resettable for UsbctrlSpec {
419    const RESET_VALUE: u8 = 0xc0;
420}
mcxa_pac/usb0/usbctrl.rs

mcxa_pac/usb0/
usbctrl.rs
