mcxa_pac/usb0/
ctl.rs

1#[doc = "Register `CTL` reader"]
2pub type R = crate::R<CtlSpec>;
3#[doc = "Register `CTL` writer"]
4pub type W = crate::W<CtlSpec>;
5#[doc = "USB Enable\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Usbensofen {
9    #[doc = "0: Disable"]
10    DisUsbSof = 0,
11    #[doc = "1: Enable"]
12    EnUsbSof = 1,
13}
14impl From<Usbensofen> for bool {
15    #[inline(always)]
16    fn from(variant: Usbensofen) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `USBENSOFEN` reader - USB Enable"]
21pub type UsbensofenR = crate::BitReader<Usbensofen>;
22impl UsbensofenR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Usbensofen {
26        match self.bits {
27            false => Usbensofen::DisUsbSof,
28            true => Usbensofen::EnUsbSof,
29        }
30    }
31    #[doc = "Disable"]
32    #[inline(always)]
33    pub fn is_dis_usb_sof(&self) -> bool {
34        *self == Usbensofen::DisUsbSof
35    }
36    #[doc = "Enable"]
37    #[inline(always)]
38    pub fn is_en_usb_sof(&self) -> bool {
39        *self == Usbensofen::EnUsbSof
40    }
41}
42#[doc = "Field `USBENSOFEN` writer - USB Enable"]
43pub type UsbensofenW<'a, REG> = crate::BitWriter<'a, REG, Usbensofen>;
44impl<'a, REG> UsbensofenW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Disable"]
49    #[inline(always)]
50    pub fn dis_usb_sof(self) -> &'a mut crate::W<REG> {
51        self.variant(Usbensofen::DisUsbSof)
52    }
53    #[doc = "Enable"]
54    #[inline(always)]
55    pub fn en_usb_sof(self) -> &'a mut crate::W<REG> {
56        self.variant(Usbensofen::EnUsbSof)
57    }
58}
59#[doc = "Field `ODDRST` reader - Odd Reset"]
60pub type OddrstR = crate::BitReader;
61#[doc = "Field `ODDRST` writer - Odd Reset"]
62pub type OddrstW<'a, REG> = crate::BitWriter<'a, REG>;
63#[doc = "Field `RESUME` reader - Resume"]
64pub type ResumeR = crate::BitReader;
65#[doc = "Field `RESUME` writer - Resume"]
66pub type ResumeW<'a, REG> = crate::BitWriter<'a, REG>;
67#[doc = "Host Mode Enable\n\nValue on reset: 0"]
68#[cfg_attr(feature = "defmt", derive(defmt::Format))]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum Hostmodeen {
71    #[doc = "0: USBFS operates in Device mode."]
72    EnDeviceMode = 0,
73    #[doc = "1: USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor."]
74    EnHostMode = 1,
75}
76impl From<Hostmodeen> for bool {
77    #[inline(always)]
78    fn from(variant: Hostmodeen) -> Self {
79        variant as u8 != 0
80    }
81}
82#[doc = "Field `HOSTMODEEN` reader - Host Mode Enable"]
83pub type HostmodeenR = crate::BitReader<Hostmodeen>;
84impl HostmodeenR {
85    #[doc = "Get enumerated values variant"]
86    #[inline(always)]
87    pub const fn variant(&self) -> Hostmodeen {
88        match self.bits {
89            false => Hostmodeen::EnDeviceMode,
90            true => Hostmodeen::EnHostMode,
91        }
92    }
93    #[doc = "USBFS operates in Device mode."]
94    #[inline(always)]
95    pub fn is_en_device_mode(&self) -> bool {
96        *self == Hostmodeen::EnDeviceMode
97    }
98    #[doc = "USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor."]
99    #[inline(always)]
100    pub fn is_en_host_mode(&self) -> bool {
101        *self == Hostmodeen::EnHostMode
102    }
103}
104#[doc = "Field `HOSTMODEEN` writer - Host Mode Enable"]
105pub type HostmodeenW<'a, REG> = crate::BitWriter<'a, REG, Hostmodeen>;
106impl<'a, REG> HostmodeenW<'a, REG>
107where
108    REG: crate::Writable + crate::RegisterSpec,
109{
110    #[doc = "USBFS operates in Device mode."]
111    #[inline(always)]
112    pub fn en_device_mode(self) -> &'a mut crate::W<REG> {
113        self.variant(Hostmodeen::EnDeviceMode)
114    }
115    #[doc = "USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor."]
116    #[inline(always)]
117    pub fn en_host_mode(self) -> &'a mut crate::W<REG> {
118        self.variant(Hostmodeen::EnHostMode)
119    }
120}
121#[doc = "Reset Signaling Enable\n\nValue on reset: 0"]
122#[cfg_attr(feature = "defmt", derive(defmt::Format))]
123#[derive(Clone, Copy, Debug, PartialEq, Eq)]
124pub enum Reset {
125    #[doc = "0: Disable"]
126    Disable = 0,
127    #[doc = "1: Enable"]
128    Enable = 1,
129}
130impl From<Reset> for bool {
131    #[inline(always)]
132    fn from(variant: Reset) -> Self {
133        variant as u8 != 0
134    }
135}
136#[doc = "Field `RESET` reader - Reset Signaling Enable"]
137pub type ResetR = crate::BitReader<Reset>;
138impl ResetR {
139    #[doc = "Get enumerated values variant"]
140    #[inline(always)]
141    pub const fn variant(&self) -> Reset {
142        match self.bits {
143            false => Reset::Disable,
144            true => Reset::Enable,
145        }
146    }
147    #[doc = "Disable"]
148    #[inline(always)]
149    pub fn is_disable(&self) -> bool {
150        *self == Reset::Disable
151    }
152    #[doc = "Enable"]
153    #[inline(always)]
154    pub fn is_enable(&self) -> bool {
155        *self == Reset::Enable
156    }
157}
158#[doc = "Field `RESET` writer - Reset Signaling Enable"]
159pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>;
160impl<'a, REG> ResetW<'a, REG>
161where
162    REG: crate::Writable + crate::RegisterSpec,
163{
164    #[doc = "Disable"]
165    #[inline(always)]
166    pub fn disable(self) -> &'a mut crate::W<REG> {
167        self.variant(Reset::Disable)
168    }
169    #[doc = "Enable"]
170    #[inline(always)]
171    pub fn enable(self) -> &'a mut crate::W<REG> {
172        self.variant(Reset::Enable)
173    }
174}
175#[doc = "Field `TXSUSPENDTOKENBUSY` reader - TXD Suspend And Token Busy"]
176pub type TxsuspendtokenbusyR = crate::BitReader;
177#[doc = "Field `TXSUSPENDTOKENBUSY` writer - TXD Suspend And Token Busy"]
178pub type TxsuspendtokenbusyW<'a, REG> = crate::BitWriter<'a, REG>;
179#[doc = "Field `SE0` reader - Live USB Single-Ended Zero signal"]
180pub type Se0R = crate::BitReader;
181#[doc = "Field `SE0` writer - Live USB Single-Ended Zero signal"]
182pub type Se0W<'a, REG> = crate::BitWriter<'a, REG>;
183#[doc = "Field `JSTATE` reader - Live USB Differential Receiver JSTATE Signal"]
184pub type JstateR = crate::BitReader;
185#[doc = "Field `JSTATE` writer - Live USB Differential Receiver JSTATE Signal"]
186pub type JstateW<'a, REG> = crate::BitWriter<'a, REG>;
187impl R {
188    #[doc = "Bit 0 - USB Enable"]
189    #[inline(always)]
190    pub fn usbensofen(&self) -> UsbensofenR {
191        UsbensofenR::new((self.bits & 1) != 0)
192    }
193    #[doc = "Bit 1 - Odd Reset"]
194    #[inline(always)]
195    pub fn oddrst(&self) -> OddrstR {
196        OddrstR::new(((self.bits >> 1) & 1) != 0)
197    }
198    #[doc = "Bit 2 - Resume"]
199    #[inline(always)]
200    pub fn resume(&self) -> ResumeR {
201        ResumeR::new(((self.bits >> 2) & 1) != 0)
202    }
203    #[doc = "Bit 3 - Host Mode Enable"]
204    #[inline(always)]
205    pub fn hostmodeen(&self) -> HostmodeenR {
206        HostmodeenR::new(((self.bits >> 3) & 1) != 0)
207    }
208    #[doc = "Bit 4 - Reset Signaling Enable"]
209    #[inline(always)]
210    pub fn reset(&self) -> ResetR {
211        ResetR::new(((self.bits >> 4) & 1) != 0)
212    }
213    #[doc = "Bit 5 - TXD Suspend And Token Busy"]
214    #[inline(always)]
215    pub fn txsuspendtokenbusy(&self) -> TxsuspendtokenbusyR {
216        TxsuspendtokenbusyR::new(((self.bits >> 5) & 1) != 0)
217    }
218    #[doc = "Bit 6 - Live USB Single-Ended Zero signal"]
219    #[inline(always)]
220    pub fn se0(&self) -> Se0R {
221        Se0R::new(((self.bits >> 6) & 1) != 0)
222    }
223    #[doc = "Bit 7 - Live USB Differential Receiver JSTATE Signal"]
224    #[inline(always)]
225    pub fn jstate(&self) -> JstateR {
226        JstateR::new(((self.bits >> 7) & 1) != 0)
227    }
228}
229#[cfg(feature = "debug")]
230impl core::fmt::Debug for R {
231    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
232        f.debug_struct("CTL")
233            .field("usbensofen", &self.usbensofen())
234            .field("oddrst", &self.oddrst())
235            .field("resume", &self.resume())
236            .field("hostmodeen", &self.hostmodeen())
237            .field("reset", &self.reset())
238            .field("txsuspendtokenbusy", &self.txsuspendtokenbusy())
239            .field("se0", &self.se0())
240            .field("jstate", &self.jstate())
241            .finish()
242    }
243}
244impl W {
245    #[doc = "Bit 0 - USB Enable"]
246    #[inline(always)]
247    pub fn usbensofen(&mut self) -> UsbensofenW<'_, CtlSpec> {
248        UsbensofenW::new(self, 0)
249    }
250    #[doc = "Bit 1 - Odd Reset"]
251    #[inline(always)]
252    pub fn oddrst(&mut self) -> OddrstW<'_, CtlSpec> {
253        OddrstW::new(self, 1)
254    }
255    #[doc = "Bit 2 - Resume"]
256    #[inline(always)]
257    pub fn resume(&mut self) -> ResumeW<'_, CtlSpec> {
258        ResumeW::new(self, 2)
259    }
260    #[doc = "Bit 3 - Host Mode Enable"]
261    #[inline(always)]
262    pub fn hostmodeen(&mut self) -> HostmodeenW<'_, CtlSpec> {
263        HostmodeenW::new(self, 3)
264    }
265    #[doc = "Bit 4 - Reset Signaling Enable"]
266    #[inline(always)]
267    pub fn reset(&mut self) -> ResetW<'_, CtlSpec> {
268        ResetW::new(self, 4)
269    }
270    #[doc = "Bit 5 - TXD Suspend And Token Busy"]
271    #[inline(always)]
272    pub fn txsuspendtokenbusy(&mut self) -> TxsuspendtokenbusyW<'_, CtlSpec> {
273        TxsuspendtokenbusyW::new(self, 5)
274    }
275    #[doc = "Bit 6 - Live USB Single-Ended Zero signal"]
276    #[inline(always)]
277    pub fn se0(&mut self) -> Se0W<'_, CtlSpec> {
278        Se0W::new(self, 6)
279    }
280    #[doc = "Bit 7 - Live USB Differential Receiver JSTATE Signal"]
281    #[inline(always)]
282    pub fn jstate(&mut self) -> JstateW<'_, CtlSpec> {
283        JstateW::new(self, 7)
284    }
285}
286#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
287pub struct CtlSpec;
288impl crate::RegisterSpec for CtlSpec {
289    type Ux = u8;
290}
291#[doc = "`read()` method returns [`ctl::R`](R) reader structure"]
292impl crate::Readable for CtlSpec {}
293#[doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"]
294impl crate::Writable for CtlSpec {
295    type Safety = crate::Unsafe;
296}
297#[doc = "`reset()` method sets CTL to value 0"]
298impl crate::Resettable for CtlSpec {}
mcxa_pac/usb0/ctl.rs

mcxa_pac/usb0/
ctl.rs
