mcxa_pac/syscon/
remap.rs

1#[doc = "Register `REMAP` reader"]
2pub type R = crate::R<RemapSpec>;
3#[doc = "Register `REMAP` writer"]
4pub type W = crate::W<RemapSpec>;
5#[doc = "RAMX0 address remap for CPU System bus\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Cpu0Sbus {
10    #[doc = "0: RAMX0: alias space is disabled."]
11    Cpu0Sbus0 = 0,
12    #[doc = "1: RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is 0x20000000 + (system ram size - RAMX size)*1024."]
13    Cpu0Sbus1 = 1,
14}
15impl From<Cpu0Sbus> for u8 {
16    #[inline(always)]
17    fn from(variant: Cpu0Sbus) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for Cpu0Sbus {
22    type Ux = u8;
23}
24impl crate::IsEnum for Cpu0Sbus {}
25#[doc = "Field `CPU0_SBUS` reader - RAMX0 address remap for CPU System bus"]
26pub type Cpu0SbusR = crate::FieldReader<Cpu0Sbus>;
27impl Cpu0SbusR {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<Cpu0Sbus> {
31        match self.bits {
32            0 => Some(Cpu0Sbus::Cpu0Sbus0),
33            1 => Some(Cpu0Sbus::Cpu0Sbus1),
34            _ => None,
35        }
36    }
37    #[doc = "RAMX0: alias space is disabled."]
38    #[inline(always)]
39    pub fn is_cpu0_sbus_0(&self) -> bool {
40        *self == Cpu0Sbus::Cpu0Sbus0
41    }
42    #[doc = "RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is 0x20000000 + (system ram size - RAMX size)*1024."]
43    #[inline(always)]
44    pub fn is_cpu0_sbus_1(&self) -> bool {
45        *self == Cpu0Sbus::Cpu0Sbus1
46    }
47}
48#[doc = "Field `CPU0_SBUS` writer - RAMX0 address remap for CPU System bus"]
49pub type Cpu0SbusW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Sbus>;
50impl<'a, REG> Cpu0SbusW<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53    REG::Ux: From<u8>,
54{
55    #[doc = "RAMX0: alias space is disabled."]
56    #[inline(always)]
57    pub fn cpu0_sbus_0(self) -> &'a mut crate::W<REG> {
58        self.variant(Cpu0Sbus::Cpu0Sbus0)
59    }
60    #[doc = "RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is 0x20000000 + (system ram size - RAMX size)*1024."]
61    #[inline(always)]
62    pub fn cpu0_sbus_1(self) -> &'a mut crate::W<REG> {
63        self.variant(Cpu0Sbus::Cpu0Sbus1)
64    }
65}
66#[doc = "RAMX0 address remap for SmartDMA D-BUS\n\nValue on reset: 0"]
67#[cfg_attr(feature = "defmt", derive(defmt::Format))]
68#[derive(Clone, Copy, Debug, PartialEq, Eq)]
69#[repr(u8)]
70pub enum SmartDmaD {
71    #[doc = "0: RAMX0: alias space is disabled."]
72    SmartDmaD0 = 0,
73    #[doc = "1: RAMX0: same alias space as CPU0_SBUS"]
74    SmartDmaD1 = 1,
75}
76impl From<SmartDmaD> for u8 {
77    #[inline(always)]
78    fn from(variant: SmartDmaD) -> Self {
79        variant as _
80    }
81}
82impl crate::FieldSpec for SmartDmaD {
83    type Ux = u8;
84}
85impl crate::IsEnum for SmartDmaD {}
86#[doc = "Field `SmartDMA_D` reader - RAMX0 address remap for SmartDMA D-BUS"]
87pub type SmartDmaDR = crate::FieldReader<SmartDmaD>;
88impl SmartDmaDR {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> Option<SmartDmaD> {
92        match self.bits {
93            0 => Some(SmartDmaD::SmartDmaD0),
94            1 => Some(SmartDmaD::SmartDmaD1),
95            _ => None,
96        }
97    }
98    #[doc = "RAMX0: alias space is disabled."]
99    #[inline(always)]
100    pub fn is_smart_dma_d_0(&self) -> bool {
101        *self == SmartDmaD::SmartDmaD0
102    }
103    #[doc = "RAMX0: same alias space as CPU0_SBUS"]
104    #[inline(always)]
105    pub fn is_smart_dma_d_1(&self) -> bool {
106        *self == SmartDmaD::SmartDmaD1
107    }
108}
109#[doc = "Field `SmartDMA_D` writer - RAMX0 address remap for SmartDMA D-BUS"]
110pub type SmartDmaDW<'a, REG> = crate::FieldWriter<'a, REG, 2, SmartDmaD>;
111impl<'a, REG> SmartDmaDW<'a, REG>
112where
113    REG: crate::Writable + crate::RegisterSpec,
114    REG::Ux: From<u8>,
115{
116    #[doc = "RAMX0: alias space is disabled."]
117    #[inline(always)]
118    pub fn smart_dma_d_0(self) -> &'a mut crate::W<REG> {
119        self.variant(SmartDmaD::SmartDmaD0)
120    }
121    #[doc = "RAMX0: same alias space as CPU0_SBUS"]
122    #[inline(always)]
123    pub fn smart_dma_d_1(self) -> &'a mut crate::W<REG> {
124        self.variant(SmartDmaD::SmartDmaD1)
125    }
126}
127#[doc = "RAMX0 address remap for SmartDMA I-BUS\n\nValue on reset: 0"]
128#[cfg_attr(feature = "defmt", derive(defmt::Format))]
129#[derive(Clone, Copy, Debug, PartialEq, Eq)]
130#[repr(u8)]
131pub enum SmartDmaI {
132    #[doc = "0: RAMX0: alias space is disabled."]
133    SmartDmaI0 = 0,
134    #[doc = "1: RAMX0: same alias space as CPU0_SBUS"]
135    SmartDmaI1 = 1,
136}
137impl From<SmartDmaI> for u8 {
138    #[inline(always)]
139    fn from(variant: SmartDmaI) -> Self {
140        variant as _
141    }
142}
143impl crate::FieldSpec for SmartDmaI {
144    type Ux = u8;
145}
146impl crate::IsEnum for SmartDmaI {}
147#[doc = "Field `SmartDMA_I` reader - RAMX0 address remap for SmartDMA I-BUS"]
148pub type SmartDmaIR = crate::FieldReader<SmartDmaI>;
149impl SmartDmaIR {
150    #[doc = "Get enumerated values variant"]
151    #[inline(always)]
152    pub const fn variant(&self) -> Option<SmartDmaI> {
153        match self.bits {
154            0 => Some(SmartDmaI::SmartDmaI0),
155            1 => Some(SmartDmaI::SmartDmaI1),
156            _ => None,
157        }
158    }
159    #[doc = "RAMX0: alias space is disabled."]
160    #[inline(always)]
161    pub fn is_smart_dma_i_0(&self) -> bool {
162        *self == SmartDmaI::SmartDmaI0
163    }
164    #[doc = "RAMX0: same alias space as CPU0_SBUS"]
165    #[inline(always)]
166    pub fn is_smart_dma_i_1(&self) -> bool {
167        *self == SmartDmaI::SmartDmaI1
168    }
169}
170#[doc = "Field `SmartDMA_I` writer - RAMX0 address remap for SmartDMA I-BUS"]
171pub type SmartDmaIW<'a, REG> = crate::FieldWriter<'a, REG, 2, SmartDmaI>;
172impl<'a, REG> SmartDmaIW<'a, REG>
173where
174    REG: crate::Writable + crate::RegisterSpec,
175    REG::Ux: From<u8>,
176{
177    #[doc = "RAMX0: alias space is disabled."]
178    #[inline(always)]
179    pub fn smart_dma_i_0(self) -> &'a mut crate::W<REG> {
180        self.variant(SmartDmaI::SmartDmaI0)
181    }
182    #[doc = "RAMX0: same alias space as CPU0_SBUS"]
183    #[inline(always)]
184    pub fn smart_dma_i_1(self) -> &'a mut crate::W<REG> {
185        self.variant(SmartDmaI::SmartDmaI1)
186    }
187}
188#[doc = "RAMX0 address remap for DMA0\n\nValue on reset: 0"]
189#[cfg_attr(feature = "defmt", derive(defmt::Format))]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191#[repr(u8)]
192pub enum Dma0 {
193    #[doc = "0: RAMX0: alias space is disabled."]
194    Dma0_0 = 0,
195    #[doc = "1: RAMX0: same alias space as CPU0_SBUS"]
196    Dma0_1 = 1,
197}
198impl From<Dma0> for u8 {
199    #[inline(always)]
200    fn from(variant: Dma0) -> Self {
201        variant as _
202    }
203}
204impl crate::FieldSpec for Dma0 {
205    type Ux = u8;
206}
207impl crate::IsEnum for Dma0 {}
208#[doc = "Field `DMA0` reader - RAMX0 address remap for DMA0"]
209pub type Dma0R = crate::FieldReader<Dma0>;
210impl Dma0R {
211    #[doc = "Get enumerated values variant"]
212    #[inline(always)]
213    pub const fn variant(&self) -> Option<Dma0> {
214        match self.bits {
215            0 => Some(Dma0::Dma0_0),
216            1 => Some(Dma0::Dma0_1),
217            _ => None,
218        }
219    }
220    #[doc = "RAMX0: alias space is disabled."]
221    #[inline(always)]
222    pub fn is_dma0_0(&self) -> bool {
223        *self == Dma0::Dma0_0
224    }
225    #[doc = "RAMX0: same alias space as CPU0_SBUS"]
226    #[inline(always)]
227    pub fn is_dma0_1(&self) -> bool {
228        *self == Dma0::Dma0_1
229    }
230}
231#[doc = "Field `DMA0` writer - RAMX0 address remap for DMA0"]
232pub type Dma0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Dma0>;
233impl<'a, REG> Dma0W<'a, REG>
234where
235    REG: crate::Writable + crate::RegisterSpec,
236    REG::Ux: From<u8>,
237{
238    #[doc = "RAMX0: alias space is disabled."]
239    #[inline(always)]
240    pub fn dma0_0(self) -> &'a mut crate::W<REG> {
241        self.variant(Dma0::Dma0_0)
242    }
243    #[doc = "RAMX0: same alias space as CPU0_SBUS"]
244    #[inline(always)]
245    pub fn dma0_1(self) -> &'a mut crate::W<REG> {
246        self.variant(Dma0::Dma0_1)
247    }
248}
249#[doc = "RAMX0 address remap for PKC\n\nValue on reset: 0"]
250#[cfg_attr(feature = "defmt", derive(defmt::Format))]
251#[derive(Clone, Copy, Debug, PartialEq, Eq)]
252#[repr(u8)]
253pub enum Pkc {
254    #[doc = "0: RAMX0: alias space is disabled."]
255    Pkc0 = 0,
256    #[doc = "1: RAMX0: same alias space as CPU0_SBUS"]
257    Pkc1 = 1,
258}
259impl From<Pkc> for u8 {
260    #[inline(always)]
261    fn from(variant: Pkc) -> Self {
262        variant as _
263    }
264}
265impl crate::FieldSpec for Pkc {
266    type Ux = u8;
267}
268impl crate::IsEnum for Pkc {}
269#[doc = "Field `PKC` reader - RAMX0 address remap for PKC"]
270pub type PkcR = crate::FieldReader<Pkc>;
271impl PkcR {
272    #[doc = "Get enumerated values variant"]
273    #[inline(always)]
274    pub const fn variant(&self) -> Option<Pkc> {
275        match self.bits {
276            0 => Some(Pkc::Pkc0),
277            1 => Some(Pkc::Pkc1),
278            _ => None,
279        }
280    }
281    #[doc = "RAMX0: alias space is disabled."]
282    #[inline(always)]
283    pub fn is_pkc_0(&self) -> bool {
284        *self == Pkc::Pkc0
285    }
286    #[doc = "RAMX0: same alias space as CPU0_SBUS"]
287    #[inline(always)]
288    pub fn is_pkc_1(&self) -> bool {
289        *self == Pkc::Pkc1
290    }
291}
292#[doc = "Field `PKC` writer - RAMX0 address remap for PKC"]
293pub type PkcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pkc>;
294impl<'a, REG> PkcW<'a, REG>
295where
296    REG: crate::Writable + crate::RegisterSpec,
297    REG::Ux: From<u8>,
298{
299    #[doc = "RAMX0: alias space is disabled."]
300    #[inline(always)]
301    pub fn pkc_0(self) -> &'a mut crate::W<REG> {
302        self.variant(Pkc::Pkc0)
303    }
304    #[doc = "RAMX0: same alias space as CPU0_SBUS"]
305    #[inline(always)]
306    pub fn pkc_1(self) -> &'a mut crate::W<REG> {
307        self.variant(Pkc::Pkc1)
308    }
309}
310#[doc = "RAMX0 address remap for USB0\n\nValue on reset: 0"]
311#[cfg_attr(feature = "defmt", derive(defmt::Format))]
312#[derive(Clone, Copy, Debug, PartialEq, Eq)]
313#[repr(u8)]
314pub enum Usb0 {
315    #[doc = "0: RAMX0: alias space is disabled."]
316    Usb0_0 = 0,
317    #[doc = "1: RAMX0: same alias space as CPU0_SBUS"]
318    Usb0_1 = 1,
319}
320impl From<Usb0> for u8 {
321    #[inline(always)]
322    fn from(variant: Usb0) -> Self {
323        variant as _
324    }
325}
326impl crate::FieldSpec for Usb0 {
327    type Ux = u8;
328}
329impl crate::IsEnum for Usb0 {}
330#[doc = "Field `USB0` reader - RAMX0 address remap for USB0"]
331pub type Usb0R = crate::FieldReader<Usb0>;
332impl Usb0R {
333    #[doc = "Get enumerated values variant"]
334    #[inline(always)]
335    pub const fn variant(&self) -> Option<Usb0> {
336        match self.bits {
337            0 => Some(Usb0::Usb0_0),
338            1 => Some(Usb0::Usb0_1),
339            _ => None,
340        }
341    }
342    #[doc = "RAMX0: alias space is disabled."]
343    #[inline(always)]
344    pub fn is_usb0_0(&self) -> bool {
345        *self == Usb0::Usb0_0
346    }
347    #[doc = "RAMX0: same alias space as CPU0_SBUS"]
348    #[inline(always)]
349    pub fn is_usb0_1(&self) -> bool {
350        *self == Usb0::Usb0_1
351    }
352}
353#[doc = "Field `USB0` writer - RAMX0 address remap for USB0"]
354pub type Usb0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Usb0>;
355impl<'a, REG> Usb0W<'a, REG>
356where
357    REG: crate::Writable + crate::RegisterSpec,
358    REG::Ux: From<u8>,
359{
360    #[doc = "RAMX0: alias space is disabled."]
361    #[inline(always)]
362    pub fn usb0_0(self) -> &'a mut crate::W<REG> {
363        self.variant(Usb0::Usb0_0)
364    }
365    #[doc = "RAMX0: same alias space as CPU0_SBUS"]
366    #[inline(always)]
367    pub fn usb0_1(self) -> &'a mut crate::W<REG> {
368        self.variant(Usb0::Usb0_1)
369    }
370}
371#[doc = "This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset.\n\nValue on reset: 0"]
372#[cfg_attr(feature = "defmt", derive(defmt::Format))]
373#[derive(Clone, Copy, Debug, PartialEq, Eq)]
374pub enum Lock {
375    #[doc = "0: This register is not locked and can be altered."]
376    Lock0 = 0,
377    #[doc = "1: This register is locked and cannot be altered until a system reset."]
378    Lock1 = 1,
379}
380impl From<Lock> for bool {
381    #[inline(always)]
382    fn from(variant: Lock) -> Self {
383        variant as u8 != 0
384    }
385}
386#[doc = "Field `LOCK` reader - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."]
387pub type LockR = crate::BitReader<Lock>;
388impl LockR {
389    #[doc = "Get enumerated values variant"]
390    #[inline(always)]
391    pub const fn variant(&self) -> Lock {
392        match self.bits {
393            false => Lock::Lock0,
394            true => Lock::Lock1,
395        }
396    }
397    #[doc = "This register is not locked and can be altered."]
398    #[inline(always)]
399    pub fn is_lock_0(&self) -> bool {
400        *self == Lock::Lock0
401    }
402    #[doc = "This register is locked and cannot be altered until a system reset."]
403    #[inline(always)]
404    pub fn is_lock_1(&self) -> bool {
405        *self == Lock::Lock1
406    }
407}
408#[doc = "Field `LOCK` writer - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."]
409pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>;
410impl<'a, REG> LockW<'a, REG>
411where
412    REG: crate::Writable + crate::RegisterSpec,
413{
414    #[doc = "This register is not locked and can be altered."]
415    #[inline(always)]
416    pub fn lock_0(self) -> &'a mut crate::W<REG> {
417        self.variant(Lock::Lock0)
418    }
419    #[doc = "This register is locked and cannot be altered until a system reset."]
420    #[inline(always)]
421    pub fn lock_1(self) -> &'a mut crate::W<REG> {
422        self.variant(Lock::Lock1)
423    }
424}
425impl R {
426    #[doc = "Bits 2:3 - RAMX0 address remap for CPU System bus"]
427    #[inline(always)]
428    pub fn cpu0_sbus(&self) -> Cpu0SbusR {
429        Cpu0SbusR::new(((self.bits >> 2) & 3) as u8)
430    }
431    #[doc = "Bits 4:5 - RAMX0 address remap for SmartDMA D-BUS"]
432    #[inline(always)]
433    pub fn smart_dma_d(&self) -> SmartDmaDR {
434        SmartDmaDR::new(((self.bits >> 4) & 3) as u8)
435    }
436    #[doc = "Bits 6:7 - RAMX0 address remap for SmartDMA I-BUS"]
437    #[inline(always)]
438    pub fn smart_dma_i(&self) -> SmartDmaIR {
439        SmartDmaIR::new(((self.bits >> 6) & 3) as u8)
440    }
441    #[doc = "Bits 8:9 - RAMX0 address remap for DMA0"]
442    #[inline(always)]
443    pub fn dma0(&self) -> Dma0R {
444        Dma0R::new(((self.bits >> 8) & 3) as u8)
445    }
446    #[doc = "Bits 12:13 - RAMX0 address remap for PKC"]
447    #[inline(always)]
448    pub fn pkc(&self) -> PkcR {
449        PkcR::new(((self.bits >> 12) & 3) as u8)
450    }
451    #[doc = "Bits 24:25 - RAMX0 address remap for USB0"]
452    #[inline(always)]
453    pub fn usb0(&self) -> Usb0R {
454        Usb0R::new(((self.bits >> 24) & 3) as u8)
455    }
456    #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."]
457    #[inline(always)]
458    pub fn lock(&self) -> LockR {
459        LockR::new(((self.bits >> 31) & 1) != 0)
460    }
461}
462#[cfg(feature = "debug")]
463impl core::fmt::Debug for R {
464    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
465        f.debug_struct("REMAP")
466            .field("cpu0_sbus", &self.cpu0_sbus())
467            .field("smart_dma_d", &self.smart_dma_d())
468            .field("smart_dma_i", &self.smart_dma_i())
469            .field("dma0", &self.dma0())
470            .field("pkc", &self.pkc())
471            .field("usb0", &self.usb0())
472            .field("lock", &self.lock())
473            .finish()
474    }
475}
476impl W {
477    #[doc = "Bits 2:3 - RAMX0 address remap for CPU System bus"]
478    #[inline(always)]
479    pub fn cpu0_sbus(&mut self) -> Cpu0SbusW<'_, RemapSpec> {
480        Cpu0SbusW::new(self, 2)
481    }
482    #[doc = "Bits 4:5 - RAMX0 address remap for SmartDMA D-BUS"]
483    #[inline(always)]
484    pub fn smart_dma_d(&mut self) -> SmartDmaDW<'_, RemapSpec> {
485        SmartDmaDW::new(self, 4)
486    }
487    #[doc = "Bits 6:7 - RAMX0 address remap for SmartDMA I-BUS"]
488    #[inline(always)]
489    pub fn smart_dma_i(&mut self) -> SmartDmaIW<'_, RemapSpec> {
490        SmartDmaIW::new(self, 6)
491    }
492    #[doc = "Bits 8:9 - RAMX0 address remap for DMA0"]
493    #[inline(always)]
494    pub fn dma0(&mut self) -> Dma0W<'_, RemapSpec> {
495        Dma0W::new(self, 8)
496    }
497    #[doc = "Bits 12:13 - RAMX0 address remap for PKC"]
498    #[inline(always)]
499    pub fn pkc(&mut self) -> PkcW<'_, RemapSpec> {
500        PkcW::new(self, 12)
501    }
502    #[doc = "Bits 24:25 - RAMX0 address remap for USB0"]
503    #[inline(always)]
504    pub fn usb0(&mut self) -> Usb0W<'_, RemapSpec> {
505        Usb0W::new(self, 24)
506    }
507    #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."]
508    #[inline(always)]
509    pub fn lock(&mut self) -> LockW<'_, RemapSpec> {
510        LockW::new(self, 31)
511    }
512}
513#[doc = "AHB Matrix Remap Control\n\nYou can [`read`](crate::Reg::read) this register and get [`remap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
514pub struct RemapSpec;
515impl crate::RegisterSpec for RemapSpec {
516    type Ux = u32;
517}
518#[doc = "`read()` method returns [`remap::R`](R) reader structure"]
519impl crate::Readable for RemapSpec {}
520#[doc = "`write(|w| ..)` method takes [`remap::W`](W) writer structure"]
521impl crate::Writable for RemapSpec {
522    type Safety = crate::Unsafe;
523}
524#[doc = "`reset()` method sets REMAP to value 0"]
525impl crate::Resettable for RemapSpec {}
mcxa_pac/syscon/remap.rs

mcxa_pac/syscon/
remap.rs
