mcxa_pac/syscon/
ahbclkdiv.rs

1#[doc = "Register `AHBCLKDIV` reader"]
2pub type R = crate::R<AhbclkdivSpec>;
3#[doc = "Register `AHBCLKDIV` writer"]
4pub type W = crate::W<AhbclkdivSpec>;
5#[doc = "Field `DIV` reader - Clock divider value"]
6pub type DivR = crate::FieldReader;
7#[doc = "Field `DIV` writer - Clock divider value"]
8pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Divider status flag\n\nValue on reset: 0"]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12pub enum Unstab {
13    #[doc = "0: Divider clock is stable"]
14    Stable = 0,
15    #[doc = "1: Clock frequency is not stable"]
16    Ongoing = 1,
17}
18impl From<Unstab> for bool {
19    #[inline(always)]
20    fn from(variant: Unstab) -> Self {
21        variant as u8 != 0
22    }
23}
24#[doc = "Field `UNSTAB` reader - Divider status flag"]
25pub type UnstabR = crate::BitReader<Unstab>;
26impl UnstabR {
27    #[doc = "Get enumerated values variant"]
28    #[inline(always)]
29    pub const fn variant(&self) -> Unstab {
30        match self.bits {
31            false => Unstab::Stable,
32            true => Unstab::Ongoing,
33        }
34    }
35    #[doc = "Divider clock is stable"]
36    #[inline(always)]
37    pub fn is_stable(&self) -> bool {
38        *self == Unstab::Stable
39    }
40    #[doc = "Clock frequency is not stable"]
41    #[inline(always)]
42    pub fn is_ongoing(&self) -> bool {
43        *self == Unstab::Ongoing
44    }
45}
46impl R {
47    #[doc = "Bits 0:7 - Clock divider value"]
48    #[inline(always)]
49    pub fn div(&self) -> DivR {
50        DivR::new((self.bits & 0xff) as u8)
51    }
52    #[doc = "Bit 31 - Divider status flag"]
53    #[inline(always)]
54    pub fn unstab(&self) -> UnstabR {
55        UnstabR::new(((self.bits >> 31) & 1) != 0)
56    }
57}
58#[cfg(feature = "debug")]
59impl core::fmt::Debug for R {
60    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
61        f.debug_struct("AHBCLKDIV")
62            .field("div", &self.div())
63            .field("unstab", &self.unstab())
64            .finish()
65    }
66}
67impl W {
68    #[doc = "Bits 0:7 - Clock divider value"]
69    #[inline(always)]
70    pub fn div(&mut self) -> DivW<'_, AhbclkdivSpec> {
71        DivW::new(self, 0)
72    }
73}
74#[doc = "System Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`ahbclkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbclkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
75pub struct AhbclkdivSpec;
76impl crate::RegisterSpec for AhbclkdivSpec {
77    type Ux = u32;
78}
79#[doc = "`read()` method returns [`ahbclkdiv::R`](R) reader structure"]
80impl crate::Readable for AhbclkdivSpec {}
81#[doc = "`write(|w| ..)` method takes [`ahbclkdiv::W`](W) writer structure"]
82impl crate::Writable for AhbclkdivSpec {
83    type Safety = crate::Unsafe;
84}
85#[doc = "`reset()` method sets AHBCLKDIV to value 0"]
86impl crate::Resettable for AhbclkdivSpec {}
mcxa_pac/syscon/ahbclkdiv.rs

mcxa_pac/syscon/
ahbclkdiv.rs
