mcxa_pac/scg0/
spllctrl.rs

1#[doc = "Register `SPLLCTRL` reader"]
2pub type R = crate::R<SpllctrlSpec>;
3#[doc = "Register `SPLLCTRL` writer"]
4pub type W = crate::W<SpllctrlSpec>;
5#[doc = "Field `SELR` reader - Bandwidth select R (resistor) value."]
6pub type SelrR = crate::FieldReader;
7#[doc = "Field `SELR` writer - Bandwidth select R (resistor) value."]
8pub type SelrW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `SELI` reader - Bandwidth select I (interation) value."]
10pub type SeliR = crate::FieldReader;
11#[doc = "Field `SELI` writer - Bandwidth select I (interation) value."]
12pub type SeliW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `SELP` reader - Bandwidth select P (proportional) value."]
14pub type SelpR = crate::FieldReader;
15#[doc = "Field `SELP` writer - Bandwidth select P (proportional) value."]
16pub type SelpW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
17#[doc = "Bypass of the divide-by-2 divider\n\nValue on reset: 0"]
18#[cfg_attr(feature = "defmt", derive(defmt::Format))]
19#[derive(Clone, Copy, Debug, PartialEq, Eq)]
20pub enum Bypasspostdiv2 {
21    #[doc = "0: Use the divide-by-2 divider in the post-divider."]
22    NotBypassed = 0,
23    #[doc = "1: Bypass of the divide-by-2 divider in the post-divider."]
24    Bypassed = 1,
25}
26impl From<Bypasspostdiv2> for bool {
27    #[inline(always)]
28    fn from(variant: Bypasspostdiv2) -> Self {
29        variant as u8 != 0
30    }
31}
32#[doc = "Field `BYPASSPOSTDIV2` reader - Bypass of the divide-by-2 divider"]
33pub type Bypasspostdiv2R = crate::BitReader<Bypasspostdiv2>;
34impl Bypasspostdiv2R {
35    #[doc = "Get enumerated values variant"]
36    #[inline(always)]
37    pub const fn variant(&self) -> Bypasspostdiv2 {
38        match self.bits {
39            false => Bypasspostdiv2::NotBypassed,
40            true => Bypasspostdiv2::Bypassed,
41        }
42    }
43    #[doc = "Use the divide-by-2 divider in the post-divider."]
44    #[inline(always)]
45    pub fn is_not_bypassed(&self) -> bool {
46        *self == Bypasspostdiv2::NotBypassed
47    }
48    #[doc = "Bypass of the divide-by-2 divider in the post-divider."]
49    #[inline(always)]
50    pub fn is_bypassed(&self) -> bool {
51        *self == Bypasspostdiv2::Bypassed
52    }
53}
54#[doc = "Field `BYPASSPOSTDIV2` writer - Bypass of the divide-by-2 divider"]
55pub type Bypasspostdiv2W<'a, REG> = crate::BitWriter<'a, REG, Bypasspostdiv2>;
56impl<'a, REG> Bypasspostdiv2W<'a, REG>
57where
58    REG: crate::Writable + crate::RegisterSpec,
59{
60    #[doc = "Use the divide-by-2 divider in the post-divider."]
61    #[inline(always)]
62    pub fn not_bypassed(self) -> &'a mut crate::W<REG> {
63        self.variant(Bypasspostdiv2::NotBypassed)
64    }
65    #[doc = "Bypass of the divide-by-2 divider in the post-divider."]
66    #[inline(always)]
67    pub fn bypassed(self) -> &'a mut crate::W<REG> {
68        self.variant(Bypasspostdiv2::Bypassed)
69    }
70}
71#[doc = "Up Limiter.\n\nValue on reset: 0"]
72#[cfg_attr(feature = "defmt", derive(defmt::Format))]
73#[derive(Clone, Copy, Debug, PartialEq, Eq)]
74pub enum Limupoff {
75    #[doc = "0: Application set to non Spectrum and Fractional applications."]
76    Disabled = 0,
77    #[doc = "1: Application set to Spectrum and Fractional applications."]
78    Enabled = 1,
79}
80impl From<Limupoff> for bool {
81    #[inline(always)]
82    fn from(variant: Limupoff) -> Self {
83        variant as u8 != 0
84    }
85}
86#[doc = "Field `LIMUPOFF` reader - Up Limiter."]
87pub type LimupoffR = crate::BitReader<Limupoff>;
88impl LimupoffR {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> Limupoff {
92        match self.bits {
93            false => Limupoff::Disabled,
94            true => Limupoff::Enabled,
95        }
96    }
97    #[doc = "Application set to non Spectrum and Fractional applications."]
98    #[inline(always)]
99    pub fn is_disabled(&self) -> bool {
100        *self == Limupoff::Disabled
101    }
102    #[doc = "Application set to Spectrum and Fractional applications."]
103    #[inline(always)]
104    pub fn is_enabled(&self) -> bool {
105        *self == Limupoff::Enabled
106    }
107}
108#[doc = "Field `LIMUPOFF` writer - Up Limiter."]
109pub type LimupoffW<'a, REG> = crate::BitWriter<'a, REG, Limupoff>;
110impl<'a, REG> LimupoffW<'a, REG>
111where
112    REG: crate::Writable + crate::RegisterSpec,
113{
114    #[doc = "Application set to non Spectrum and Fractional applications."]
115    #[inline(always)]
116    pub fn disabled(self) -> &'a mut crate::W<REG> {
117        self.variant(Limupoff::Disabled)
118    }
119    #[doc = "Application set to Spectrum and Fractional applications."]
120    #[inline(always)]
121    pub fn enabled(self) -> &'a mut crate::W<REG> {
122        self.variant(Limupoff::Enabled)
123    }
124}
125#[doc = "Control of the bandwidth of the PLL.\n\nValue on reset: 0"]
126#[cfg_attr(feature = "defmt", derive(defmt::Format))]
127#[derive(Clone, Copy, Debug, PartialEq, Eq)]
128pub enum Banddirect {
129    #[doc = "0: The bandwidth is changed synchronously with the feedback-divider"]
130    Disabled = 0,
131    #[doc = "1: Modifies the bandwidth of the PLL directly"]
132    Enabled = 1,
133}
134impl From<Banddirect> for bool {
135    #[inline(always)]
136    fn from(variant: Banddirect) -> Self {
137        variant as u8 != 0
138    }
139}
140#[doc = "Field `BANDDIRECT` reader - Control of the bandwidth of the PLL."]
141pub type BanddirectR = crate::BitReader<Banddirect>;
142impl BanddirectR {
143    #[doc = "Get enumerated values variant"]
144    #[inline(always)]
145    pub const fn variant(&self) -> Banddirect {
146        match self.bits {
147            false => Banddirect::Disabled,
148            true => Banddirect::Enabled,
149        }
150    }
151    #[doc = "The bandwidth is changed synchronously with the feedback-divider"]
152    #[inline(always)]
153    pub fn is_disabled(&self) -> bool {
154        *self == Banddirect::Disabled
155    }
156    #[doc = "Modifies the bandwidth of the PLL directly"]
157    #[inline(always)]
158    pub fn is_enabled(&self) -> bool {
159        *self == Banddirect::Enabled
160    }
161}
162#[doc = "Field `BANDDIRECT` writer - Control of the bandwidth of the PLL."]
163pub type BanddirectW<'a, REG> = crate::BitWriter<'a, REG, Banddirect>;
164impl<'a, REG> BanddirectW<'a, REG>
165where
166    REG: crate::Writable + crate::RegisterSpec,
167{
168    #[doc = "The bandwidth is changed synchronously with the feedback-divider"]
169    #[inline(always)]
170    pub fn disabled(self) -> &'a mut crate::W<REG> {
171        self.variant(Banddirect::Disabled)
172    }
173    #[doc = "Modifies the bandwidth of the PLL directly"]
174    #[inline(always)]
175    pub fn enabled(self) -> &'a mut crate::W<REG> {
176        self.variant(Banddirect::Enabled)
177    }
178}
179#[doc = "Bypass of the pre-divider.\n\nValue on reset: 0"]
180#[cfg_attr(feature = "defmt", derive(defmt::Format))]
181#[derive(Clone, Copy, Debug, PartialEq, Eq)]
182pub enum Bypassprediv {
183    #[doc = "0: Use the pre-divider"]
184    Disabled = 0,
185    #[doc = "1: Bypass of the pre-divider"]
186    Enabled = 1,
187}
188impl From<Bypassprediv> for bool {
189    #[inline(always)]
190    fn from(variant: Bypassprediv) -> Self {
191        variant as u8 != 0
192    }
193}
194#[doc = "Field `BYPASSPREDIV` reader - Bypass of the pre-divider."]
195pub type BypasspredivR = crate::BitReader<Bypassprediv>;
196impl BypasspredivR {
197    #[doc = "Get enumerated values variant"]
198    #[inline(always)]
199    pub const fn variant(&self) -> Bypassprediv {
200        match self.bits {
201            false => Bypassprediv::Disabled,
202            true => Bypassprediv::Enabled,
203        }
204    }
205    #[doc = "Use the pre-divider"]
206    #[inline(always)]
207    pub fn is_disabled(&self) -> bool {
208        *self == Bypassprediv::Disabled
209    }
210    #[doc = "Bypass of the pre-divider"]
211    #[inline(always)]
212    pub fn is_enabled(&self) -> bool {
213        *self == Bypassprediv::Enabled
214    }
215}
216#[doc = "Field `BYPASSPREDIV` writer - Bypass of the pre-divider."]
217pub type BypasspredivW<'a, REG> = crate::BitWriter<'a, REG, Bypassprediv>;
218impl<'a, REG> BypasspredivW<'a, REG>
219where
220    REG: crate::Writable + crate::RegisterSpec,
221{
222    #[doc = "Use the pre-divider"]
223    #[inline(always)]
224    pub fn disabled(self) -> &'a mut crate::W<REG> {
225        self.variant(Bypassprediv::Disabled)
226    }
227    #[doc = "Bypass of the pre-divider"]
228    #[inline(always)]
229    pub fn enabled(self) -> &'a mut crate::W<REG> {
230        self.variant(Bypassprediv::Enabled)
231    }
232}
233#[doc = "Bypass of the post-divider.\n\nValue on reset: 0"]
234#[cfg_attr(feature = "defmt", derive(defmt::Format))]
235#[derive(Clone, Copy, Debug, PartialEq, Eq)]
236pub enum Bypasspostdiv {
237    #[doc = "0: Use the post-divider"]
238    Disabled = 0,
239    #[doc = "1: Bypass of the post-divider"]
240    Enabled = 1,
241}
242impl From<Bypasspostdiv> for bool {
243    #[inline(always)]
244    fn from(variant: Bypasspostdiv) -> Self {
245        variant as u8 != 0
246    }
247}
248#[doc = "Field `BYPASSPOSTDIV` reader - Bypass of the post-divider."]
249pub type BypasspostdivR = crate::BitReader<Bypasspostdiv>;
250impl BypasspostdivR {
251    #[doc = "Get enumerated values variant"]
252    #[inline(always)]
253    pub const fn variant(&self) -> Bypasspostdiv {
254        match self.bits {
255            false => Bypasspostdiv::Disabled,
256            true => Bypasspostdiv::Enabled,
257        }
258    }
259    #[doc = "Use the post-divider"]
260    #[inline(always)]
261    pub fn is_disabled(&self) -> bool {
262        *self == Bypasspostdiv::Disabled
263    }
264    #[doc = "Bypass of the post-divider"]
265    #[inline(always)]
266    pub fn is_enabled(&self) -> bool {
267        *self == Bypasspostdiv::Enabled
268    }
269}
270#[doc = "Field `BYPASSPOSTDIV` writer - Bypass of the post-divider."]
271pub type BypasspostdivW<'a, REG> = crate::BitWriter<'a, REG, Bypasspostdiv>;
272impl<'a, REG> BypasspostdivW<'a, REG>
273where
274    REG: crate::Writable + crate::RegisterSpec,
275{
276    #[doc = "Use the post-divider"]
277    #[inline(always)]
278    pub fn disabled(self) -> &'a mut crate::W<REG> {
279        self.variant(Bypasspostdiv::Disabled)
280    }
281    #[doc = "Bypass of the post-divider"]
282    #[inline(always)]
283    pub fn enabled(self) -> &'a mut crate::W<REG> {
284        self.variant(Bypasspostdiv::Enabled)
285    }
286}
287#[doc = "Free Running Mode Enable\n\nValue on reset: 0"]
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum Frm {
291    #[doc = "0: Free running mode disabled"]
292    Disabled = 0,
293    #[doc = "1: Free running mode enabled"]
294    Enabled = 1,
295}
296impl From<Frm> for bool {
297    #[inline(always)]
298    fn from(variant: Frm) -> Self {
299        variant as u8 != 0
300    }
301}
302#[doc = "Field `FRM` reader - Free Running Mode Enable"]
303pub type FrmR = crate::BitReader<Frm>;
304impl FrmR {
305    #[doc = "Get enumerated values variant"]
306    #[inline(always)]
307    pub const fn variant(&self) -> Frm {
308        match self.bits {
309            false => Frm::Disabled,
310            true => Frm::Enabled,
311        }
312    }
313    #[doc = "Free running mode disabled"]
314    #[inline(always)]
315    pub fn is_disabled(&self) -> bool {
316        *self == Frm::Disabled
317    }
318    #[doc = "Free running mode enabled"]
319    #[inline(always)]
320    pub fn is_enabled(&self) -> bool {
321        *self == Frm::Enabled
322    }
323}
324#[doc = "Field `FRM` writer - Free Running Mode Enable"]
325pub type FrmW<'a, REG> = crate::BitWriter<'a, REG, Frm>;
326impl<'a, REG> FrmW<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    #[doc = "Free running mode disabled"]
331    #[inline(always)]
332    pub fn disabled(self) -> &'a mut crate::W<REG> {
333        self.variant(Frm::Disabled)
334    }
335    #[doc = "Free running mode enabled"]
336    #[inline(always)]
337    pub fn enabled(self) -> &'a mut crate::W<REG> {
338        self.variant(Frm::Enabled)
339    }
340}
341#[doc = "Clock Source\n\nValue on reset: 0"]
342#[cfg_attr(feature = "defmt", derive(defmt::Format))]
343#[derive(Clone, Copy, Debug, PartialEq, Eq)]
344#[repr(u8)]
345pub enum Source {
346    #[doc = "0: SOSC"]
347    Sosc = 0,
348    #[doc = "1: FIRC 45 MHz clock. FIRC_SCLK_PERIPH_EN needs to be set to use FIRC 45 MHz clock."]
349    Firc = 1,
350    #[doc = "2: ROSC"]
351    Rsvd = 2,
352    #[doc = "3: SIRC 12 MHz clock"]
353    Sirc = 3,
354}
355impl From<Source> for u8 {
356    #[inline(always)]
357    fn from(variant: Source) -> Self {
358        variant as _
359    }
360}
361impl crate::FieldSpec for Source {
362    type Ux = u8;
363}
364impl crate::IsEnum for Source {}
365#[doc = "Field `SOURCE` reader - Clock Source"]
366pub type SourceR = crate::FieldReader<Source>;
367impl SourceR {
368    #[doc = "Get enumerated values variant"]
369    #[inline(always)]
370    pub const fn variant(&self) -> Source {
371        match self.bits {
372            0 => Source::Sosc,
373            1 => Source::Firc,
374            2 => Source::Rsvd,
375            3 => Source::Sirc,
376            _ => unreachable!(),
377        }
378    }
379    #[doc = "SOSC"]
380    #[inline(always)]
381    pub fn is_sosc(&self) -> bool {
382        *self == Source::Sosc
383    }
384    #[doc = "FIRC 45 MHz clock. FIRC_SCLK_PERIPH_EN needs to be set to use FIRC 45 MHz clock."]
385    #[inline(always)]
386    pub fn is_firc(&self) -> bool {
387        *self == Source::Firc
388    }
389    #[doc = "ROSC"]
390    #[inline(always)]
391    pub fn is_rsvd(&self) -> bool {
392        *self == Source::Rsvd
393    }
394    #[doc = "SIRC 12 MHz clock"]
395    #[inline(always)]
396    pub fn is_sirc(&self) -> bool {
397        *self == Source::Sirc
398    }
399}
400#[doc = "Field `SOURCE` writer - Clock Source"]
401pub type SourceW<'a, REG> = crate::FieldWriter<'a, REG, 2, Source, crate::Safe>;
402impl<'a, REG> SourceW<'a, REG>
403where
404    REG: crate::Writable + crate::RegisterSpec,
405    REG::Ux: From<u8>,
406{
407    #[doc = "SOSC"]
408    #[inline(always)]
409    pub fn sosc(self) -> &'a mut crate::W<REG> {
410        self.variant(Source::Sosc)
411    }
412    #[doc = "FIRC 45 MHz clock. FIRC_SCLK_PERIPH_EN needs to be set to use FIRC 45 MHz clock."]
413    #[inline(always)]
414    pub fn firc(self) -> &'a mut crate::W<REG> {
415        self.variant(Source::Firc)
416    }
417    #[doc = "ROSC"]
418    #[inline(always)]
419    pub fn rsvd(self) -> &'a mut crate::W<REG> {
420        self.variant(Source::Rsvd)
421    }
422    #[doc = "SIRC 12 MHz clock"]
423    #[inline(always)]
424    pub fn sirc(self) -> &'a mut crate::W<REG> {
425        self.variant(Source::Sirc)
426    }
427}
428impl R {
429    #[doc = "Bits 0:3 - Bandwidth select R (resistor) value."]
430    #[inline(always)]
431    pub fn selr(&self) -> SelrR {
432        SelrR::new((self.bits & 0x0f) as u8)
433    }
434    #[doc = "Bits 4:9 - Bandwidth select I (interation) value."]
435    #[inline(always)]
436    pub fn seli(&self) -> SeliR {
437        SeliR::new(((self.bits >> 4) & 0x3f) as u8)
438    }
439    #[doc = "Bits 10:14 - Bandwidth select P (proportional) value."]
440    #[inline(always)]
441    pub fn selp(&self) -> SelpR {
442        SelpR::new(((self.bits >> 10) & 0x1f) as u8)
443    }
444    #[doc = "Bit 16 - Bypass of the divide-by-2 divider"]
445    #[inline(always)]
446    pub fn bypasspostdiv2(&self) -> Bypasspostdiv2R {
447        Bypasspostdiv2R::new(((self.bits >> 16) & 1) != 0)
448    }
449    #[doc = "Bit 17 - Up Limiter."]
450    #[inline(always)]
451    pub fn limupoff(&self) -> LimupoffR {
452        LimupoffR::new(((self.bits >> 17) & 1) != 0)
453    }
454    #[doc = "Bit 18 - Control of the bandwidth of the PLL."]
455    #[inline(always)]
456    pub fn banddirect(&self) -> BanddirectR {
457        BanddirectR::new(((self.bits >> 18) & 1) != 0)
458    }
459    #[doc = "Bit 19 - Bypass of the pre-divider."]
460    #[inline(always)]
461    pub fn bypassprediv(&self) -> BypasspredivR {
462        BypasspredivR::new(((self.bits >> 19) & 1) != 0)
463    }
464    #[doc = "Bit 20 - Bypass of the post-divider."]
465    #[inline(always)]
466    pub fn bypasspostdiv(&self) -> BypasspostdivR {
467        BypasspostdivR::new(((self.bits >> 20) & 1) != 0)
468    }
469    #[doc = "Bit 22 - Free Running Mode Enable"]
470    #[inline(always)]
471    pub fn frm(&self) -> FrmR {
472        FrmR::new(((self.bits >> 22) & 1) != 0)
473    }
474    #[doc = "Bits 25:26 - Clock Source"]
475    #[inline(always)]
476    pub fn source(&self) -> SourceR {
477        SourceR::new(((self.bits >> 25) & 3) as u8)
478    }
479}
480#[cfg(feature = "debug")]
481impl core::fmt::Debug for R {
482    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
483        f.debug_struct("SPLLCTRL")
484            .field("selr", &self.selr())
485            .field("seli", &self.seli())
486            .field("selp", &self.selp())
487            .field("bypasspostdiv2", &self.bypasspostdiv2())
488            .field("limupoff", &self.limupoff())
489            .field("banddirect", &self.banddirect())
490            .field("bypassprediv", &self.bypassprediv())
491            .field("bypasspostdiv", &self.bypasspostdiv())
492            .field("frm", &self.frm())
493            .field("source", &self.source())
494            .finish()
495    }
496}
497impl W {
498    #[doc = "Bits 0:3 - Bandwidth select R (resistor) value."]
499    #[inline(always)]
500    pub fn selr(&mut self) -> SelrW<'_, SpllctrlSpec> {
501        SelrW::new(self, 0)
502    }
503    #[doc = "Bits 4:9 - Bandwidth select I (interation) value."]
504    #[inline(always)]
505    pub fn seli(&mut self) -> SeliW<'_, SpllctrlSpec> {
506        SeliW::new(self, 4)
507    }
508    #[doc = "Bits 10:14 - Bandwidth select P (proportional) value."]
509    #[inline(always)]
510    pub fn selp(&mut self) -> SelpW<'_, SpllctrlSpec> {
511        SelpW::new(self, 10)
512    }
513    #[doc = "Bit 16 - Bypass of the divide-by-2 divider"]
514    #[inline(always)]
515    pub fn bypasspostdiv2(&mut self) -> Bypasspostdiv2W<'_, SpllctrlSpec> {
516        Bypasspostdiv2W::new(self, 16)
517    }
518    #[doc = "Bit 17 - Up Limiter."]
519    #[inline(always)]
520    pub fn limupoff(&mut self) -> LimupoffW<'_, SpllctrlSpec> {
521        LimupoffW::new(self, 17)
522    }
523    #[doc = "Bit 18 - Control of the bandwidth of the PLL."]
524    #[inline(always)]
525    pub fn banddirect(&mut self) -> BanddirectW<'_, SpllctrlSpec> {
526        BanddirectW::new(self, 18)
527    }
528    #[doc = "Bit 19 - Bypass of the pre-divider."]
529    #[inline(always)]
530    pub fn bypassprediv(&mut self) -> BypasspredivW<'_, SpllctrlSpec> {
531        BypasspredivW::new(self, 19)
532    }
533    #[doc = "Bit 20 - Bypass of the post-divider."]
534    #[inline(always)]
535    pub fn bypasspostdiv(&mut self) -> BypasspostdivW<'_, SpllctrlSpec> {
536        BypasspostdivW::new(self, 20)
537    }
538    #[doc = "Bit 22 - Free Running Mode Enable"]
539    #[inline(always)]
540    pub fn frm(&mut self) -> FrmW<'_, SpllctrlSpec> {
541        FrmW::new(self, 22)
542    }
543    #[doc = "Bits 25:26 - Clock Source"]
544    #[inline(always)]
545    pub fn source(&mut self) -> SourceW<'_, SpllctrlSpec> {
546        SourceW::new(self, 25)
547    }
548}
549#[doc = "SPLL Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
550pub struct SpllctrlSpec;
551impl crate::RegisterSpec for SpllctrlSpec {
552    type Ux = u32;
553}
554#[doc = "`read()` method returns [`spllctrl::R`](R) reader structure"]
555impl crate::Readable for SpllctrlSpec {}
556#[doc = "`write(|w| ..)` method takes [`spllctrl::W`](W) writer structure"]
557impl crate::Writable for SpllctrlSpec {
558    type Safety = crate::Unsafe;
559}
560#[doc = "`reset()` method sets SPLLCTRL to value 0"]
561impl crate::Resettable for SpllctrlSpec {}
mcxa_pac/scg0/spllctrl.rs

mcxa_pac/scg0/
spllctrl.rs
