mcxa_pac/scg0/
spllcsr.rs

1#[doc = "Register `SPLLCSR` reader"]
2pub type R = crate::R<SpllcsrSpec>;
3#[doc = "Register `SPLLCSR` writer"]
4pub type W = crate::W<SpllcsrSpec>;
5#[doc = "SPLL Power Enable\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Spllpwren {
9    #[doc = "0: SPLL clock is powered off"]
10    Disabled = 0,
11    #[doc = "1: SPLL clock is powered on"]
12    Enabled = 1,
13}
14impl From<Spllpwren> for bool {
15    #[inline(always)]
16    fn from(variant: Spllpwren) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `SPLLPWREN` reader - SPLL Power Enable"]
21pub type SpllpwrenR = crate::BitReader<Spllpwren>;
22impl SpllpwrenR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Spllpwren {
26        match self.bits {
27            false => Spllpwren::Disabled,
28            true => Spllpwren::Enabled,
29        }
30    }
31    #[doc = "SPLL clock is powered off"]
32    #[inline(always)]
33    pub fn is_disabled(&self) -> bool {
34        *self == Spllpwren::Disabled
35    }
36    #[doc = "SPLL clock is powered on"]
37    #[inline(always)]
38    pub fn is_enabled(&self) -> bool {
39        *self == Spllpwren::Enabled
40    }
41}
42#[doc = "Field `SPLLPWREN` writer - SPLL Power Enable"]
43pub type SpllpwrenW<'a, REG> = crate::BitWriter<'a, REG, Spllpwren>;
44impl<'a, REG> SpllpwrenW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "SPLL clock is powered off"]
49    #[inline(always)]
50    pub fn disabled(self) -> &'a mut crate::W<REG> {
51        self.variant(Spllpwren::Disabled)
52    }
53    #[doc = "SPLL clock is powered on"]
54    #[inline(always)]
55    pub fn enabled(self) -> &'a mut crate::W<REG> {
56        self.variant(Spllpwren::Enabled)
57    }
58}
59#[doc = "SPLL Clock Enable\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Spllclken {
63    #[doc = "0: SPLL clock is disabled"]
64    Disabled = 0,
65    #[doc = "1: SPLL clock is enabled"]
66    Enabled = 1,
67}
68impl From<Spllclken> for bool {
69    #[inline(always)]
70    fn from(variant: Spllclken) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `SPLLCLKEN` reader - SPLL Clock Enable"]
75pub type SpllclkenR = crate::BitReader<Spllclken>;
76impl SpllclkenR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Spllclken {
80        match self.bits {
81            false => Spllclken::Disabled,
82            true => Spllclken::Enabled,
83        }
84    }
85    #[doc = "SPLL clock is disabled"]
86    #[inline(always)]
87    pub fn is_disabled(&self) -> bool {
88        *self == Spllclken::Disabled
89    }
90    #[doc = "SPLL clock is enabled"]
91    #[inline(always)]
92    pub fn is_enabled(&self) -> bool {
93        *self == Spllclken::Enabled
94    }
95}
96#[doc = "Field `SPLLCLKEN` writer - SPLL Clock Enable"]
97pub type SpllclkenW<'a, REG> = crate::BitWriter<'a, REG, Spllclken>;
98impl<'a, REG> SpllclkenW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "SPLL clock is disabled"]
103    #[inline(always)]
104    pub fn disabled(self) -> &'a mut crate::W<REG> {
105        self.variant(Spllclken::Disabled)
106    }
107    #[doc = "SPLL clock is enabled"]
108    #[inline(always)]
109    pub fn enabled(self) -> &'a mut crate::W<REG> {
110        self.variant(Spllclken::Enabled)
111    }
112}
113#[doc = "SPLL Stop Enable\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Spllsten {
117    #[doc = "0: SPLL is disabled in Deep Sleep mode"]
118    DisabledInStop = 0,
119    #[doc = "1: SPLL is enabled in Deep Sleep mode"]
120    EnabledInStop = 1,
121}
122impl From<Spllsten> for bool {
123    #[inline(always)]
124    fn from(variant: Spllsten) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `SPLLSTEN` reader - SPLL Stop Enable"]
129pub type SpllstenR = crate::BitReader<Spllsten>;
130impl SpllstenR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Spllsten {
134        match self.bits {
135            false => Spllsten::DisabledInStop,
136            true => Spllsten::EnabledInStop,
137        }
138    }
139    #[doc = "SPLL is disabled in Deep Sleep mode"]
140    #[inline(always)]
141    pub fn is_disabled_in_stop(&self) -> bool {
142        *self == Spllsten::DisabledInStop
143    }
144    #[doc = "SPLL is enabled in Deep Sleep mode"]
145    #[inline(always)]
146    pub fn is_enabled_in_stop(&self) -> bool {
147        *self == Spllsten::EnabledInStop
148    }
149}
150#[doc = "Field `SPLLSTEN` writer - SPLL Stop Enable"]
151pub type SpllstenW<'a, REG> = crate::BitWriter<'a, REG, Spllsten>;
152impl<'a, REG> SpllstenW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "SPLL is disabled in Deep Sleep mode"]
157    #[inline(always)]
158    pub fn disabled_in_stop(self) -> &'a mut crate::W<REG> {
159        self.variant(Spllsten::DisabledInStop)
160    }
161    #[doc = "SPLL is enabled in Deep Sleep mode"]
162    #[inline(always)]
163    pub fn enabled_in_stop(self) -> &'a mut crate::W<REG> {
164        self.variant(Spllsten::EnabledInStop)
165    }
166}
167#[doc = "Free running mode clock stable\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum FrmClockstable {
171    #[doc = "0: Free running mode clock stable is disabled"]
172    Disabled = 0,
173    #[doc = "1: Free running mode clock stable is enabled"]
174    Enabled = 1,
175}
176impl From<FrmClockstable> for bool {
177    #[inline(always)]
178    fn from(variant: FrmClockstable) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `FRM_CLOCKSTABLE` reader - Free running mode clock stable"]
183pub type FrmClockstableR = crate::BitReader<FrmClockstable>;
184impl FrmClockstableR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> FrmClockstable {
188        match self.bits {
189            false => FrmClockstable::Disabled,
190            true => FrmClockstable::Enabled,
191        }
192    }
193    #[doc = "Free running mode clock stable is disabled"]
194    #[inline(always)]
195    pub fn is_disabled(&self) -> bool {
196        *self == FrmClockstable::Disabled
197    }
198    #[doc = "Free running mode clock stable is enabled"]
199    #[inline(always)]
200    pub fn is_enabled(&self) -> bool {
201        *self == FrmClockstable::Enabled
202    }
203}
204#[doc = "Field `FRM_CLOCKSTABLE` writer - Free running mode clock stable"]
205pub type FrmClockstableW<'a, REG> = crate::BitWriter<'a, REG, FrmClockstable>;
206impl<'a, REG> FrmClockstableW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Free running mode clock stable is disabled"]
211    #[inline(always)]
212    pub fn disabled(self) -> &'a mut crate::W<REG> {
213        self.variant(FrmClockstable::Disabled)
214    }
215    #[doc = "Free running mode clock stable is enabled"]
216    #[inline(always)]
217    pub fn enabled(self) -> &'a mut crate::W<REG> {
218        self.variant(FrmClockstable::Enabled)
219    }
220}
221#[doc = "SPLL Clock Monitor\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum Spllcm {
225    #[doc = "0: SPLL Clock Monitor is disabled"]
226    Disabled = 0,
227    #[doc = "1: SPLL Clock Monitor is enabled"]
228    Enabled = 1,
229}
230impl From<Spllcm> for bool {
231    #[inline(always)]
232    fn from(variant: Spllcm) -> Self {
233        variant as u8 != 0
234    }
235}
236#[doc = "Field `SPLLCM` reader - SPLL Clock Monitor"]
237pub type SpllcmR = crate::BitReader<Spllcm>;
238impl SpllcmR {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> Spllcm {
242        match self.bits {
243            false => Spllcm::Disabled,
244            true => Spllcm::Enabled,
245        }
246    }
247    #[doc = "SPLL Clock Monitor is disabled"]
248    #[inline(always)]
249    pub fn is_disabled(&self) -> bool {
250        *self == Spllcm::Disabled
251    }
252    #[doc = "SPLL Clock Monitor is enabled"]
253    #[inline(always)]
254    pub fn is_enabled(&self) -> bool {
255        *self == Spllcm::Enabled
256    }
257}
258#[doc = "Field `SPLLCM` writer - SPLL Clock Monitor"]
259pub type SpllcmW<'a, REG> = crate::BitWriter<'a, REG, Spllcm>;
260impl<'a, REG> SpllcmW<'a, REG>
261where
262    REG: crate::Writable + crate::RegisterSpec,
263{
264    #[doc = "SPLL Clock Monitor is disabled"]
265    #[inline(always)]
266    pub fn disabled(self) -> &'a mut crate::W<REG> {
267        self.variant(Spllcm::Disabled)
268    }
269    #[doc = "SPLL Clock Monitor is enabled"]
270    #[inline(always)]
271    pub fn enabled(self) -> &'a mut crate::W<REG> {
272        self.variant(Spllcm::Enabled)
273    }
274}
275#[doc = "SPLL Clock Monitor Reset Enable\n\nValue on reset: 0"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum Spllcmre {
279    #[doc = "0: Clock monitor generates an interrupt when an error is detected"]
280    GenerateInterrupt = 0,
281    #[doc = "1: Clock monitor generates a reset when an error is detected"]
282    GenerateReset = 1,
283}
284impl From<Spllcmre> for bool {
285    #[inline(always)]
286    fn from(variant: Spllcmre) -> Self {
287        variant as u8 != 0
288    }
289}
290#[doc = "Field `SPLLCMRE` reader - SPLL Clock Monitor Reset Enable"]
291pub type SpllcmreR = crate::BitReader<Spllcmre>;
292impl SpllcmreR {
293    #[doc = "Get enumerated values variant"]
294    #[inline(always)]
295    pub const fn variant(&self) -> Spllcmre {
296        match self.bits {
297            false => Spllcmre::GenerateInterrupt,
298            true => Spllcmre::GenerateReset,
299        }
300    }
301    #[doc = "Clock monitor generates an interrupt when an error is detected"]
302    #[inline(always)]
303    pub fn is_generate_interrupt(&self) -> bool {
304        *self == Spllcmre::GenerateInterrupt
305    }
306    #[doc = "Clock monitor generates a reset when an error is detected"]
307    #[inline(always)]
308    pub fn is_generate_reset(&self) -> bool {
309        *self == Spllcmre::GenerateReset
310    }
311}
312#[doc = "Field `SPLLCMRE` writer - SPLL Clock Monitor Reset Enable"]
313pub type SpllcmreW<'a, REG> = crate::BitWriter<'a, REG, Spllcmre>;
314impl<'a, REG> SpllcmreW<'a, REG>
315where
316    REG: crate::Writable + crate::RegisterSpec,
317{
318    #[doc = "Clock monitor generates an interrupt when an error is detected"]
319    #[inline(always)]
320    pub fn generate_interrupt(self) -> &'a mut crate::W<REG> {
321        self.variant(Spllcmre::GenerateInterrupt)
322    }
323    #[doc = "Clock monitor generates a reset when an error is detected"]
324    #[inline(always)]
325    pub fn generate_reset(self) -> &'a mut crate::W<REG> {
326        self.variant(Spllcmre::GenerateReset)
327    }
328}
329#[doc = "Lock Register\n\nValue on reset: 0"]
330#[cfg_attr(feature = "defmt", derive(defmt::Format))]
331#[derive(Clone, Copy, Debug, PartialEq, Eq)]
332pub enum Lk {
333    #[doc = "0: Control Status Register can be written"]
334    WriteEnabled = 0,
335    #[doc = "1: Control Status Register cannot be written"]
336    WriteDisabled = 1,
337}
338impl From<Lk> for bool {
339    #[inline(always)]
340    fn from(variant: Lk) -> Self {
341        variant as u8 != 0
342    }
343}
344#[doc = "Field `LK` reader - Lock Register"]
345pub type LkR = crate::BitReader<Lk>;
346impl LkR {
347    #[doc = "Get enumerated values variant"]
348    #[inline(always)]
349    pub const fn variant(&self) -> Lk {
350        match self.bits {
351            false => Lk::WriteEnabled,
352            true => Lk::WriteDisabled,
353        }
354    }
355    #[doc = "Control Status Register can be written"]
356    #[inline(always)]
357    pub fn is_write_enabled(&self) -> bool {
358        *self == Lk::WriteEnabled
359    }
360    #[doc = "Control Status Register cannot be written"]
361    #[inline(always)]
362    pub fn is_write_disabled(&self) -> bool {
363        *self == Lk::WriteDisabled
364    }
365}
366#[doc = "Field `LK` writer - Lock Register"]
367pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>;
368impl<'a, REG> LkW<'a, REG>
369where
370    REG: crate::Writable + crate::RegisterSpec,
371{
372    #[doc = "Control Status Register can be written"]
373    #[inline(always)]
374    pub fn write_enabled(self) -> &'a mut crate::W<REG> {
375        self.variant(Lk::WriteEnabled)
376    }
377    #[doc = "Control Status Register cannot be written"]
378    #[inline(always)]
379    pub fn write_disabled(self) -> &'a mut crate::W<REG> {
380        self.variant(Lk::WriteDisabled)
381    }
382}
383#[doc = "SPLL LOCK\n\nValue on reset: 0"]
384#[cfg_attr(feature = "defmt", derive(defmt::Format))]
385#[derive(Clone, Copy, Debug, PartialEq, Eq)]
386pub enum SpllLock {
387    #[doc = "0: SPLL is not powered on or not locked"]
388    DisabledOrNotValid = 0,
389    #[doc = "1: SPLL is locked"]
390    EnabledAndValid = 1,
391}
392impl From<SpllLock> for bool {
393    #[inline(always)]
394    fn from(variant: SpllLock) -> Self {
395        variant as u8 != 0
396    }
397}
398#[doc = "Field `SPLL_LOCK` reader - SPLL LOCK"]
399pub type SpllLockR = crate::BitReader<SpllLock>;
400impl SpllLockR {
401    #[doc = "Get enumerated values variant"]
402    #[inline(always)]
403    pub const fn variant(&self) -> SpllLock {
404        match self.bits {
405            false => SpllLock::DisabledOrNotValid,
406            true => SpllLock::EnabledAndValid,
407        }
408    }
409    #[doc = "SPLL is not powered on or not locked"]
410    #[inline(always)]
411    pub fn is_disabled_or_not_valid(&self) -> bool {
412        *self == SpllLock::DisabledOrNotValid
413    }
414    #[doc = "SPLL is locked"]
415    #[inline(always)]
416    pub fn is_enabled_and_valid(&self) -> bool {
417        *self == SpllLock::EnabledAndValid
418    }
419}
420#[doc = "SPLL Selected\n\nValue on reset: 0"]
421#[cfg_attr(feature = "defmt", derive(defmt::Format))]
422#[derive(Clone, Copy, Debug, PartialEq, Eq)]
423pub enum Spllsel {
424    #[doc = "0: SPLL is not the system clock source"]
425    NotSpll = 0,
426    #[doc = "1: SPLL is the system clock source"]
427    Spll = 1,
428}
429impl From<Spllsel> for bool {
430    #[inline(always)]
431    fn from(variant: Spllsel) -> Self {
432        variant as u8 != 0
433    }
434}
435#[doc = "Field `SPLLSEL` reader - SPLL Selected"]
436pub type SpllselR = crate::BitReader<Spllsel>;
437impl SpllselR {
438    #[doc = "Get enumerated values variant"]
439    #[inline(always)]
440    pub const fn variant(&self) -> Spllsel {
441        match self.bits {
442            false => Spllsel::NotSpll,
443            true => Spllsel::Spll,
444        }
445    }
446    #[doc = "SPLL is not the system clock source"]
447    #[inline(always)]
448    pub fn is_not_spll(&self) -> bool {
449        *self == Spllsel::NotSpll
450    }
451    #[doc = "SPLL is the system clock source"]
452    #[inline(always)]
453    pub fn is_spll(&self) -> bool {
454        *self == Spllsel::Spll
455    }
456}
457#[doc = "SPLL Clock Error\n\nValue on reset: 0"]
458#[cfg_attr(feature = "defmt", derive(defmt::Format))]
459#[derive(Clone, Copy, Debug, PartialEq, Eq)]
460pub enum Spllerr {
461    #[doc = "0: SPLL Clock Monitor is disabled or has not detected an error"]
462    DisabledOrNoError = 0,
463    #[doc = "1: SPLL Clock Monitor is enabled and detected an error"]
464    EnabledAndError = 1,
465}
466impl From<Spllerr> for bool {
467    #[inline(always)]
468    fn from(variant: Spllerr) -> Self {
469        variant as u8 != 0
470    }
471}
472#[doc = "Field `SPLLERR` reader - SPLL Clock Error"]
473pub type SpllerrR = crate::BitReader<Spllerr>;
474impl SpllerrR {
475    #[doc = "Get enumerated values variant"]
476    #[inline(always)]
477    pub const fn variant(&self) -> Spllerr {
478        match self.bits {
479            false => Spllerr::DisabledOrNoError,
480            true => Spllerr::EnabledAndError,
481        }
482    }
483    #[doc = "SPLL Clock Monitor is disabled or has not detected an error"]
484    #[inline(always)]
485    pub fn is_disabled_or_no_error(&self) -> bool {
486        *self == Spllerr::DisabledOrNoError
487    }
488    #[doc = "SPLL Clock Monitor is enabled and detected an error"]
489    #[inline(always)]
490    pub fn is_enabled_and_error(&self) -> bool {
491        *self == Spllerr::EnabledAndError
492    }
493}
494#[doc = "Field `SPLLERR` writer - SPLL Clock Error"]
495pub type SpllerrW<'a, REG> = crate::BitWriter1C<'a, REG, Spllerr>;
496impl<'a, REG> SpllerrW<'a, REG>
497where
498    REG: crate::Writable + crate::RegisterSpec,
499{
500    #[doc = "SPLL Clock Monitor is disabled or has not detected an error"]
501    #[inline(always)]
502    pub fn disabled_or_no_error(self) -> &'a mut crate::W<REG> {
503        self.variant(Spllerr::DisabledOrNoError)
504    }
505    #[doc = "SPLL Clock Monitor is enabled and detected an error"]
506    #[inline(always)]
507    pub fn enabled_and_error(self) -> &'a mut crate::W<REG> {
508        self.variant(Spllerr::EnabledAndError)
509    }
510}
511#[doc = "SPLL LOCK Interrupt Enable\n\nValue on reset: 0"]
512#[cfg_attr(feature = "defmt", derive(defmt::Format))]
513#[derive(Clone, Copy, Debug, PartialEq, Eq)]
514pub enum SpllLockIe {
515    #[doc = "0: SPLL_LOCK interrupt is not enabled"]
516    NotSpll = 0,
517    #[doc = "1: SPLL_LOCK interrupt is enabled"]
518    Spll = 1,
519}
520impl From<SpllLockIe> for bool {
521    #[inline(always)]
522    fn from(variant: SpllLockIe) -> Self {
523        variant as u8 != 0
524    }
525}
526#[doc = "Field `SPLL_LOCK_IE` reader - SPLL LOCK Interrupt Enable"]
527pub type SpllLockIeR = crate::BitReader<SpllLockIe>;
528impl SpllLockIeR {
529    #[doc = "Get enumerated values variant"]
530    #[inline(always)]
531    pub const fn variant(&self) -> SpllLockIe {
532        match self.bits {
533            false => SpllLockIe::NotSpll,
534            true => SpllLockIe::Spll,
535        }
536    }
537    #[doc = "SPLL_LOCK interrupt is not enabled"]
538    #[inline(always)]
539    pub fn is_not_spll(&self) -> bool {
540        *self == SpllLockIe::NotSpll
541    }
542    #[doc = "SPLL_LOCK interrupt is enabled"]
543    #[inline(always)]
544    pub fn is_spll(&self) -> bool {
545        *self == SpllLockIe::Spll
546    }
547}
548#[doc = "Field `SPLL_LOCK_IE` writer - SPLL LOCK Interrupt Enable"]
549pub type SpllLockIeW<'a, REG> = crate::BitWriter<'a, REG, SpllLockIe>;
550impl<'a, REG> SpllLockIeW<'a, REG>
551where
552    REG: crate::Writable + crate::RegisterSpec,
553{
554    #[doc = "SPLL_LOCK interrupt is not enabled"]
555    #[inline(always)]
556    pub fn not_spll(self) -> &'a mut crate::W<REG> {
557        self.variant(SpllLockIe::NotSpll)
558    }
559    #[doc = "SPLL_LOCK interrupt is enabled"]
560    #[inline(always)]
561    pub fn spll(self) -> &'a mut crate::W<REG> {
562        self.variant(SpllLockIe::Spll)
563    }
564}
565impl R {
566    #[doc = "Bit 0 - SPLL Power Enable"]
567    #[inline(always)]
568    pub fn spllpwren(&self) -> SpllpwrenR {
569        SpllpwrenR::new((self.bits & 1) != 0)
570    }
571    #[doc = "Bit 1 - SPLL Clock Enable"]
572    #[inline(always)]
573    pub fn spllclken(&self) -> SpllclkenR {
574        SpllclkenR::new(((self.bits >> 1) & 1) != 0)
575    }
576    #[doc = "Bit 2 - SPLL Stop Enable"]
577    #[inline(always)]
578    pub fn spllsten(&self) -> SpllstenR {
579        SpllstenR::new(((self.bits >> 2) & 1) != 0)
580    }
581    #[doc = "Bit 3 - Free running mode clock stable"]
582    #[inline(always)]
583    pub fn frm_clockstable(&self) -> FrmClockstableR {
584        FrmClockstableR::new(((self.bits >> 3) & 1) != 0)
585    }
586    #[doc = "Bit 16 - SPLL Clock Monitor"]
587    #[inline(always)]
588    pub fn spllcm(&self) -> SpllcmR {
589        SpllcmR::new(((self.bits >> 16) & 1) != 0)
590    }
591    #[doc = "Bit 17 - SPLL Clock Monitor Reset Enable"]
592    #[inline(always)]
593    pub fn spllcmre(&self) -> SpllcmreR {
594        SpllcmreR::new(((self.bits >> 17) & 1) != 0)
595    }
596    #[doc = "Bit 23 - Lock Register"]
597    #[inline(always)]
598    pub fn lk(&self) -> LkR {
599        LkR::new(((self.bits >> 23) & 1) != 0)
600    }
601    #[doc = "Bit 24 - SPLL LOCK"]
602    #[inline(always)]
603    pub fn spll_lock(&self) -> SpllLockR {
604        SpllLockR::new(((self.bits >> 24) & 1) != 0)
605    }
606    #[doc = "Bit 25 - SPLL Selected"]
607    #[inline(always)]
608    pub fn spllsel(&self) -> SpllselR {
609        SpllselR::new(((self.bits >> 25) & 1) != 0)
610    }
611    #[doc = "Bit 26 - SPLL Clock Error"]
612    #[inline(always)]
613    pub fn spllerr(&self) -> SpllerrR {
614        SpllerrR::new(((self.bits >> 26) & 1) != 0)
615    }
616    #[doc = "Bit 30 - SPLL LOCK Interrupt Enable"]
617    #[inline(always)]
618    pub fn spll_lock_ie(&self) -> SpllLockIeR {
619        SpllLockIeR::new(((self.bits >> 30) & 1) != 0)
620    }
621}
622#[cfg(feature = "debug")]
623impl core::fmt::Debug for R {
624    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
625        f.debug_struct("SPLLCSR")
626            .field("spllpwren", &self.spllpwren())
627            .field("spllclken", &self.spllclken())
628            .field("spllsten", &self.spllsten())
629            .field("frm_clockstable", &self.frm_clockstable())
630            .field("spllcm", &self.spllcm())
631            .field("spllcmre", &self.spllcmre())
632            .field("lk", &self.lk())
633            .field("spll_lock", &self.spll_lock())
634            .field("spllsel", &self.spllsel())
635            .field("spllerr", &self.spllerr())
636            .field("spll_lock_ie", &self.spll_lock_ie())
637            .finish()
638    }
639}
640impl W {
641    #[doc = "Bit 0 - SPLL Power Enable"]
642    #[inline(always)]
643    pub fn spllpwren(&mut self) -> SpllpwrenW<'_, SpllcsrSpec> {
644        SpllpwrenW::new(self, 0)
645    }
646    #[doc = "Bit 1 - SPLL Clock Enable"]
647    #[inline(always)]
648    pub fn spllclken(&mut self) -> SpllclkenW<'_, SpllcsrSpec> {
649        SpllclkenW::new(self, 1)
650    }
651    #[doc = "Bit 2 - SPLL Stop Enable"]
652    #[inline(always)]
653    pub fn spllsten(&mut self) -> SpllstenW<'_, SpllcsrSpec> {
654        SpllstenW::new(self, 2)
655    }
656    #[doc = "Bit 3 - Free running mode clock stable"]
657    #[inline(always)]
658    pub fn frm_clockstable(&mut self) -> FrmClockstableW<'_, SpllcsrSpec> {
659        FrmClockstableW::new(self, 3)
660    }
661    #[doc = "Bit 16 - SPLL Clock Monitor"]
662    #[inline(always)]
663    pub fn spllcm(&mut self) -> SpllcmW<'_, SpllcsrSpec> {
664        SpllcmW::new(self, 16)
665    }
666    #[doc = "Bit 17 - SPLL Clock Monitor Reset Enable"]
667    #[inline(always)]
668    pub fn spllcmre(&mut self) -> SpllcmreW<'_, SpllcsrSpec> {
669        SpllcmreW::new(self, 17)
670    }
671    #[doc = "Bit 23 - Lock Register"]
672    #[inline(always)]
673    pub fn lk(&mut self) -> LkW<'_, SpllcsrSpec> {
674        LkW::new(self, 23)
675    }
676    #[doc = "Bit 26 - SPLL Clock Error"]
677    #[inline(always)]
678    pub fn spllerr(&mut self) -> SpllerrW<'_, SpllcsrSpec> {
679        SpllerrW::new(self, 26)
680    }
681    #[doc = "Bit 30 - SPLL LOCK Interrupt Enable"]
682    #[inline(always)]
683    pub fn spll_lock_ie(&mut self) -> SpllLockIeW<'_, SpllcsrSpec> {
684        SpllLockIeW::new(self, 30)
685    }
686}
687#[doc = "SPLL Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
688pub struct SpllcsrSpec;
689impl crate::RegisterSpec for SpllcsrSpec {
690    type Ux = u32;
691}
692#[doc = "`read()` method returns [`spllcsr::R`](R) reader structure"]
693impl crate::Readable for SpllcsrSpec {}
694#[doc = "`write(|w| ..)` method takes [`spllcsr::W`](W) writer structure"]
695impl crate::Writable for SpllcsrSpec {
696    type Safety = crate::Unsafe;
697    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000;
698}
699#[doc = "`reset()` method sets SPLLCSR to value 0"]
700impl crate::Resettable for SpllcsrSpec {}
mcxa_pac/scg0/spllcsr.rs

mcxa_pac/scg0/
spllcsr.rs
