mcxa_pac/rtc0/
tcr.rs

1#[doc = "Register `TCR` reader"]
2pub type R = crate::R<TcrSpec>;
3#[doc = "Register `TCR` writer"]
4pub type W = crate::W<TcrSpec>;
5#[doc = "Time Compensation Register\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Tcr {
10    #[doc = "0: Time Prescaler Register overflows every 32768 clock cycles."]
11    Tcr0 = 0,
12    #[doc = "1: Time Prescaler Register overflows every 32767 clock cycles."]
13    Tcr1 = 1,
14    #[doc = "126: Time Prescaler Register overflows every 32642 clock cycles."]
15    Tcr126 = 126,
16    #[doc = "127: Time Prescaler Register overflows every 32641 clock cycles."]
17    Tcr127 = 127,
18    #[doc = "128: Time Prescaler Register overflows every 32896 clock cycles."]
19    Tcr128 = 128,
20    #[doc = "129: Time Prescaler Register overflows every 32895 clock cycles."]
21    Tcr129 = 129,
22    #[doc = "255: Time Prescaler Register overflows every 32769 clock cycles."]
23    Tcr255 = 255,
24}
25impl From<Tcr> for u8 {
26    #[inline(always)]
27    fn from(variant: Tcr) -> Self {
28        variant as _
29    }
30}
31impl crate::FieldSpec for Tcr {
32    type Ux = u8;
33}
34impl crate::IsEnum for Tcr {}
35#[doc = "Field `TCR` reader - Time Compensation Register"]
36pub type TcrR = crate::FieldReader<Tcr>;
37impl TcrR {
38    #[doc = "Get enumerated values variant"]
39    #[inline(always)]
40    pub const fn variant(&self) -> Option<Tcr> {
41        match self.bits {
42            0 => Some(Tcr::Tcr0),
43            1 => Some(Tcr::Tcr1),
44            126 => Some(Tcr::Tcr126),
45            127 => Some(Tcr::Tcr127),
46            128 => Some(Tcr::Tcr128),
47            129 => Some(Tcr::Tcr129),
48            255 => Some(Tcr::Tcr255),
49            _ => None,
50        }
51    }
52    #[doc = "Time Prescaler Register overflows every 32768 clock cycles."]
53    #[inline(always)]
54    pub fn is_tcr_0(&self) -> bool {
55        *self == Tcr::Tcr0
56    }
57    #[doc = "Time Prescaler Register overflows every 32767 clock cycles."]
58    #[inline(always)]
59    pub fn is_tcr_1(&self) -> bool {
60        *self == Tcr::Tcr1
61    }
62    #[doc = "Time Prescaler Register overflows every 32642 clock cycles."]
63    #[inline(always)]
64    pub fn is_tcr_126(&self) -> bool {
65        *self == Tcr::Tcr126
66    }
67    #[doc = "Time Prescaler Register overflows every 32641 clock cycles."]
68    #[inline(always)]
69    pub fn is_tcr_127(&self) -> bool {
70        *self == Tcr::Tcr127
71    }
72    #[doc = "Time Prescaler Register overflows every 32896 clock cycles."]
73    #[inline(always)]
74    pub fn is_tcr_128(&self) -> bool {
75        *self == Tcr::Tcr128
76    }
77    #[doc = "Time Prescaler Register overflows every 32895 clock cycles."]
78    #[inline(always)]
79    pub fn is_tcr_129(&self) -> bool {
80        *self == Tcr::Tcr129
81    }
82    #[doc = "Time Prescaler Register overflows every 32769 clock cycles."]
83    #[inline(always)]
84    pub fn is_tcr_255(&self) -> bool {
85        *self == Tcr::Tcr255
86    }
87}
88#[doc = "Field `TCR` writer - Time Compensation Register"]
89pub type TcrW<'a, REG> = crate::FieldWriter<'a, REG, 8, Tcr>;
90impl<'a, REG> TcrW<'a, REG>
91where
92    REG: crate::Writable + crate::RegisterSpec,
93    REG::Ux: From<u8>,
94{
95    #[doc = "Time Prescaler Register overflows every 32768 clock cycles."]
96    #[inline(always)]
97    pub fn tcr_0(self) -> &'a mut crate::W<REG> {
98        self.variant(Tcr::Tcr0)
99    }
100    #[doc = "Time Prescaler Register overflows every 32767 clock cycles."]
101    #[inline(always)]
102    pub fn tcr_1(self) -> &'a mut crate::W<REG> {
103        self.variant(Tcr::Tcr1)
104    }
105    #[doc = "Time Prescaler Register overflows every 32642 clock cycles."]
106    #[inline(always)]
107    pub fn tcr_126(self) -> &'a mut crate::W<REG> {
108        self.variant(Tcr::Tcr126)
109    }
110    #[doc = "Time Prescaler Register overflows every 32641 clock cycles."]
111    #[inline(always)]
112    pub fn tcr_127(self) -> &'a mut crate::W<REG> {
113        self.variant(Tcr::Tcr127)
114    }
115    #[doc = "Time Prescaler Register overflows every 32896 clock cycles."]
116    #[inline(always)]
117    pub fn tcr_128(self) -> &'a mut crate::W<REG> {
118        self.variant(Tcr::Tcr128)
119    }
120    #[doc = "Time Prescaler Register overflows every 32895 clock cycles."]
121    #[inline(always)]
122    pub fn tcr_129(self) -> &'a mut crate::W<REG> {
123        self.variant(Tcr::Tcr129)
124    }
125    #[doc = "Time Prescaler Register overflows every 32769 clock cycles."]
126    #[inline(always)]
127    pub fn tcr_255(self) -> &'a mut crate::W<REG> {
128        self.variant(Tcr::Tcr255)
129    }
130}
131#[doc = "Field `CIR` reader - Compensation Interval Register"]
132pub type CirR = crate::FieldReader;
133#[doc = "Field `CIR` writer - Compensation Interval Register"]
134pub type CirW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
135#[doc = "Field `TCV` reader - Time Compensation Value"]
136pub type TcvR = crate::FieldReader;
137#[doc = "Field `CIC` reader - Compensation Interval Counter"]
138pub type CicR = crate::FieldReader;
139impl R {
140    #[doc = "Bits 0:7 - Time Compensation Register"]
141    #[inline(always)]
142    pub fn tcr(&self) -> TcrR {
143        TcrR::new((self.bits & 0xff) as u8)
144    }
145    #[doc = "Bits 8:15 - Compensation Interval Register"]
146    #[inline(always)]
147    pub fn cir(&self) -> CirR {
148        CirR::new(((self.bits >> 8) & 0xff) as u8)
149    }
150    #[doc = "Bits 16:23 - Time Compensation Value"]
151    #[inline(always)]
152    pub fn tcv(&self) -> TcvR {
153        TcvR::new(((self.bits >> 16) & 0xff) as u8)
154    }
155    #[doc = "Bits 24:31 - Compensation Interval Counter"]
156    #[inline(always)]
157    pub fn cic(&self) -> CicR {
158        CicR::new(((self.bits >> 24) & 0xff) as u8)
159    }
160}
161#[cfg(feature = "debug")]
162impl core::fmt::Debug for R {
163    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
164        f.debug_struct("TCR")
165            .field("tcr", &self.tcr())
166            .field("cir", &self.cir())
167            .field("tcv", &self.tcv())
168            .field("cic", &self.cic())
169            .finish()
170    }
171}
172impl W {
173    #[doc = "Bits 0:7 - Time Compensation Register"]
174    #[inline(always)]
175    pub fn tcr(&mut self) -> TcrW<'_, TcrSpec> {
176        TcrW::new(self, 0)
177    }
178    #[doc = "Bits 8:15 - Compensation Interval Register"]
179    #[inline(always)]
180    pub fn cir(&mut self) -> CirW<'_, TcrSpec> {
181        CirW::new(self, 8)
182    }
183}
184#[doc = "RTC Time Compensation\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
185pub struct TcrSpec;
186impl crate::RegisterSpec for TcrSpec {
187    type Ux = u32;
188}
189#[doc = "`read()` method returns [`tcr::R`](R) reader structure"]
190impl crate::Readable for TcrSpec {}
191#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"]
192impl crate::Writable for TcrSpec {
193    type Safety = crate::Unsafe;
194}
195#[doc = "`reset()` method sets TCR to value 0"]
196impl crate::Resettable for TcrSpec {}
mcxa_pac/rtc0/tcr.rs

mcxa_pac/rtc0/
tcr.rs
