mcxa_pac/lpuart0/
data.rs

1#[doc = "Register `DATA` reader"]
2pub type R = crate::R<DataSpec>;
3#[doc = "Register `DATA` writer"]
4pub type W = crate::W<DataSpec>;
5#[doc = "Field `R0T0` reader - Read receive FIFO bit 0 or write transmit FIFO bit 0"]
6pub type R0t0R = crate::BitReader;
7#[doc = "Field `R0T0` writer - Read receive FIFO bit 0 or write transmit FIFO bit 0"]
8pub type R0t0W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `R1T1` reader - Read receive FIFO bit 1 or write transmit FIFO bit 1"]
10pub type R1t1R = crate::BitReader;
11#[doc = "Field `R1T1` writer - Read receive FIFO bit 1 or write transmit FIFO bit 1"]
12pub type R1t1W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `R2T2` reader - Read receive FIFO bit 2 or write transmit FIFO bit 2"]
14pub type R2t2R = crate::BitReader;
15#[doc = "Field `R2T2` writer - Read receive FIFO bit 2 or write transmit FIFO bit 2"]
16pub type R2t2W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `R3T3` reader - Read receive FIFO bit 3 or write transmit FIFO bit 3"]
18pub type R3t3R = crate::BitReader;
19#[doc = "Field `R3T3` writer - Read receive FIFO bit 3 or write transmit FIFO bit 3"]
20pub type R3t3W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `R4T4` reader - Read receive FIFO bit 4 or write transmit FIFO bit 4"]
22pub type R4t4R = crate::BitReader;
23#[doc = "Field `R4T4` writer - Read receive FIFO bit 4 or write transmit FIFO bit 4"]
24pub type R4t4W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `R5T5` reader - Read receive FIFO bit 5 or write transmit FIFO bit 5"]
26pub type R5t5R = crate::BitReader;
27#[doc = "Field `R5T5` writer - Read receive FIFO bit 5 or write transmit FIFO bit 5"]
28pub type R5t5W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `R6T6` reader - Read receive FIFO bit 6 or write transmit FIFO bit 6"]
30pub type R6t6R = crate::BitReader;
31#[doc = "Field `R6T6` writer - Read receive FIFO bit 6 or write transmit FIFO bit 6"]
32pub type R6t6W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `R7T7` reader - Read receive FIFO bit 7 or write transmit FIFO bit 7"]
34pub type R7t7R = crate::BitReader;
35#[doc = "Field `R7T7` writer - Read receive FIFO bit 7 or write transmit FIFO bit 7"]
36pub type R7t7W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `R8T8` reader - Read receive FIFO bit 8 or write transmit FIFO bit 8"]
38pub type R8t8R = crate::BitReader;
39#[doc = "Field `R8T8` writer - Read receive FIFO bit 8 or write transmit FIFO bit 8"]
40pub type R8t8W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `R9T9` reader - Read receive FIFO bit 9 or write transmit FIFO bit 9"]
42pub type R9t9R = crate::BitReader;
43#[doc = "Field `R9T9` writer - Read receive FIFO bit 9 or write transmit FIFO bit 9"]
44pub type R9t9W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "LIN Break\n\nValue on reset: 0"]
46#[cfg_attr(feature = "defmt", derive(defmt::Format))]
47#[derive(Clone, Copy, Debug, PartialEq, Eq)]
48pub enum Linbrk {
49    #[doc = "0: Not detected"]
50    NoBreak = 0,
51    #[doc = "1: Detected"]
52    Break = 1,
53}
54impl From<Linbrk> for bool {
55    #[inline(always)]
56    fn from(variant: Linbrk) -> Self {
57        variant as u8 != 0
58    }
59}
60#[doc = "Field `LINBRK` reader - LIN Break"]
61pub type LinbrkR = crate::BitReader<Linbrk>;
62impl LinbrkR {
63    #[doc = "Get enumerated values variant"]
64    #[inline(always)]
65    pub const fn variant(&self) -> Linbrk {
66        match self.bits {
67            false => Linbrk::NoBreak,
68            true => Linbrk::Break,
69        }
70    }
71    #[doc = "Not detected"]
72    #[inline(always)]
73    pub fn is_no_break(&self) -> bool {
74        *self == Linbrk::NoBreak
75    }
76    #[doc = "Detected"]
77    #[inline(always)]
78    pub fn is_break(&self) -> bool {
79        *self == Linbrk::Break
80    }
81}
82#[doc = "Idle Line\n\nValue on reset: 0"]
83#[cfg_attr(feature = "defmt", derive(defmt::Format))]
84#[derive(Clone, Copy, Debug, PartialEq, Eq)]
85pub enum Idline {
86    #[doc = "0: Not idle"]
87    NoIdle = 0,
88    #[doc = "1: Idle"]
89    Idle = 1,
90}
91impl From<Idline> for bool {
92    #[inline(always)]
93    fn from(variant: Idline) -> Self {
94        variant as u8 != 0
95    }
96}
97#[doc = "Field `IDLINE` reader - Idle Line"]
98pub type IdlineR = crate::BitReader<Idline>;
99impl IdlineR {
100    #[doc = "Get enumerated values variant"]
101    #[inline(always)]
102    pub const fn variant(&self) -> Idline {
103        match self.bits {
104            false => Idline::NoIdle,
105            true => Idline::Idle,
106        }
107    }
108    #[doc = "Not idle"]
109    #[inline(always)]
110    pub fn is_no_idle(&self) -> bool {
111        *self == Idline::NoIdle
112    }
113    #[doc = "Idle"]
114    #[inline(always)]
115    pub fn is_idle(&self) -> bool {
116        *self == Idline::Idle
117    }
118}
119#[doc = "Receive Buffer Empty\n\nValue on reset: 1"]
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum Rxempt {
123    #[doc = "0: Valid data"]
124    NotEmpty = 0,
125    #[doc = "1: Invalid data and empty"]
126    Empty = 1,
127}
128impl From<Rxempt> for bool {
129    #[inline(always)]
130    fn from(variant: Rxempt) -> Self {
131        variant as u8 != 0
132    }
133}
134#[doc = "Field `RXEMPT` reader - Receive Buffer Empty"]
135pub type RxemptR = crate::BitReader<Rxempt>;
136impl RxemptR {
137    #[doc = "Get enumerated values variant"]
138    #[inline(always)]
139    pub const fn variant(&self) -> Rxempt {
140        match self.bits {
141            false => Rxempt::NotEmpty,
142            true => Rxempt::Empty,
143        }
144    }
145    #[doc = "Valid data"]
146    #[inline(always)]
147    pub fn is_not_empty(&self) -> bool {
148        *self == Rxempt::NotEmpty
149    }
150    #[doc = "Invalid data and empty"]
151    #[inline(always)]
152    pub fn is_empty(&self) -> bool {
153        *self == Rxempt::Empty
154    }
155}
156#[doc = "Frame Error Transmit Special Character\n\nValue on reset: 0"]
157#[cfg_attr(feature = "defmt", derive(defmt::Format))]
158#[derive(Clone, Copy, Debug, PartialEq, Eq)]
159pub enum Fretsc {
160    #[doc = "0: Received without a frame error on reads or transmits a normal character on writes"]
161    NoError = 0,
162    #[doc = "1: Received with a frame error on reads or transmits an idle or break character on writes"]
163    Error = 1,
164}
165impl From<Fretsc> for bool {
166    #[inline(always)]
167    fn from(variant: Fretsc) -> Self {
168        variant as u8 != 0
169    }
170}
171#[doc = "Field `FRETSC` reader - Frame Error Transmit Special Character"]
172pub type FretscR = crate::BitReader<Fretsc>;
173impl FretscR {
174    #[doc = "Get enumerated values variant"]
175    #[inline(always)]
176    pub const fn variant(&self) -> Fretsc {
177        match self.bits {
178            false => Fretsc::NoError,
179            true => Fretsc::Error,
180        }
181    }
182    #[doc = "Received without a frame error on reads or transmits a normal character on writes"]
183    #[inline(always)]
184    pub fn is_no_error(&self) -> bool {
185        *self == Fretsc::NoError
186    }
187    #[doc = "Received with a frame error on reads or transmits an idle or break character on writes"]
188    #[inline(always)]
189    pub fn is_error(&self) -> bool {
190        *self == Fretsc::Error
191    }
192}
193#[doc = "Field `FRETSC` writer - Frame Error Transmit Special Character"]
194pub type FretscW<'a, REG> = crate::BitWriter<'a, REG, Fretsc>;
195impl<'a, REG> FretscW<'a, REG>
196where
197    REG: crate::Writable + crate::RegisterSpec,
198{
199    #[doc = "Received without a frame error on reads or transmits a normal character on writes"]
200    #[inline(always)]
201    pub fn no_error(self) -> &'a mut crate::W<REG> {
202        self.variant(Fretsc::NoError)
203    }
204    #[doc = "Received with a frame error on reads or transmits an idle or break character on writes"]
205    #[inline(always)]
206    pub fn error(self) -> &'a mut crate::W<REG> {
207        self.variant(Fretsc::Error)
208    }
209}
210#[doc = "Parity Error\n\nValue on reset: 0"]
211#[cfg_attr(feature = "defmt", derive(defmt::Format))]
212#[derive(Clone, Copy, Debug, PartialEq, Eq)]
213pub enum Paritye {
214    #[doc = "0: Received without a parity error"]
215    NoParity = 0,
216    #[doc = "1: Received with a parity error"]
217    Parity = 1,
218}
219impl From<Paritye> for bool {
220    #[inline(always)]
221    fn from(variant: Paritye) -> Self {
222        variant as u8 != 0
223    }
224}
225#[doc = "Field `PARITYE` reader - Parity Error"]
226pub type ParityeR = crate::BitReader<Paritye>;
227impl ParityeR {
228    #[doc = "Get enumerated values variant"]
229    #[inline(always)]
230    pub const fn variant(&self) -> Paritye {
231        match self.bits {
232            false => Paritye::NoParity,
233            true => Paritye::Parity,
234        }
235    }
236    #[doc = "Received without a parity error"]
237    #[inline(always)]
238    pub fn is_no_parity(&self) -> bool {
239        *self == Paritye::NoParity
240    }
241    #[doc = "Received with a parity error"]
242    #[inline(always)]
243    pub fn is_parity(&self) -> bool {
244        *self == Paritye::Parity
245    }
246}
247#[doc = "Noisy Data Received\n\nValue on reset: 0"]
248#[cfg_attr(feature = "defmt", derive(defmt::Format))]
249#[derive(Clone, Copy, Debug, PartialEq, Eq)]
250pub enum Noisy {
251    #[doc = "0: Received without noise"]
252    NoNoise = 0,
253    #[doc = "1: Received with noise"]
254    Noise = 1,
255}
256impl From<Noisy> for bool {
257    #[inline(always)]
258    fn from(variant: Noisy) -> Self {
259        variant as u8 != 0
260    }
261}
262#[doc = "Field `NOISY` reader - Noisy Data Received"]
263pub type NoisyR = crate::BitReader<Noisy>;
264impl NoisyR {
265    #[doc = "Get enumerated values variant"]
266    #[inline(always)]
267    pub const fn variant(&self) -> Noisy {
268        match self.bits {
269            false => Noisy::NoNoise,
270            true => Noisy::Noise,
271        }
272    }
273    #[doc = "Received without noise"]
274    #[inline(always)]
275    pub fn is_no_noise(&self) -> bool {
276        *self == Noisy::NoNoise
277    }
278    #[doc = "Received with noise"]
279    #[inline(always)]
280    pub fn is_noise(&self) -> bool {
281        *self == Noisy::Noise
282    }
283}
284impl R {
285    #[doc = "Bit 0 - Read receive FIFO bit 0 or write transmit FIFO bit 0"]
286    #[inline(always)]
287    pub fn r0t0(&self) -> R0t0R {
288        R0t0R::new((self.bits & 1) != 0)
289    }
290    #[doc = "Bit 1 - Read receive FIFO bit 1 or write transmit FIFO bit 1"]
291    #[inline(always)]
292    pub fn r1t1(&self) -> R1t1R {
293        R1t1R::new(((self.bits >> 1) & 1) != 0)
294    }
295    #[doc = "Bit 2 - Read receive FIFO bit 2 or write transmit FIFO bit 2"]
296    #[inline(always)]
297    pub fn r2t2(&self) -> R2t2R {
298        R2t2R::new(((self.bits >> 2) & 1) != 0)
299    }
300    #[doc = "Bit 3 - Read receive FIFO bit 3 or write transmit FIFO bit 3"]
301    #[inline(always)]
302    pub fn r3t3(&self) -> R3t3R {
303        R3t3R::new(((self.bits >> 3) & 1) != 0)
304    }
305    #[doc = "Bit 4 - Read receive FIFO bit 4 or write transmit FIFO bit 4"]
306    #[inline(always)]
307    pub fn r4t4(&self) -> R4t4R {
308        R4t4R::new(((self.bits >> 4) & 1) != 0)
309    }
310    #[doc = "Bit 5 - Read receive FIFO bit 5 or write transmit FIFO bit 5"]
311    #[inline(always)]
312    pub fn r5t5(&self) -> R5t5R {
313        R5t5R::new(((self.bits >> 5) & 1) != 0)
314    }
315    #[doc = "Bit 6 - Read receive FIFO bit 6 or write transmit FIFO bit 6"]
316    #[inline(always)]
317    pub fn r6t6(&self) -> R6t6R {
318        R6t6R::new(((self.bits >> 6) & 1) != 0)
319    }
320    #[doc = "Bit 7 - Read receive FIFO bit 7 or write transmit FIFO bit 7"]
321    #[inline(always)]
322    pub fn r7t7(&self) -> R7t7R {
323        R7t7R::new(((self.bits >> 7) & 1) != 0)
324    }
325    #[doc = "Bit 8 - Read receive FIFO bit 8 or write transmit FIFO bit 8"]
326    #[inline(always)]
327    pub fn r8t8(&self) -> R8t8R {
328        R8t8R::new(((self.bits >> 8) & 1) != 0)
329    }
330    #[doc = "Bit 9 - Read receive FIFO bit 9 or write transmit FIFO bit 9"]
331    #[inline(always)]
332    pub fn r9t9(&self) -> R9t9R {
333        R9t9R::new(((self.bits >> 9) & 1) != 0)
334    }
335    #[doc = "Bit 10 - LIN Break"]
336    #[inline(always)]
337    pub fn linbrk(&self) -> LinbrkR {
338        LinbrkR::new(((self.bits >> 10) & 1) != 0)
339    }
340    #[doc = "Bit 11 - Idle Line"]
341    #[inline(always)]
342    pub fn idline(&self) -> IdlineR {
343        IdlineR::new(((self.bits >> 11) & 1) != 0)
344    }
345    #[doc = "Bit 12 - Receive Buffer Empty"]
346    #[inline(always)]
347    pub fn rxempt(&self) -> RxemptR {
348        RxemptR::new(((self.bits >> 12) & 1) != 0)
349    }
350    #[doc = "Bit 13 - Frame Error Transmit Special Character"]
351    #[inline(always)]
352    pub fn fretsc(&self) -> FretscR {
353        FretscR::new(((self.bits >> 13) & 1) != 0)
354    }
355    #[doc = "Bit 14 - Parity Error"]
356    #[inline(always)]
357    pub fn paritye(&self) -> ParityeR {
358        ParityeR::new(((self.bits >> 14) & 1) != 0)
359    }
360    #[doc = "Bit 15 - Noisy Data Received"]
361    #[inline(always)]
362    pub fn noisy(&self) -> NoisyR {
363        NoisyR::new(((self.bits >> 15) & 1) != 0)
364    }
365}
366#[cfg(feature = "debug")]
367impl core::fmt::Debug for R {
368    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
369        f.debug_struct("DATA")
370            .field("r0t0", &self.r0t0())
371            .field("r1t1", &self.r1t1())
372            .field("r2t2", &self.r2t2())
373            .field("r3t3", &self.r3t3())
374            .field("r4t4", &self.r4t4())
375            .field("r5t5", &self.r5t5())
376            .field("r6t6", &self.r6t6())
377            .field("r7t7", &self.r7t7())
378            .field("r8t8", &self.r8t8())
379            .field("r9t9", &self.r9t9())
380            .field("linbrk", &self.linbrk())
381            .field("idline", &self.idline())
382            .field("rxempt", &self.rxempt())
383            .field("fretsc", &self.fretsc())
384            .field("paritye", &self.paritye())
385            .field("noisy", &self.noisy())
386            .finish()
387    }
388}
389impl W {
390    #[doc = "Bit 0 - Read receive FIFO bit 0 or write transmit FIFO bit 0"]
391    #[inline(always)]
392    pub fn r0t0(&mut self) -> R0t0W<'_, DataSpec> {
393        R0t0W::new(self, 0)
394    }
395    #[doc = "Bit 1 - Read receive FIFO bit 1 or write transmit FIFO bit 1"]
396    #[inline(always)]
397    pub fn r1t1(&mut self) -> R1t1W<'_, DataSpec> {
398        R1t1W::new(self, 1)
399    }
400    #[doc = "Bit 2 - Read receive FIFO bit 2 or write transmit FIFO bit 2"]
401    #[inline(always)]
402    pub fn r2t2(&mut self) -> R2t2W<'_, DataSpec> {
403        R2t2W::new(self, 2)
404    }
405    #[doc = "Bit 3 - Read receive FIFO bit 3 or write transmit FIFO bit 3"]
406    #[inline(always)]
407    pub fn r3t3(&mut self) -> R3t3W<'_, DataSpec> {
408        R3t3W::new(self, 3)
409    }
410    #[doc = "Bit 4 - Read receive FIFO bit 4 or write transmit FIFO bit 4"]
411    #[inline(always)]
412    pub fn r4t4(&mut self) -> R4t4W<'_, DataSpec> {
413        R4t4W::new(self, 4)
414    }
415    #[doc = "Bit 5 - Read receive FIFO bit 5 or write transmit FIFO bit 5"]
416    #[inline(always)]
417    pub fn r5t5(&mut self) -> R5t5W<'_, DataSpec> {
418        R5t5W::new(self, 5)
419    }
420    #[doc = "Bit 6 - Read receive FIFO bit 6 or write transmit FIFO bit 6"]
421    #[inline(always)]
422    pub fn r6t6(&mut self) -> R6t6W<'_, DataSpec> {
423        R6t6W::new(self, 6)
424    }
425    #[doc = "Bit 7 - Read receive FIFO bit 7 or write transmit FIFO bit 7"]
426    #[inline(always)]
427    pub fn r7t7(&mut self) -> R7t7W<'_, DataSpec> {
428        R7t7W::new(self, 7)
429    }
430    #[doc = "Bit 8 - Read receive FIFO bit 8 or write transmit FIFO bit 8"]
431    #[inline(always)]
432    pub fn r8t8(&mut self) -> R8t8W<'_, DataSpec> {
433        R8t8W::new(self, 8)
434    }
435    #[doc = "Bit 9 - Read receive FIFO bit 9 or write transmit FIFO bit 9"]
436    #[inline(always)]
437    pub fn r9t9(&mut self) -> R9t9W<'_, DataSpec> {
438        R9t9W::new(self, 9)
439    }
440    #[doc = "Bit 13 - Frame Error Transmit Special Character"]
441    #[inline(always)]
442    pub fn fretsc(&mut self) -> FretscW<'_, DataSpec> {
443        FretscW::new(self, 13)
444    }
445}
446#[doc = "Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
447pub struct DataSpec;
448impl crate::RegisterSpec for DataSpec {
449    type Ux = u32;
450}
451#[doc = "`read()` method returns [`data::R`](R) reader structure"]
452impl crate::Readable for DataSpec {}
453#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
454impl crate::Writable for DataSpec {
455    type Safety = crate::Unsafe;
456}
457#[doc = "`reset()` method sets DATA to value 0x1000"]
458impl crate::Resettable for DataSpec {
459    const RESET_VALUE: u32 = 0x1000;
460}
mcxa_pac/lpuart0/data.rs

mcxa_pac/lpuart0/
data.rs
