1#[doc = "Register `PIDR` reader"]
2pub type R = crate::R<PidrSpec>;
3#[doc = "Register `PIDR` writer"]
4pub type W = crate::W<PidrSpec>;
5#[doc = "Port Input Disable\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Pid {
9 #[doc = "0: Configured for general-purpose input"]
10 Pid0 = 0,
11 #[doc = "1: Disabled for general-purpose input"]
12 Pid1 = 1,
13}
14impl From<Pid> for bool {
15 #[inline(always)]
16 fn from(variant: Pid) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `PID(0-31)` reader - Port Input Disable"]
21pub type PidR = crate::BitReader<Pid>;
22impl PidR {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> Pid {
26 match self.bits {
27 false => Pid::Pid0,
28 true => Pid::Pid1,
29 }
30 }
31 #[doc = "Configured for general-purpose input"]
32 #[inline(always)]
33 pub fn is_pid0(&self) -> bool {
34 *self == Pid::Pid0
35 }
36 #[doc = "Disabled for general-purpose input"]
37 #[inline(always)]
38 pub fn is_pid1(&self) -> bool {
39 *self == Pid::Pid1
40 }
41}
42#[doc = "Field `PID(0-31)` writer - Port Input Disable"]
43pub type PidW<'a, REG> = crate::BitWriter<'a, REG, Pid>;
44impl<'a, REG> PidW<'a, REG>
45where
46 REG: crate::Writable + crate::RegisterSpec,
47{
48 #[doc = "Configured for general-purpose input"]
49 #[inline(always)]
50 pub fn pid0(self) -> &'a mut crate::W<REG> {
51 self.variant(Pid::Pid0)
52 }
53 #[doc = "Disabled for general-purpose input"]
54 #[inline(always)]
55 pub fn pid1(self) -> &'a mut crate::W<REG> {
56 self.variant(Pid::Pid1)
57 }
58}
59impl R {
60 #[doc = "Port Input Disable"]
61 #[doc = ""]
62 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `PID0` field.</div>"]
63 #[inline(always)]
64 pub fn pid(&self, n: u8) -> PidR {
65 #[allow(clippy::no_effect)]
66 [(); 32][n as usize];
67 PidR::new(((self.bits >> n) & 1) != 0)
68 }
69 #[doc = "Iterator for array of:"]
70 #[doc = "Port Input Disable"]
71 #[inline(always)]
72 pub fn pid_iter(&self) -> impl Iterator<Item = PidR> + '_ {
73 (0..32).map(move |n| PidR::new(((self.bits >> n) & 1) != 0))
74 }
75 #[doc = "Bit 0 - Port Input Disable"]
76 #[inline(always)]
77 pub fn pid0(&self) -> PidR {
78 PidR::new((self.bits & 1) != 0)
79 }
80 #[doc = "Bit 1 - Port Input Disable"]
81 #[inline(always)]
82 pub fn pid1(&self) -> PidR {
83 PidR::new(((self.bits >> 1) & 1) != 0)
84 }
85 #[doc = "Bit 2 - Port Input Disable"]
86 #[inline(always)]
87 pub fn pid2(&self) -> PidR {
88 PidR::new(((self.bits >> 2) & 1) != 0)
89 }
90 #[doc = "Bit 3 - Port Input Disable"]
91 #[inline(always)]
92 pub fn pid3(&self) -> PidR {
93 PidR::new(((self.bits >> 3) & 1) != 0)
94 }
95 #[doc = "Bit 4 - Port Input Disable"]
96 #[inline(always)]
97 pub fn pid4(&self) -> PidR {
98 PidR::new(((self.bits >> 4) & 1) != 0)
99 }
100 #[doc = "Bit 5 - Port Input Disable"]
101 #[inline(always)]
102 pub fn pid5(&self) -> PidR {
103 PidR::new(((self.bits >> 5) & 1) != 0)
104 }
105 #[doc = "Bit 6 - Port Input Disable"]
106 #[inline(always)]
107 pub fn pid6(&self) -> PidR {
108 PidR::new(((self.bits >> 6) & 1) != 0)
109 }
110 #[doc = "Bit 7 - Port Input Disable"]
111 #[inline(always)]
112 pub fn pid7(&self) -> PidR {
113 PidR::new(((self.bits >> 7) & 1) != 0)
114 }
115 #[doc = "Bit 8 - Port Input Disable"]
116 #[inline(always)]
117 pub fn pid8(&self) -> PidR {
118 PidR::new(((self.bits >> 8) & 1) != 0)
119 }
120 #[doc = "Bit 9 - Port Input Disable"]
121 #[inline(always)]
122 pub fn pid9(&self) -> PidR {
123 PidR::new(((self.bits >> 9) & 1) != 0)
124 }
125 #[doc = "Bit 10 - Port Input Disable"]
126 #[inline(always)]
127 pub fn pid10(&self) -> PidR {
128 PidR::new(((self.bits >> 10) & 1) != 0)
129 }
130 #[doc = "Bit 11 - Port Input Disable"]
131 #[inline(always)]
132 pub fn pid11(&self) -> PidR {
133 PidR::new(((self.bits >> 11) & 1) != 0)
134 }
135 #[doc = "Bit 12 - Port Input Disable"]
136 #[inline(always)]
137 pub fn pid12(&self) -> PidR {
138 PidR::new(((self.bits >> 12) & 1) != 0)
139 }
140 #[doc = "Bit 13 - Port Input Disable"]
141 #[inline(always)]
142 pub fn pid13(&self) -> PidR {
143 PidR::new(((self.bits >> 13) & 1) != 0)
144 }
145 #[doc = "Bit 14 - Port Input Disable"]
146 #[inline(always)]
147 pub fn pid14(&self) -> PidR {
148 PidR::new(((self.bits >> 14) & 1) != 0)
149 }
150 #[doc = "Bit 15 - Port Input Disable"]
151 #[inline(always)]
152 pub fn pid15(&self) -> PidR {
153 PidR::new(((self.bits >> 15) & 1) != 0)
154 }
155 #[doc = "Bit 16 - Port Input Disable"]
156 #[inline(always)]
157 pub fn pid16(&self) -> PidR {
158 PidR::new(((self.bits >> 16) & 1) != 0)
159 }
160 #[doc = "Bit 17 - Port Input Disable"]
161 #[inline(always)]
162 pub fn pid17(&self) -> PidR {
163 PidR::new(((self.bits >> 17) & 1) != 0)
164 }
165 #[doc = "Bit 18 - Port Input Disable"]
166 #[inline(always)]
167 pub fn pid18(&self) -> PidR {
168 PidR::new(((self.bits >> 18) & 1) != 0)
169 }
170 #[doc = "Bit 19 - Port Input Disable"]
171 #[inline(always)]
172 pub fn pid19(&self) -> PidR {
173 PidR::new(((self.bits >> 19) & 1) != 0)
174 }
175 #[doc = "Bit 20 - Port Input Disable"]
176 #[inline(always)]
177 pub fn pid20(&self) -> PidR {
178 PidR::new(((self.bits >> 20) & 1) != 0)
179 }
180 #[doc = "Bit 21 - Port Input Disable"]
181 #[inline(always)]
182 pub fn pid21(&self) -> PidR {
183 PidR::new(((self.bits >> 21) & 1) != 0)
184 }
185 #[doc = "Bit 22 - Port Input Disable"]
186 #[inline(always)]
187 pub fn pid22(&self) -> PidR {
188 PidR::new(((self.bits >> 22) & 1) != 0)
189 }
190 #[doc = "Bit 23 - Port Input Disable"]
191 #[inline(always)]
192 pub fn pid23(&self) -> PidR {
193 PidR::new(((self.bits >> 23) & 1) != 0)
194 }
195 #[doc = "Bit 24 - Port Input Disable"]
196 #[inline(always)]
197 pub fn pid24(&self) -> PidR {
198 PidR::new(((self.bits >> 24) & 1) != 0)
199 }
200 #[doc = "Bit 25 - Port Input Disable"]
201 #[inline(always)]
202 pub fn pid25(&self) -> PidR {
203 PidR::new(((self.bits >> 25) & 1) != 0)
204 }
205 #[doc = "Bit 26 - Port Input Disable"]
206 #[inline(always)]
207 pub fn pid26(&self) -> PidR {
208 PidR::new(((self.bits >> 26) & 1) != 0)
209 }
210 #[doc = "Bit 27 - Port Input Disable"]
211 #[inline(always)]
212 pub fn pid27(&self) -> PidR {
213 PidR::new(((self.bits >> 27) & 1) != 0)
214 }
215 #[doc = "Bit 28 - Port Input Disable"]
216 #[inline(always)]
217 pub fn pid28(&self) -> PidR {
218 PidR::new(((self.bits >> 28) & 1) != 0)
219 }
220 #[doc = "Bit 29 - Port Input Disable"]
221 #[inline(always)]
222 pub fn pid29(&self) -> PidR {
223 PidR::new(((self.bits >> 29) & 1) != 0)
224 }
225 #[doc = "Bit 30 - Port Input Disable"]
226 #[inline(always)]
227 pub fn pid30(&self) -> PidR {
228 PidR::new(((self.bits >> 30) & 1) != 0)
229 }
230 #[doc = "Bit 31 - Port Input Disable"]
231 #[inline(always)]
232 pub fn pid31(&self) -> PidR {
233 PidR::new(((self.bits >> 31) & 1) != 0)
234 }
235}
236#[cfg(feature = "debug")]
237impl core::fmt::Debug for R {
238 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
239 f.debug_struct("PIDR")
240 .field("pid0", &self.pid0())
241 .field("pid1", &self.pid1())
242 .field("pid2", &self.pid2())
243 .field("pid3", &self.pid3())
244 .field("pid4", &self.pid4())
245 .field("pid5", &self.pid5())
246 .field("pid6", &self.pid6())
247 .field("pid7", &self.pid7())
248 .field("pid8", &self.pid8())
249 .field("pid9", &self.pid9())
250 .field("pid10", &self.pid10())
251 .field("pid11", &self.pid11())
252 .field("pid12", &self.pid12())
253 .field("pid13", &self.pid13())
254 .field("pid14", &self.pid14())
255 .field("pid15", &self.pid15())
256 .field("pid16", &self.pid16())
257 .field("pid17", &self.pid17())
258 .field("pid18", &self.pid18())
259 .field("pid19", &self.pid19())
260 .field("pid20", &self.pid20())
261 .field("pid21", &self.pid21())
262 .field("pid22", &self.pid22())
263 .field("pid23", &self.pid23())
264 .field("pid24", &self.pid24())
265 .field("pid25", &self.pid25())
266 .field("pid26", &self.pid26())
267 .field("pid27", &self.pid27())
268 .field("pid28", &self.pid28())
269 .field("pid29", &self.pid29())
270 .field("pid30", &self.pid30())
271 .field("pid31", &self.pid31())
272 .finish()
273 }
274}
275impl W {
276 #[doc = "Port Input Disable"]
277 #[doc = ""]
278 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `PID0` field.</div>"]
279 #[inline(always)]
280 pub fn pid(&mut self, n: u8) -> PidW<'_, PidrSpec> {
281 #[allow(clippy::no_effect)]
282 [(); 32][n as usize];
283 PidW::new(self, n)
284 }
285 #[doc = "Bit 0 - Port Input Disable"]
286 #[inline(always)]
287 pub fn pid0(&mut self) -> PidW<'_, PidrSpec> {
288 PidW::new(self, 0)
289 }
290 #[doc = "Bit 1 - Port Input Disable"]
291 #[inline(always)]
292 pub fn pid1(&mut self) -> PidW<'_, PidrSpec> {
293 PidW::new(self, 1)
294 }
295 #[doc = "Bit 2 - Port Input Disable"]
296 #[inline(always)]
297 pub fn pid2(&mut self) -> PidW<'_, PidrSpec> {
298 PidW::new(self, 2)
299 }
300 #[doc = "Bit 3 - Port Input Disable"]
301 #[inline(always)]
302 pub fn pid3(&mut self) -> PidW<'_, PidrSpec> {
303 PidW::new(self, 3)
304 }
305 #[doc = "Bit 4 - Port Input Disable"]
306 #[inline(always)]
307 pub fn pid4(&mut self) -> PidW<'_, PidrSpec> {
308 PidW::new(self, 4)
309 }
310 #[doc = "Bit 5 - Port Input Disable"]
311 #[inline(always)]
312 pub fn pid5(&mut self) -> PidW<'_, PidrSpec> {
313 PidW::new(self, 5)
314 }
315 #[doc = "Bit 6 - Port Input Disable"]
316 #[inline(always)]
317 pub fn pid6(&mut self) -> PidW<'_, PidrSpec> {
318 PidW::new(self, 6)
319 }
320 #[doc = "Bit 7 - Port Input Disable"]
321 #[inline(always)]
322 pub fn pid7(&mut self) -> PidW<'_, PidrSpec> {
323 PidW::new(self, 7)
324 }
325 #[doc = "Bit 8 - Port Input Disable"]
326 #[inline(always)]
327 pub fn pid8(&mut self) -> PidW<'_, PidrSpec> {
328 PidW::new(self, 8)
329 }
330 #[doc = "Bit 9 - Port Input Disable"]
331 #[inline(always)]
332 pub fn pid9(&mut self) -> PidW<'_, PidrSpec> {
333 PidW::new(self, 9)
334 }
335 #[doc = "Bit 10 - Port Input Disable"]
336 #[inline(always)]
337 pub fn pid10(&mut self) -> PidW<'_, PidrSpec> {
338 PidW::new(self, 10)
339 }
340 #[doc = "Bit 11 - Port Input Disable"]
341 #[inline(always)]
342 pub fn pid11(&mut self) -> PidW<'_, PidrSpec> {
343 PidW::new(self, 11)
344 }
345 #[doc = "Bit 12 - Port Input Disable"]
346 #[inline(always)]
347 pub fn pid12(&mut self) -> PidW<'_, PidrSpec> {
348 PidW::new(self, 12)
349 }
350 #[doc = "Bit 13 - Port Input Disable"]
351 #[inline(always)]
352 pub fn pid13(&mut self) -> PidW<'_, PidrSpec> {
353 PidW::new(self, 13)
354 }
355 #[doc = "Bit 14 - Port Input Disable"]
356 #[inline(always)]
357 pub fn pid14(&mut self) -> PidW<'_, PidrSpec> {
358 PidW::new(self, 14)
359 }
360 #[doc = "Bit 15 - Port Input Disable"]
361 #[inline(always)]
362 pub fn pid15(&mut self) -> PidW<'_, PidrSpec> {
363 PidW::new(self, 15)
364 }
365 #[doc = "Bit 16 - Port Input Disable"]
366 #[inline(always)]
367 pub fn pid16(&mut self) -> PidW<'_, PidrSpec> {
368 PidW::new(self, 16)
369 }
370 #[doc = "Bit 17 - Port Input Disable"]
371 #[inline(always)]
372 pub fn pid17(&mut self) -> PidW<'_, PidrSpec> {
373 PidW::new(self, 17)
374 }
375 #[doc = "Bit 18 - Port Input Disable"]
376 #[inline(always)]
377 pub fn pid18(&mut self) -> PidW<'_, PidrSpec> {
378 PidW::new(self, 18)
379 }
380 #[doc = "Bit 19 - Port Input Disable"]
381 #[inline(always)]
382 pub fn pid19(&mut self) -> PidW<'_, PidrSpec> {
383 PidW::new(self, 19)
384 }
385 #[doc = "Bit 20 - Port Input Disable"]
386 #[inline(always)]
387 pub fn pid20(&mut self) -> PidW<'_, PidrSpec> {
388 PidW::new(self, 20)
389 }
390 #[doc = "Bit 21 - Port Input Disable"]
391 #[inline(always)]
392 pub fn pid21(&mut self) -> PidW<'_, PidrSpec> {
393 PidW::new(self, 21)
394 }
395 #[doc = "Bit 22 - Port Input Disable"]
396 #[inline(always)]
397 pub fn pid22(&mut self) -> PidW<'_, PidrSpec> {
398 PidW::new(self, 22)
399 }
400 #[doc = "Bit 23 - Port Input Disable"]
401 #[inline(always)]
402 pub fn pid23(&mut self) -> PidW<'_, PidrSpec> {
403 PidW::new(self, 23)
404 }
405 #[doc = "Bit 24 - Port Input Disable"]
406 #[inline(always)]
407 pub fn pid24(&mut self) -> PidW<'_, PidrSpec> {
408 PidW::new(self, 24)
409 }
410 #[doc = "Bit 25 - Port Input Disable"]
411 #[inline(always)]
412 pub fn pid25(&mut self) -> PidW<'_, PidrSpec> {
413 PidW::new(self, 25)
414 }
415 #[doc = "Bit 26 - Port Input Disable"]
416 #[inline(always)]
417 pub fn pid26(&mut self) -> PidW<'_, PidrSpec> {
418 PidW::new(self, 26)
419 }
420 #[doc = "Bit 27 - Port Input Disable"]
421 #[inline(always)]
422 pub fn pid27(&mut self) -> PidW<'_, PidrSpec> {
423 PidW::new(self, 27)
424 }
425 #[doc = "Bit 28 - Port Input Disable"]
426 #[inline(always)]
427 pub fn pid28(&mut self) -> PidW<'_, PidrSpec> {
428 PidW::new(self, 28)
429 }
430 #[doc = "Bit 29 - Port Input Disable"]
431 #[inline(always)]
432 pub fn pid29(&mut self) -> PidW<'_, PidrSpec> {
433 PidW::new(self, 29)
434 }
435 #[doc = "Bit 30 - Port Input Disable"]
436 #[inline(always)]
437 pub fn pid30(&mut self) -> PidW<'_, PidrSpec> {
438 PidW::new(self, 30)
439 }
440 #[doc = "Bit 31 - Port Input Disable"]
441 #[inline(always)]
442 pub fn pid31(&mut self) -> PidW<'_, PidrSpec> {
443 PidW::new(self, 31)
444 }
445}
446#[doc = "Port Input Disable\n\nYou can [`read`](crate::Reg::read) this register and get [`pidr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
447pub struct PidrSpec;
448impl crate::RegisterSpec for PidrSpec {
449 type Ux = u32;
450}
451#[doc = "`read()` method returns [`pidr::R`](R) reader structure"]
452impl crate::Readable for PidrSpec {}
453#[doc = "`write(|w| ..)` method takes [`pidr::W`](W) writer structure"]
454impl crate::Writable for PidrSpec {
455 type Safety = crate::Unsafe;
456}
457#[doc = "`reset()` method sets PIDR to value 0"]
458impl crate::Resettable for PidrSpec {}