1#[doc = "Register `FCTRL` reader"]
2pub type R = crate::R<FctrlSpec>;
3#[doc = "Register `FCTRL` writer"]
4pub type W = crate::W<FctrlSpec>;
5#[doc = "Field `RWSC` reader - Read Wait-State Control"]
6pub type RwscR = crate::FieldReader;
7#[doc = "Field `RWSC` writer - Read Wait-State Control"]
8pub type RwscW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Low speed active mode\n\nValue on reset: 1"]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12pub enum Lsactive {
13 #[doc = "0: Full speed active mode requested"]
14 Lsactive0 = 0,
15 #[doc = "1: Low speed active mode requested"]
16 Lsactive1 = 1,
17}
18impl From<Lsactive> for bool {
19 #[inline(always)]
20 fn from(variant: Lsactive) -> Self {
21 variant as u8 != 0
22 }
23}
24#[doc = "Field `LSACTIVE` reader - Low speed active mode"]
25pub type LsactiveR = crate::BitReader<Lsactive>;
26impl LsactiveR {
27 #[doc = "Get enumerated values variant"]
28 #[inline(always)]
29 pub const fn variant(&self) -> Lsactive {
30 match self.bits {
31 false => Lsactive::Lsactive0,
32 true => Lsactive::Lsactive1,
33 }
34 }
35 #[doc = "Full speed active mode requested"]
36 #[inline(always)]
37 pub fn is_lsactive0(&self) -> bool {
38 *self == Lsactive::Lsactive0
39 }
40 #[doc = "Low speed active mode requested"]
41 #[inline(always)]
42 pub fn is_lsactive1(&self) -> bool {
43 *self == Lsactive::Lsactive1
44 }
45}
46#[doc = "Field `LSACTIVE` writer - Low speed active mode"]
47pub type LsactiveW<'a, REG> = crate::BitWriter<'a, REG, Lsactive>;
48impl<'a, REG> LsactiveW<'a, REG>
49where
50 REG: crate::Writable + crate::RegisterSpec,
51{
52 #[doc = "Full speed active mode requested"]
53 #[inline(always)]
54 pub fn lsactive0(self) -> &'a mut crate::W<REG> {
55 self.variant(Lsactive::Lsactive0)
56 }
57 #[doc = "Low speed active mode requested"]
58 #[inline(always)]
59 pub fn lsactive1(self) -> &'a mut crate::W<REG> {
60 self.variant(Lsactive::Lsactive1)
61 }
62}
63#[doc = "Force Double Bit Fault Detect\n\nValue on reset: 0"]
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum Fdfd {
67 #[doc = "0: FSTAT\\[DFDIF\\] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller"]
68 Fdfd0 = 0,
69 #[doc = "1: FSTAT\\[DFDIF\\] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set."]
70 Fdfd1 = 1,
71}
72impl From<Fdfd> for bool {
73 #[inline(always)]
74 fn from(variant: Fdfd) -> Self {
75 variant as u8 != 0
76 }
77}
78#[doc = "Field `FDFD` reader - Force Double Bit Fault Detect"]
79pub type FdfdR = crate::BitReader<Fdfd>;
80impl FdfdR {
81 #[doc = "Get enumerated values variant"]
82 #[inline(always)]
83 pub const fn variant(&self) -> Fdfd {
84 match self.bits {
85 false => Fdfd::Fdfd0,
86 true => Fdfd::Fdfd1,
87 }
88 }
89 #[doc = "FSTAT\\[DFDIF\\] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller"]
90 #[inline(always)]
91 pub fn is_fdfd0(&self) -> bool {
92 *self == Fdfd::Fdfd0
93 }
94 #[doc = "FSTAT\\[DFDIF\\] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set."]
95 #[inline(always)]
96 pub fn is_fdfd1(&self) -> bool {
97 *self == Fdfd::Fdfd1
98 }
99}
100#[doc = "Field `FDFD` writer - Force Double Bit Fault Detect"]
101pub type FdfdW<'a, REG> = crate::BitWriter<'a, REG, Fdfd>;
102impl<'a, REG> FdfdW<'a, REG>
103where
104 REG: crate::Writable + crate::RegisterSpec,
105{
106 #[doc = "FSTAT\\[DFDIF\\] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller"]
107 #[inline(always)]
108 pub fn fdfd0(self) -> &'a mut crate::W<REG> {
109 self.variant(Fdfd::Fdfd0)
110 }
111 #[doc = "FSTAT\\[DFDIF\\] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set."]
112 #[inline(always)]
113 pub fn fdfd1(self) -> &'a mut crate::W<REG> {
114 self.variant(Fdfd::Fdfd1)
115 }
116}
117#[doc = "Abort Request\n\nValue on reset: 0"]
118#[cfg_attr(feature = "defmt", derive(defmt::Format))]
119#[derive(Clone, Copy, Debug, PartialEq, Eq)]
120pub enum Abtreq {
121 #[doc = "0: No request to abort a command write sequence"]
122 Abtreq0 = 0,
123 #[doc = "1: Request to abort a command write sequence"]
124 Abtreq1 = 1,
125}
126impl From<Abtreq> for bool {
127 #[inline(always)]
128 fn from(variant: Abtreq) -> Self {
129 variant as u8 != 0
130 }
131}
132#[doc = "Field `ABTREQ` reader - Abort Request"]
133pub type AbtreqR = crate::BitReader<Abtreq>;
134impl AbtreqR {
135 #[doc = "Get enumerated values variant"]
136 #[inline(always)]
137 pub const fn variant(&self) -> Abtreq {
138 match self.bits {
139 false => Abtreq::Abtreq0,
140 true => Abtreq::Abtreq1,
141 }
142 }
143 #[doc = "No request to abort a command write sequence"]
144 #[inline(always)]
145 pub fn is_abtreq0(&self) -> bool {
146 *self == Abtreq::Abtreq0
147 }
148 #[doc = "Request to abort a command write sequence"]
149 #[inline(always)]
150 pub fn is_abtreq1(&self) -> bool {
151 *self == Abtreq::Abtreq1
152 }
153}
154#[doc = "Field `ABTREQ` writer - Abort Request"]
155pub type AbtreqW<'a, REG> = crate::BitWriter<'a, REG, Abtreq>;
156impl<'a, REG> AbtreqW<'a, REG>
157where
158 REG: crate::Writable + crate::RegisterSpec,
159{
160 #[doc = "No request to abort a command write sequence"]
161 #[inline(always)]
162 pub fn abtreq0(self) -> &'a mut crate::W<REG> {
163 self.variant(Abtreq::Abtreq0)
164 }
165 #[doc = "Request to abort a command write sequence"]
166 #[inline(always)]
167 pub fn abtreq1(self) -> &'a mut crate::W<REG> {
168 self.variant(Abtreq::Abtreq1)
169 }
170}
171impl R {
172 #[doc = "Bits 0:3 - Read Wait-State Control"]
173 #[inline(always)]
174 pub fn rwsc(&self) -> RwscR {
175 RwscR::new((self.bits & 0x0f) as u8)
176 }
177 #[doc = "Bit 8 - Low speed active mode"]
178 #[inline(always)]
179 pub fn lsactive(&self) -> LsactiveR {
180 LsactiveR::new(((self.bits >> 8) & 1) != 0)
181 }
182 #[doc = "Bit 16 - Force Double Bit Fault Detect"]
183 #[inline(always)]
184 pub fn fdfd(&self) -> FdfdR {
185 FdfdR::new(((self.bits >> 16) & 1) != 0)
186 }
187 #[doc = "Bit 24 - Abort Request"]
188 #[inline(always)]
189 pub fn abtreq(&self) -> AbtreqR {
190 AbtreqR::new(((self.bits >> 24) & 1) != 0)
191 }
192}
193#[cfg(feature = "debug")]
194impl core::fmt::Debug for R {
195 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
196 f.debug_struct("FCTRL")
197 .field("rwsc", &self.rwsc())
198 .field("lsactive", &self.lsactive())
199 .field("fdfd", &self.fdfd())
200 .field("abtreq", &self.abtreq())
201 .finish()
202 }
203}
204impl W {
205 #[doc = "Bits 0:3 - Read Wait-State Control"]
206 #[inline(always)]
207 pub fn rwsc(&mut self) -> RwscW<'_, FctrlSpec> {
208 RwscW::new(self, 0)
209 }
210 #[doc = "Bit 8 - Low speed active mode"]
211 #[inline(always)]
212 pub fn lsactive(&mut self) -> LsactiveW<'_, FctrlSpec> {
213 LsactiveW::new(self, 8)
214 }
215 #[doc = "Bit 16 - Force Double Bit Fault Detect"]
216 #[inline(always)]
217 pub fn fdfd(&mut self) -> FdfdW<'_, FctrlSpec> {
218 FdfdW::new(self, 16)
219 }
220 #[doc = "Bit 24 - Abort Request"]
221 #[inline(always)]
222 pub fn abtreq(&mut self) -> AbtreqW<'_, FctrlSpec> {
223 AbtreqW::new(self, 24)
224 }
225}
226#[doc = "Flash Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
227pub struct FctrlSpec;
228impl crate::RegisterSpec for FctrlSpec {
229 type Ux = u32;
230}
231#[doc = "`read()` method returns [`fctrl::R`](R) reader structure"]
232impl crate::Readable for FctrlSpec {}
233#[doc = "`write(|w| ..)` method takes [`fctrl::W`](W) writer structure"]
234impl crate::Writable for FctrlSpec {
235 type Safety = crate::Unsafe;
236}
237#[doc = "`reset()` method sets FCTRL to value 0x0100"]
238impl crate::Resettable for FctrlSpec {
239 const RESET_VALUE: u32 = 0x0100;
240}