1#[doc = "Register `SM0CTRL` reader"]
2pub type R = crate::R<Sm0ctrlSpec>;
3#[doc = "Register `SM0CTRL` writer"]
4pub type W = crate::W<Sm0ctrlSpec>;
5#[doc = "Double Switching Enable\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Dblen {
9 #[doc = "0: Double switching disabled."]
10 Disabled = 0,
11 #[doc = "1: Double switching enabled."]
12 Enabled = 1,
13}
14impl From<Dblen> for bool {
15 #[inline(always)]
16 fn from(variant: Dblen) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `DBLEN` reader - Double Switching Enable"]
21pub type DblenR = crate::BitReader<Dblen>;
22impl DblenR {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> Dblen {
26 match self.bits {
27 false => Dblen::Disabled,
28 true => Dblen::Enabled,
29 }
30 }
31 #[doc = "Double switching disabled."]
32 #[inline(always)]
33 pub fn is_disabled(&self) -> bool {
34 *self == Dblen::Disabled
35 }
36 #[doc = "Double switching enabled."]
37 #[inline(always)]
38 pub fn is_enabled(&self) -> bool {
39 *self == Dblen::Enabled
40 }
41}
42#[doc = "Field `DBLEN` writer - Double Switching Enable"]
43pub type DblenW<'a, REG> = crate::BitWriter<'a, REG, Dblen>;
44impl<'a, REG> DblenW<'a, REG>
45where
46 REG: crate::Writable + crate::RegisterSpec,
47{
48 #[doc = "Double switching disabled."]
49 #[inline(always)]
50 pub fn disabled(self) -> &'a mut crate::W<REG> {
51 self.variant(Dblen::Disabled)
52 }
53 #[doc = "Double switching enabled."]
54 #[inline(always)]
55 pub fn enabled(self) -> &'a mut crate::W<REG> {
56 self.variant(Dblen::Enabled)
57 }
58}
59#[doc = "PWM_X Double Switching Enable\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Dblx {
63 #[doc = "0: PWM_X double pulse disabled."]
64 Disabled = 0,
65 #[doc = "1: PWM_X double pulse enabled."]
66 Enabled = 1,
67}
68impl From<Dblx> for bool {
69 #[inline(always)]
70 fn from(variant: Dblx) -> Self {
71 variant as u8 != 0
72 }
73}
74#[doc = "Field `DBLX` reader - PWM_X Double Switching Enable"]
75pub type DblxR = crate::BitReader<Dblx>;
76impl DblxR {
77 #[doc = "Get enumerated values variant"]
78 #[inline(always)]
79 pub const fn variant(&self) -> Dblx {
80 match self.bits {
81 false => Dblx::Disabled,
82 true => Dblx::Enabled,
83 }
84 }
85 #[doc = "PWM_X double pulse disabled."]
86 #[inline(always)]
87 pub fn is_disabled(&self) -> bool {
88 *self == Dblx::Disabled
89 }
90 #[doc = "PWM_X double pulse enabled."]
91 #[inline(always)]
92 pub fn is_enabled(&self) -> bool {
93 *self == Dblx::Enabled
94 }
95}
96#[doc = "Field `DBLX` writer - PWM_X Double Switching Enable"]
97pub type DblxW<'a, REG> = crate::BitWriter<'a, REG, Dblx>;
98impl<'a, REG> DblxW<'a, REG>
99where
100 REG: crate::Writable + crate::RegisterSpec,
101{
102 #[doc = "PWM_X double pulse disabled."]
103 #[inline(always)]
104 pub fn disabled(self) -> &'a mut crate::W<REG> {
105 self.variant(Dblx::Disabled)
106 }
107 #[doc = "PWM_X double pulse enabled."]
108 #[inline(always)]
109 pub fn enabled(self) -> &'a mut crate::W<REG> {
110 self.variant(Dblx::Enabled)
111 }
112}
113#[doc = "Load Mode Select\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Ldmod {
117 #[doc = "0: Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."]
118 NextPwmReload = 0,
119 #[doc = "1: Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."]
120 MtctrlLdokSet = 1,
121}
122impl From<Ldmod> for bool {
123 #[inline(always)]
124 fn from(variant: Ldmod) -> Self {
125 variant as u8 != 0
126 }
127}
128#[doc = "Field `LDMOD` reader - Load Mode Select"]
129pub type LdmodR = crate::BitReader<Ldmod>;
130impl LdmodR {
131 #[doc = "Get enumerated values variant"]
132 #[inline(always)]
133 pub const fn variant(&self) -> Ldmod {
134 match self.bits {
135 false => Ldmod::NextPwmReload,
136 true => Ldmod::MtctrlLdokSet,
137 }
138 }
139 #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."]
140 #[inline(always)]
141 pub fn is_next_pwm_reload(&self) -> bool {
142 *self == Ldmod::NextPwmReload
143 }
144 #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."]
145 #[inline(always)]
146 pub fn is_mtctrl_ldok_set(&self) -> bool {
147 *self == Ldmod::MtctrlLdokSet
148 }
149}
150#[doc = "Field `LDMOD` writer - Load Mode Select"]
151pub type LdmodW<'a, REG> = crate::BitWriter<'a, REG, Ldmod>;
152impl<'a, REG> LdmodW<'a, REG>
153where
154 REG: crate::Writable + crate::RegisterSpec,
155{
156 #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."]
157 #[inline(always)]
158 pub fn next_pwm_reload(self) -> &'a mut crate::W<REG> {
159 self.variant(Ldmod::NextPwmReload)
160 }
161 #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."]
162 #[inline(always)]
163 pub fn mtctrl_ldok_set(self) -> &'a mut crate::W<REG> {
164 self.variant(Ldmod::MtctrlLdokSet)
165 }
166}
167#[doc = "Split the DBLPWM signal to PWM_A and PWM_B\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Split {
171 #[doc = "0: DBLPWM is not split. PWM_A and PWM_B each have double pulses."]
172 Disabled = 0,
173 #[doc = "1: DBLPWM is split to PWM_A and PWM_B."]
174 Enabled = 1,
175}
176impl From<Split> for bool {
177 #[inline(always)]
178 fn from(variant: Split) -> Self {
179 variant as u8 != 0
180 }
181}
182#[doc = "Field `SPLIT` reader - Split the DBLPWM signal to PWM_A and PWM_B"]
183pub type SplitR = crate::BitReader<Split>;
184impl SplitR {
185 #[doc = "Get enumerated values variant"]
186 #[inline(always)]
187 pub const fn variant(&self) -> Split {
188 match self.bits {
189 false => Split::Disabled,
190 true => Split::Enabled,
191 }
192 }
193 #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."]
194 #[inline(always)]
195 pub fn is_disabled(&self) -> bool {
196 *self == Split::Disabled
197 }
198 #[doc = "DBLPWM is split to PWM_A and PWM_B."]
199 #[inline(always)]
200 pub fn is_enabled(&self) -> bool {
201 *self == Split::Enabled
202 }
203}
204#[doc = "Field `SPLIT` writer - Split the DBLPWM signal to PWM_A and PWM_B"]
205pub type SplitW<'a, REG> = crate::BitWriter<'a, REG, Split>;
206impl<'a, REG> SplitW<'a, REG>
207where
208 REG: crate::Writable + crate::RegisterSpec,
209{
210 #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."]
211 #[inline(always)]
212 pub fn disabled(self) -> &'a mut crate::W<REG> {
213 self.variant(Split::Disabled)
214 }
215 #[doc = "DBLPWM is split to PWM_A and PWM_B."]
216 #[inline(always)]
217 pub fn enabled(self) -> &'a mut crate::W<REG> {
218 self.variant(Split::Enabled)
219 }
220}
221#[doc = "Prescaler\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224#[repr(u8)]
225pub enum Prsc {
226 #[doc = "0: Prescaler 1"]
227 One = 0,
228 #[doc = "1: Prescaler 2"]
229 Two = 1,
230 #[doc = "2: Prescaler 4"]
231 Four = 2,
232 #[doc = "3: Prescaler 8"]
233 Eight = 3,
234 #[doc = "4: Prescaler 16"]
235 Sixteen = 4,
236 #[doc = "5: Prescaler 32"]
237 Thirtytwo = 5,
238 #[doc = "6: Prescaler 64"]
239 Sixtyfour = 6,
240 #[doc = "7: Prescaler 128"]
241 Hundredtwentyeight = 7,
242}
243impl From<Prsc> for u8 {
244 #[inline(always)]
245 fn from(variant: Prsc) -> Self {
246 variant as _
247 }
248}
249impl crate::FieldSpec for Prsc {
250 type Ux = u8;
251}
252impl crate::IsEnum for Prsc {}
253#[doc = "Field `PRSC` reader - Prescaler"]
254pub type PrscR = crate::FieldReader<Prsc>;
255impl PrscR {
256 #[doc = "Get enumerated values variant"]
257 #[inline(always)]
258 pub const fn variant(&self) -> Prsc {
259 match self.bits {
260 0 => Prsc::One,
261 1 => Prsc::Two,
262 2 => Prsc::Four,
263 3 => Prsc::Eight,
264 4 => Prsc::Sixteen,
265 5 => Prsc::Thirtytwo,
266 6 => Prsc::Sixtyfour,
267 7 => Prsc::Hundredtwentyeight,
268 _ => unreachable!(),
269 }
270 }
271 #[doc = "Prescaler 1"]
272 #[inline(always)]
273 pub fn is_one(&self) -> bool {
274 *self == Prsc::One
275 }
276 #[doc = "Prescaler 2"]
277 #[inline(always)]
278 pub fn is_two(&self) -> bool {
279 *self == Prsc::Two
280 }
281 #[doc = "Prescaler 4"]
282 #[inline(always)]
283 pub fn is_four(&self) -> bool {
284 *self == Prsc::Four
285 }
286 #[doc = "Prescaler 8"]
287 #[inline(always)]
288 pub fn is_eight(&self) -> bool {
289 *self == Prsc::Eight
290 }
291 #[doc = "Prescaler 16"]
292 #[inline(always)]
293 pub fn is_sixteen(&self) -> bool {
294 *self == Prsc::Sixteen
295 }
296 #[doc = "Prescaler 32"]
297 #[inline(always)]
298 pub fn is_thirtytwo(&self) -> bool {
299 *self == Prsc::Thirtytwo
300 }
301 #[doc = "Prescaler 64"]
302 #[inline(always)]
303 pub fn is_sixtyfour(&self) -> bool {
304 *self == Prsc::Sixtyfour
305 }
306 #[doc = "Prescaler 128"]
307 #[inline(always)]
308 pub fn is_hundredtwentyeight(&self) -> bool {
309 *self == Prsc::Hundredtwentyeight
310 }
311}
312#[doc = "Field `PRSC` writer - Prescaler"]
313pub type PrscW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prsc, crate::Safe>;
314impl<'a, REG> PrscW<'a, REG>
315where
316 REG: crate::Writable + crate::RegisterSpec,
317 REG::Ux: From<u8>,
318{
319 #[doc = "Prescaler 1"]
320 #[inline(always)]
321 pub fn one(self) -> &'a mut crate::W<REG> {
322 self.variant(Prsc::One)
323 }
324 #[doc = "Prescaler 2"]
325 #[inline(always)]
326 pub fn two(self) -> &'a mut crate::W<REG> {
327 self.variant(Prsc::Two)
328 }
329 #[doc = "Prescaler 4"]
330 #[inline(always)]
331 pub fn four(self) -> &'a mut crate::W<REG> {
332 self.variant(Prsc::Four)
333 }
334 #[doc = "Prescaler 8"]
335 #[inline(always)]
336 pub fn eight(self) -> &'a mut crate::W<REG> {
337 self.variant(Prsc::Eight)
338 }
339 #[doc = "Prescaler 16"]
340 #[inline(always)]
341 pub fn sixteen(self) -> &'a mut crate::W<REG> {
342 self.variant(Prsc::Sixteen)
343 }
344 #[doc = "Prescaler 32"]
345 #[inline(always)]
346 pub fn thirtytwo(self) -> &'a mut crate::W<REG> {
347 self.variant(Prsc::Thirtytwo)
348 }
349 #[doc = "Prescaler 64"]
350 #[inline(always)]
351 pub fn sixtyfour(self) -> &'a mut crate::W<REG> {
352 self.variant(Prsc::Sixtyfour)
353 }
354 #[doc = "Prescaler 128"]
355 #[inline(always)]
356 pub fn hundredtwentyeight(self) -> &'a mut crate::W<REG> {
357 self.variant(Prsc::Hundredtwentyeight)
358 }
359}
360#[doc = "Compare Mode\n\nValue on reset: 0"]
361#[cfg_attr(feature = "defmt", derive(defmt::Format))]
362#[derive(Clone, Copy, Debug, PartialEq, Eq)]
363pub enum Compmode {
364 #[doc = "0: The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."]
365 EqualTo = 0,
366 #[doc = "1: The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."]
367 EqualToOrGreaterThan = 1,
368}
369impl From<Compmode> for bool {
370 #[inline(always)]
371 fn from(variant: Compmode) -> Self {
372 variant as u8 != 0
373 }
374}
375#[doc = "Field `COMPMODE` reader - Compare Mode"]
376pub type CompmodeR = crate::BitReader<Compmode>;
377impl CompmodeR {
378 #[doc = "Get enumerated values variant"]
379 #[inline(always)]
380 pub const fn variant(&self) -> Compmode {
381 match self.bits {
382 false => Compmode::EqualTo,
383 true => Compmode::EqualToOrGreaterThan,
384 }
385 }
386 #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."]
387 #[inline(always)]
388 pub fn is_equal_to(&self) -> bool {
389 *self == Compmode::EqualTo
390 }
391 #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."]
392 #[inline(always)]
393 pub fn is_equal_to_or_greater_than(&self) -> bool {
394 *self == Compmode::EqualToOrGreaterThan
395 }
396}
397#[doc = "Field `COMPMODE` writer - Compare Mode"]
398pub type CompmodeW<'a, REG> = crate::BitWriter<'a, REG, Compmode>;
399impl<'a, REG> CompmodeW<'a, REG>
400where
401 REG: crate::Writable + crate::RegisterSpec,
402{
403 #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."]
404 #[inline(always)]
405 pub fn equal_to(self) -> &'a mut crate::W<REG> {
406 self.variant(Compmode::EqualTo)
407 }
408 #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."]
409 #[inline(always)]
410 pub fn equal_to_or_greater_than(self) -> &'a mut crate::W<REG> {
411 self.variant(Compmode::EqualToOrGreaterThan)
412 }
413}
414#[doc = "Field `DT` reader - Deadtime"]
415pub type DtR = crate::FieldReader;
416#[doc = "Full Cycle Reload\n\nValue on reset: 1"]
417#[cfg_attr(feature = "defmt", derive(defmt::Format))]
418#[derive(Clone, Copy, Debug, PartialEq, Eq)]
419pub enum Full {
420 #[doc = "0: Full-cycle reloads disabled."]
421 Disabled = 0,
422 #[doc = "1: Full-cycle reloads enabled."]
423 Enabled = 1,
424}
425impl From<Full> for bool {
426 #[inline(always)]
427 fn from(variant: Full) -> Self {
428 variant as u8 != 0
429 }
430}
431#[doc = "Field `FULL` reader - Full Cycle Reload"]
432pub type FullR = crate::BitReader<Full>;
433impl FullR {
434 #[doc = "Get enumerated values variant"]
435 #[inline(always)]
436 pub const fn variant(&self) -> Full {
437 match self.bits {
438 false => Full::Disabled,
439 true => Full::Enabled,
440 }
441 }
442 #[doc = "Full-cycle reloads disabled."]
443 #[inline(always)]
444 pub fn is_disabled(&self) -> bool {
445 *self == Full::Disabled
446 }
447 #[doc = "Full-cycle reloads enabled."]
448 #[inline(always)]
449 pub fn is_enabled(&self) -> bool {
450 *self == Full::Enabled
451 }
452}
453#[doc = "Field `FULL` writer - Full Cycle Reload"]
454pub type FullW<'a, REG> = crate::BitWriter<'a, REG, Full>;
455impl<'a, REG> FullW<'a, REG>
456where
457 REG: crate::Writable + crate::RegisterSpec,
458{
459 #[doc = "Full-cycle reloads disabled."]
460 #[inline(always)]
461 pub fn disabled(self) -> &'a mut crate::W<REG> {
462 self.variant(Full::Disabled)
463 }
464 #[doc = "Full-cycle reloads enabled."]
465 #[inline(always)]
466 pub fn enabled(self) -> &'a mut crate::W<REG> {
467 self.variant(Full::Enabled)
468 }
469}
470#[doc = "Half Cycle Reload\n\nValue on reset: 0"]
471#[cfg_attr(feature = "defmt", derive(defmt::Format))]
472#[derive(Clone, Copy, Debug, PartialEq, Eq)]
473pub enum Half {
474 #[doc = "0: Half-cycle reloads disabled."]
475 Disabled = 0,
476 #[doc = "1: Half-cycle reloads enabled."]
477 Enabled = 1,
478}
479impl From<Half> for bool {
480 #[inline(always)]
481 fn from(variant: Half) -> Self {
482 variant as u8 != 0
483 }
484}
485#[doc = "Field `HALF` reader - Half Cycle Reload"]
486pub type HalfR = crate::BitReader<Half>;
487impl HalfR {
488 #[doc = "Get enumerated values variant"]
489 #[inline(always)]
490 pub const fn variant(&self) -> Half {
491 match self.bits {
492 false => Half::Disabled,
493 true => Half::Enabled,
494 }
495 }
496 #[doc = "Half-cycle reloads disabled."]
497 #[inline(always)]
498 pub fn is_disabled(&self) -> bool {
499 *self == Half::Disabled
500 }
501 #[doc = "Half-cycle reloads enabled."]
502 #[inline(always)]
503 pub fn is_enabled(&self) -> bool {
504 *self == Half::Enabled
505 }
506}
507#[doc = "Field `HALF` writer - Half Cycle Reload"]
508pub type HalfW<'a, REG> = crate::BitWriter<'a, REG, Half>;
509impl<'a, REG> HalfW<'a, REG>
510where
511 REG: crate::Writable + crate::RegisterSpec,
512{
513 #[doc = "Half-cycle reloads disabled."]
514 #[inline(always)]
515 pub fn disabled(self) -> &'a mut crate::W<REG> {
516 self.variant(Half::Disabled)
517 }
518 #[doc = "Half-cycle reloads enabled."]
519 #[inline(always)]
520 pub fn enabled(self) -> &'a mut crate::W<REG> {
521 self.variant(Half::Enabled)
522 }
523}
524#[doc = "Load Frequency\n\nValue on reset: 0"]
525#[cfg_attr(feature = "defmt", derive(defmt::Format))]
526#[derive(Clone, Copy, Debug, PartialEq, Eq)]
527#[repr(u8)]
528pub enum Ldfq {
529 #[doc = "0: Every PWM opportunity"]
530 Everypwm = 0,
531 #[doc = "1: Every 2 PWM opportunities"]
532 Every2pwm = 1,
533 #[doc = "2: Every 3 PWM opportunities"]
534 Every3pwm = 2,
535 #[doc = "3: Every 4 PWM opportunities"]
536 Every4pwm = 3,
537 #[doc = "4: Every 5 PWM opportunities"]
538 Every5pwm = 4,
539 #[doc = "5: Every 6 PWM opportunities"]
540 Every6pwm = 5,
541 #[doc = "6: Every 7 PWM opportunities"]
542 Every7pwm = 6,
543 #[doc = "7: Every 8 PWM opportunities"]
544 Every8pwm = 7,
545 #[doc = "8: Every 9 PWM opportunities"]
546 Every9pwm = 8,
547 #[doc = "9: Every 10 PWM opportunities"]
548 Every10pwm = 9,
549 #[doc = "10: Every 11 PWM opportunities"]
550 Every11pwm = 10,
551 #[doc = "11: Every 12 PWM opportunities"]
552 Every12pwm = 11,
553 #[doc = "12: Every 13 PWM opportunities"]
554 Every13pwm = 12,
555 #[doc = "13: Every 14 PWM opportunities"]
556 Every14pwm = 13,
557 #[doc = "14: Every 15 PWM opportunities"]
558 Every15pwm = 14,
559 #[doc = "15: Every 16 PWM opportunities"]
560 Every16pwm = 15,
561}
562impl From<Ldfq> for u8 {
563 #[inline(always)]
564 fn from(variant: Ldfq) -> Self {
565 variant as _
566 }
567}
568impl crate::FieldSpec for Ldfq {
569 type Ux = u8;
570}
571impl crate::IsEnum for Ldfq {}
572#[doc = "Field `LDFQ` reader - Load Frequency"]
573pub type LdfqR = crate::FieldReader<Ldfq>;
574impl LdfqR {
575 #[doc = "Get enumerated values variant"]
576 #[inline(always)]
577 pub const fn variant(&self) -> Ldfq {
578 match self.bits {
579 0 => Ldfq::Everypwm,
580 1 => Ldfq::Every2pwm,
581 2 => Ldfq::Every3pwm,
582 3 => Ldfq::Every4pwm,
583 4 => Ldfq::Every5pwm,
584 5 => Ldfq::Every6pwm,
585 6 => Ldfq::Every7pwm,
586 7 => Ldfq::Every8pwm,
587 8 => Ldfq::Every9pwm,
588 9 => Ldfq::Every10pwm,
589 10 => Ldfq::Every11pwm,
590 11 => Ldfq::Every12pwm,
591 12 => Ldfq::Every13pwm,
592 13 => Ldfq::Every14pwm,
593 14 => Ldfq::Every15pwm,
594 15 => Ldfq::Every16pwm,
595 _ => unreachable!(),
596 }
597 }
598 #[doc = "Every PWM opportunity"]
599 #[inline(always)]
600 pub fn is_everypwm(&self) -> bool {
601 *self == Ldfq::Everypwm
602 }
603 #[doc = "Every 2 PWM opportunities"]
604 #[inline(always)]
605 pub fn is_every2pwm(&self) -> bool {
606 *self == Ldfq::Every2pwm
607 }
608 #[doc = "Every 3 PWM opportunities"]
609 #[inline(always)]
610 pub fn is_every3pwm(&self) -> bool {
611 *self == Ldfq::Every3pwm
612 }
613 #[doc = "Every 4 PWM opportunities"]
614 #[inline(always)]
615 pub fn is_every4pwm(&self) -> bool {
616 *self == Ldfq::Every4pwm
617 }
618 #[doc = "Every 5 PWM opportunities"]
619 #[inline(always)]
620 pub fn is_every5pwm(&self) -> bool {
621 *self == Ldfq::Every5pwm
622 }
623 #[doc = "Every 6 PWM opportunities"]
624 #[inline(always)]
625 pub fn is_every6pwm(&self) -> bool {
626 *self == Ldfq::Every6pwm
627 }
628 #[doc = "Every 7 PWM opportunities"]
629 #[inline(always)]
630 pub fn is_every7pwm(&self) -> bool {
631 *self == Ldfq::Every7pwm
632 }
633 #[doc = "Every 8 PWM opportunities"]
634 #[inline(always)]
635 pub fn is_every8pwm(&self) -> bool {
636 *self == Ldfq::Every8pwm
637 }
638 #[doc = "Every 9 PWM opportunities"]
639 #[inline(always)]
640 pub fn is_every9pwm(&self) -> bool {
641 *self == Ldfq::Every9pwm
642 }
643 #[doc = "Every 10 PWM opportunities"]
644 #[inline(always)]
645 pub fn is_every10pwm(&self) -> bool {
646 *self == Ldfq::Every10pwm
647 }
648 #[doc = "Every 11 PWM opportunities"]
649 #[inline(always)]
650 pub fn is_every11pwm(&self) -> bool {
651 *self == Ldfq::Every11pwm
652 }
653 #[doc = "Every 12 PWM opportunities"]
654 #[inline(always)]
655 pub fn is_every12pwm(&self) -> bool {
656 *self == Ldfq::Every12pwm
657 }
658 #[doc = "Every 13 PWM opportunities"]
659 #[inline(always)]
660 pub fn is_every13pwm(&self) -> bool {
661 *self == Ldfq::Every13pwm
662 }
663 #[doc = "Every 14 PWM opportunities"]
664 #[inline(always)]
665 pub fn is_every14pwm(&self) -> bool {
666 *self == Ldfq::Every14pwm
667 }
668 #[doc = "Every 15 PWM opportunities"]
669 #[inline(always)]
670 pub fn is_every15pwm(&self) -> bool {
671 *self == Ldfq::Every15pwm
672 }
673 #[doc = "Every 16 PWM opportunities"]
674 #[inline(always)]
675 pub fn is_every16pwm(&self) -> bool {
676 *self == Ldfq::Every16pwm
677 }
678}
679#[doc = "Field `LDFQ` writer - Load Frequency"]
680pub type LdfqW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ldfq, crate::Safe>;
681impl<'a, REG> LdfqW<'a, REG>
682where
683 REG: crate::Writable + crate::RegisterSpec,
684 REG::Ux: From<u8>,
685{
686 #[doc = "Every PWM opportunity"]
687 #[inline(always)]
688 pub fn everypwm(self) -> &'a mut crate::W<REG> {
689 self.variant(Ldfq::Everypwm)
690 }
691 #[doc = "Every 2 PWM opportunities"]
692 #[inline(always)]
693 pub fn every2pwm(self) -> &'a mut crate::W<REG> {
694 self.variant(Ldfq::Every2pwm)
695 }
696 #[doc = "Every 3 PWM opportunities"]
697 #[inline(always)]
698 pub fn every3pwm(self) -> &'a mut crate::W<REG> {
699 self.variant(Ldfq::Every3pwm)
700 }
701 #[doc = "Every 4 PWM opportunities"]
702 #[inline(always)]
703 pub fn every4pwm(self) -> &'a mut crate::W<REG> {
704 self.variant(Ldfq::Every4pwm)
705 }
706 #[doc = "Every 5 PWM opportunities"]
707 #[inline(always)]
708 pub fn every5pwm(self) -> &'a mut crate::W<REG> {
709 self.variant(Ldfq::Every5pwm)
710 }
711 #[doc = "Every 6 PWM opportunities"]
712 #[inline(always)]
713 pub fn every6pwm(self) -> &'a mut crate::W<REG> {
714 self.variant(Ldfq::Every6pwm)
715 }
716 #[doc = "Every 7 PWM opportunities"]
717 #[inline(always)]
718 pub fn every7pwm(self) -> &'a mut crate::W<REG> {
719 self.variant(Ldfq::Every7pwm)
720 }
721 #[doc = "Every 8 PWM opportunities"]
722 #[inline(always)]
723 pub fn every8pwm(self) -> &'a mut crate::W<REG> {
724 self.variant(Ldfq::Every8pwm)
725 }
726 #[doc = "Every 9 PWM opportunities"]
727 #[inline(always)]
728 pub fn every9pwm(self) -> &'a mut crate::W<REG> {
729 self.variant(Ldfq::Every9pwm)
730 }
731 #[doc = "Every 10 PWM opportunities"]
732 #[inline(always)]
733 pub fn every10pwm(self) -> &'a mut crate::W<REG> {
734 self.variant(Ldfq::Every10pwm)
735 }
736 #[doc = "Every 11 PWM opportunities"]
737 #[inline(always)]
738 pub fn every11pwm(self) -> &'a mut crate::W<REG> {
739 self.variant(Ldfq::Every11pwm)
740 }
741 #[doc = "Every 12 PWM opportunities"]
742 #[inline(always)]
743 pub fn every12pwm(self) -> &'a mut crate::W<REG> {
744 self.variant(Ldfq::Every12pwm)
745 }
746 #[doc = "Every 13 PWM opportunities"]
747 #[inline(always)]
748 pub fn every13pwm(self) -> &'a mut crate::W<REG> {
749 self.variant(Ldfq::Every13pwm)
750 }
751 #[doc = "Every 14 PWM opportunities"]
752 #[inline(always)]
753 pub fn every14pwm(self) -> &'a mut crate::W<REG> {
754 self.variant(Ldfq::Every14pwm)
755 }
756 #[doc = "Every 15 PWM opportunities"]
757 #[inline(always)]
758 pub fn every15pwm(self) -> &'a mut crate::W<REG> {
759 self.variant(Ldfq::Every15pwm)
760 }
761 #[doc = "Every 16 PWM opportunities"]
762 #[inline(always)]
763 pub fn every16pwm(self) -> &'a mut crate::W<REG> {
764 self.variant(Ldfq::Every16pwm)
765 }
766}
767impl R {
768 #[doc = "Bit 0 - Double Switching Enable"]
769 #[inline(always)]
770 pub fn dblen(&self) -> DblenR {
771 DblenR::new((self.bits & 1) != 0)
772 }
773 #[doc = "Bit 1 - PWM_X Double Switching Enable"]
774 #[inline(always)]
775 pub fn dblx(&self) -> DblxR {
776 DblxR::new(((self.bits >> 1) & 1) != 0)
777 }
778 #[doc = "Bit 2 - Load Mode Select"]
779 #[inline(always)]
780 pub fn ldmod(&self) -> LdmodR {
781 LdmodR::new(((self.bits >> 2) & 1) != 0)
782 }
783 #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"]
784 #[inline(always)]
785 pub fn split(&self) -> SplitR {
786 SplitR::new(((self.bits >> 3) & 1) != 0)
787 }
788 #[doc = "Bits 4:6 - Prescaler"]
789 #[inline(always)]
790 pub fn prsc(&self) -> PrscR {
791 PrscR::new(((self.bits >> 4) & 7) as u8)
792 }
793 #[doc = "Bit 7 - Compare Mode"]
794 #[inline(always)]
795 pub fn compmode(&self) -> CompmodeR {
796 CompmodeR::new(((self.bits >> 7) & 1) != 0)
797 }
798 #[doc = "Bits 8:9 - Deadtime"]
799 #[inline(always)]
800 pub fn dt(&self) -> DtR {
801 DtR::new(((self.bits >> 8) & 3) as u8)
802 }
803 #[doc = "Bit 10 - Full Cycle Reload"]
804 #[inline(always)]
805 pub fn full(&self) -> FullR {
806 FullR::new(((self.bits >> 10) & 1) != 0)
807 }
808 #[doc = "Bit 11 - Half Cycle Reload"]
809 #[inline(always)]
810 pub fn half(&self) -> HalfR {
811 HalfR::new(((self.bits >> 11) & 1) != 0)
812 }
813 #[doc = "Bits 12:15 - Load Frequency"]
814 #[inline(always)]
815 pub fn ldfq(&self) -> LdfqR {
816 LdfqR::new(((self.bits >> 12) & 0x0f) as u8)
817 }
818}
819#[cfg(feature = "debug")]
820impl core::fmt::Debug for R {
821 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
822 f.debug_struct("SM0CTRL")
823 .field("dblen", &self.dblen())
824 .field("dblx", &self.dblx())
825 .field("ldmod", &self.ldmod())
826 .field("split", &self.split())
827 .field("prsc", &self.prsc())
828 .field("compmode", &self.compmode())
829 .field("dt", &self.dt())
830 .field("full", &self.full())
831 .field("half", &self.half())
832 .field("ldfq", &self.ldfq())
833 .finish()
834 }
835}
836impl W {
837 #[doc = "Bit 0 - Double Switching Enable"]
838 #[inline(always)]
839 pub fn dblen(&mut self) -> DblenW<'_, Sm0ctrlSpec> {
840 DblenW::new(self, 0)
841 }
842 #[doc = "Bit 1 - PWM_X Double Switching Enable"]
843 #[inline(always)]
844 pub fn dblx(&mut self) -> DblxW<'_, Sm0ctrlSpec> {
845 DblxW::new(self, 1)
846 }
847 #[doc = "Bit 2 - Load Mode Select"]
848 #[inline(always)]
849 pub fn ldmod(&mut self) -> LdmodW<'_, Sm0ctrlSpec> {
850 LdmodW::new(self, 2)
851 }
852 #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"]
853 #[inline(always)]
854 pub fn split(&mut self) -> SplitW<'_, Sm0ctrlSpec> {
855 SplitW::new(self, 3)
856 }
857 #[doc = "Bits 4:6 - Prescaler"]
858 #[inline(always)]
859 pub fn prsc(&mut self) -> PrscW<'_, Sm0ctrlSpec> {
860 PrscW::new(self, 4)
861 }
862 #[doc = "Bit 7 - Compare Mode"]
863 #[inline(always)]
864 pub fn compmode(&mut self) -> CompmodeW<'_, Sm0ctrlSpec> {
865 CompmodeW::new(self, 7)
866 }
867 #[doc = "Bit 10 - Full Cycle Reload"]
868 #[inline(always)]
869 pub fn full(&mut self) -> FullW<'_, Sm0ctrlSpec> {
870 FullW::new(self, 10)
871 }
872 #[doc = "Bit 11 - Half Cycle Reload"]
873 #[inline(always)]
874 pub fn half(&mut self) -> HalfW<'_, Sm0ctrlSpec> {
875 HalfW::new(self, 11)
876 }
877 #[doc = "Bits 12:15 - Load Frequency"]
878 #[inline(always)]
879 pub fn ldfq(&mut self) -> LdfqW<'_, Sm0ctrlSpec> {
880 LdfqW::new(self, 12)
881 }
882}
883#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
884pub struct Sm0ctrlSpec;
885impl crate::RegisterSpec for Sm0ctrlSpec {
886 type Ux = u16;
887}
888#[doc = "`read()` method returns [`sm0ctrl::R`](R) reader structure"]
889impl crate::Readable for Sm0ctrlSpec {}
890#[doc = "`write(|w| ..)` method takes [`sm0ctrl::W`](W) writer structure"]
891impl crate::Writable for Sm0ctrlSpec {
892 type Safety = crate::Unsafe;
893}
894#[doc = "`reset()` method sets SM0CTRL to value 0x0400"]
895impl crate::Resettable for Sm0ctrlSpec {
896 const RESET_VALUE: u16 = 0x0400;
897}