1#![doc = "Peripheral access API for MCXA256 microcontrollers (generated using svd2rust v0.37.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
2#![allow(non_camel_case_types)]
3#![allow(non_snake_case)]
4#![no_std]
5#![cfg_attr(docsrs, feature(doc_cfg))]
6#[doc = r"Number available in the NVIC for configuring priority"]
7pub const NVIC_PRIO_BITS: u8 = 3;
8#[cfg(feature = "rt")]
9pub use self::Interrupt as interrupt;
10#[cfg(feature = "rt")]
11pub use cortex_m_rt::interrupt;
12#[allow(unused_imports)]
13use generic::*;
14#[doc = r"Common register and bit access and modify traits"]
15pub mod generic;
16#[cfg(feature = "rt")]
17extern "C" {
18 fn Reserved16();
19 fn CMC();
20 fn DMA_CH0();
21 fn DMA_CH1();
22 fn DMA_CH2();
23 fn DMA_CH3();
24 fn DMA_CH4();
25 fn DMA_CH5();
26 fn DMA_CH6();
27 fn DMA_CH7();
28 fn ERM0_SINGLE_BIT();
29 fn ERM0_MULTI_BIT();
30 fn FMU0();
31 fn GLIKEY0();
32 fn MBC0();
33 fn SCG0();
34 fn SPC0();
35 fn TDET();
36 fn WUU0();
37 fn CAN0();
38 fn CAN1();
39 fn FLEXIO();
40 fn I3C0();
41 fn LPI2C0();
42 fn LPI2C1();
43 fn LPSPI0();
44 fn LPSPI1();
45 fn LPUART0();
46 fn LPUART1();
47 fn LPUART2();
48 fn LPUART3();
49 fn LPUART4();
50 fn USB0();
51 fn CDOG0();
52 fn CTIMER0();
53 fn CTIMER1();
54 fn CTIMER2();
55 fn CTIMER3();
56 fn CTIMER4();
57 fn FLEXPWM0_RELOAD_ERROR();
58 fn FLEXPWM0_FAULT();
59 fn FLEXPWM0_SUBMODULE0();
60 fn FLEXPWM0_SUBMODULE1();
61 fn FLEXPWM0_SUBMODULE2();
62 fn FLEXPWM0_SUBMODULE3();
63 fn EQDC0_COMPARE();
64 fn EQDC0_HOME();
65 fn EQDC0_WATCHDOG();
66 fn EQDC0_INDEX();
67 fn FREQME0();
68 fn LPTMR0();
69 fn OS_EVENT();
70 fn WAKETIMER0();
71 fn UTICK0();
72 fn WWDT0();
73 fn ADC0();
74 fn ADC1();
75 fn CMP0();
76 fn CMP1();
77 fn CMP2();
78 fn DAC0();
79 fn GPIO0();
80 fn GPIO1();
81 fn GPIO2();
82 fn GPIO3();
83 fn GPIO4();
84 fn LPI2C2();
85 fn LPI2C3();
86 fn FLEXPWM1_RELOAD_ERROR();
87 fn FLEXPWM1_FAULT();
88 fn FLEXPWM1_SUBMODULE0();
89 fn FLEXPWM1_SUBMODULE1();
90 fn FLEXPWM1_SUBMODULE2();
91 fn FLEXPWM1_SUBMODULE3();
92 fn EQDC1_COMPARE();
93 fn EQDC1_HOME();
94 fn EQDC1_WATCHDOG();
95 fn EQDC1_INDEX();
96 fn LPUART5();
97 fn MAU();
98 fn SMARTDMA();
99 fn CDOG1();
100 fn PKC();
101 fn SGI();
102 fn TRNG0();
103 fn ADC2();
104 fn ADC3();
105 fn RTC();
106 fn RTC_1HZ();
107 fn SLCD();
108}
109#[doc(hidden)]
110#[repr(C)]
111pub union Vector {
112 _handler: unsafe extern "C" fn(),
113 _reserved: u32,
114}
115#[cfg(feature = "rt")]
116#[doc(hidden)]
117#[link_section = ".vector_table.interrupts"]
118#[no_mangle]
119pub static __INTERRUPTS: [Vector; 122] = [
120 Vector { _handler: Reserved16 },
121 Vector { _handler: CMC },
122 Vector { _handler: DMA_CH0 },
123 Vector { _handler: DMA_CH1 },
124 Vector { _handler: DMA_CH2 },
125 Vector { _handler: DMA_CH3 },
126 Vector { _handler: DMA_CH4 },
127 Vector { _handler: DMA_CH5 },
128 Vector { _handler: DMA_CH6 },
129 Vector { _handler: DMA_CH7 },
130 Vector {
131 _handler: ERM0_SINGLE_BIT,
132 },
133 Vector {
134 _handler: ERM0_MULTI_BIT,
135 },
136 Vector { _handler: FMU0 },
137 Vector { _handler: GLIKEY0 },
138 Vector { _handler: MBC0 },
139 Vector { _handler: SCG0 },
140 Vector { _handler: SPC0 },
141 Vector { _handler: TDET },
142 Vector { _handler: WUU0 },
143 Vector { _handler: CAN0 },
144 Vector { _handler: CAN1 },
145 Vector { _reserved: 0 },
146 Vector { _reserved: 0 },
147 Vector { _handler: FLEXIO },
148 Vector { _handler: I3C0 },
149 Vector { _reserved: 0 },
150 Vector { _handler: LPI2C0 },
151 Vector { _handler: LPI2C1 },
152 Vector { _handler: LPSPI0 },
153 Vector { _handler: LPSPI1 },
154 Vector { _reserved: 0 },
155 Vector { _handler: LPUART0 },
156 Vector { _handler: LPUART1 },
157 Vector { _handler: LPUART2 },
158 Vector { _handler: LPUART3 },
159 Vector { _handler: LPUART4 },
160 Vector { _handler: USB0 },
161 Vector { _reserved: 0 },
162 Vector { _handler: CDOG0 },
163 Vector { _handler: CTIMER0 },
164 Vector { _handler: CTIMER1 },
165 Vector { _handler: CTIMER2 },
166 Vector { _handler: CTIMER3 },
167 Vector { _handler: CTIMER4 },
168 Vector {
169 _handler: FLEXPWM0_RELOAD_ERROR,
170 },
171 Vector {
172 _handler: FLEXPWM0_FAULT,
173 },
174 Vector {
175 _handler: FLEXPWM0_SUBMODULE0,
176 },
177 Vector {
178 _handler: FLEXPWM0_SUBMODULE1,
179 },
180 Vector {
181 _handler: FLEXPWM0_SUBMODULE2,
182 },
183 Vector {
184 _handler: FLEXPWM0_SUBMODULE3,
185 },
186 Vector {
187 _handler: EQDC0_COMPARE,
188 },
189 Vector { _handler: EQDC0_HOME },
190 Vector {
191 _handler: EQDC0_WATCHDOG,
192 },
193 Vector { _handler: EQDC0_INDEX },
194 Vector { _handler: FREQME0 },
195 Vector { _handler: LPTMR0 },
196 Vector { _reserved: 0 },
197 Vector { _handler: OS_EVENT },
198 Vector { _handler: WAKETIMER0 },
199 Vector { _handler: UTICK0 },
200 Vector { _handler: WWDT0 },
201 Vector { _reserved: 0 },
202 Vector { _handler: ADC0 },
203 Vector { _handler: ADC1 },
204 Vector { _handler: CMP0 },
205 Vector { _handler: CMP1 },
206 Vector { _handler: CMP2 },
207 Vector { _handler: DAC0 },
208 Vector { _reserved: 0 },
209 Vector { _reserved: 0 },
210 Vector { _reserved: 0 },
211 Vector { _handler: GPIO0 },
212 Vector { _handler: GPIO1 },
213 Vector { _handler: GPIO2 },
214 Vector { _handler: GPIO3 },
215 Vector { _handler: GPIO4 },
216 Vector { _reserved: 0 },
217 Vector { _handler: LPI2C2 },
218 Vector { _handler: LPI2C3 },
219 Vector {
220 _handler: FLEXPWM1_RELOAD_ERROR,
221 },
222 Vector {
223 _handler: FLEXPWM1_FAULT,
224 },
225 Vector {
226 _handler: FLEXPWM1_SUBMODULE0,
227 },
228 Vector {
229 _handler: FLEXPWM1_SUBMODULE1,
230 },
231 Vector {
232 _handler: FLEXPWM1_SUBMODULE2,
233 },
234 Vector {
235 _handler: FLEXPWM1_SUBMODULE3,
236 },
237 Vector {
238 _handler: EQDC1_COMPARE,
239 },
240 Vector { _handler: EQDC1_HOME },
241 Vector {
242 _handler: EQDC1_WATCHDOG,
243 },
244 Vector { _handler: EQDC1_INDEX },
245 Vector { _reserved: 0 },
246 Vector { _reserved: 0 },
247 Vector { _reserved: 0 },
248 Vector { _reserved: 0 },
249 Vector { _reserved: 0 },
250 Vector { _reserved: 0 },
251 Vector { _handler: LPUART5 },
252 Vector { _reserved: 0 },
253 Vector { _reserved: 0 },
254 Vector { _reserved: 0 },
255 Vector { _reserved: 0 },
256 Vector { _reserved: 0 },
257 Vector { _reserved: 0 },
258 Vector { _reserved: 0 },
259 Vector { _reserved: 0 },
260 Vector { _reserved: 0 },
261 Vector { _reserved: 0 },
262 Vector { _reserved: 0 },
263 Vector { _handler: MAU },
264 Vector { _handler: SMARTDMA },
265 Vector { _handler: CDOG1 },
266 Vector { _handler: PKC },
267 Vector { _handler: SGI },
268 Vector { _reserved: 0 },
269 Vector { _handler: TRNG0 },
270 Vector { _reserved: 0 },
271 Vector { _reserved: 0 },
272 Vector { _handler: ADC2 },
273 Vector { _handler: ADC3 },
274 Vector { _reserved: 0 },
275 Vector { _handler: RTC },
276 Vector { _handler: RTC_1HZ },
277 Vector { _handler: SLCD },
278];
279#[doc = r"Enumeration of all the interrupts."]
280#[cfg_attr(feature = "defmt", derive(defmt::Format))]
281#[derive(Copy, Clone, Debug, PartialEq, Eq)]
282#[repr(u16)]
283pub enum Interrupt {
284 #[doc = "0 - Reserved16"]
285 Reserved16 = 0,
286 #[doc = "1 - CMC"]
287 CMC = 1,
288 #[doc = "2 - DMA_CH0"]
289 DMA_CH0 = 2,
290 #[doc = "3 - DMA_CH1"]
291 DMA_CH1 = 3,
292 #[doc = "4 - DMA_CH2"]
293 DMA_CH2 = 4,
294 #[doc = "5 - DMA_CH3"]
295 DMA_CH3 = 5,
296 #[doc = "6 - DMA_CH4"]
297 DMA_CH4 = 6,
298 #[doc = "7 - DMA_CH5"]
299 DMA_CH5 = 7,
300 #[doc = "8 - DMA_CH6"]
301 DMA_CH6 = 8,
302 #[doc = "9 - DMA_CH7"]
303 DMA_CH7 = 9,
304 #[doc = "10 - ERM0_SINGLE_BIT"]
305 ERM0_SINGLE_BIT = 10,
306 #[doc = "11 - ERM0_MULTI_BIT"]
307 ERM0_MULTI_BIT = 11,
308 #[doc = "12 - FMU0"]
309 FMU0 = 12,
310 #[doc = "13 - GLIKEY0"]
311 GLIKEY0 = 13,
312 #[doc = "14 - MBC0"]
313 MBC0 = 14,
314 #[doc = "15 - SCG0"]
315 SCG0 = 15,
316 #[doc = "16 - SPC0"]
317 SPC0 = 16,
318 #[doc = "17 - TDET"]
319 TDET = 17,
320 #[doc = "18 - WUU0"]
321 WUU0 = 18,
322 #[doc = "19 - CAN0"]
323 CAN0 = 19,
324 #[doc = "20 - CAN1"]
325 CAN1 = 20,
326 #[doc = "23 - FLEXIO"]
327 FLEXIO = 23,
328 #[doc = "24 - I3C0"]
329 I3C0 = 24,
330 #[doc = "26 - LPI2C0"]
331 LPI2C0 = 26,
332 #[doc = "27 - LPI2C1"]
333 LPI2C1 = 27,
334 #[doc = "28 - LPSPI0"]
335 LPSPI0 = 28,
336 #[doc = "29 - LPSPI1"]
337 LPSPI1 = 29,
338 #[doc = "31 - LPUART0"]
339 LPUART0 = 31,
340 #[doc = "32 - LPUART1"]
341 LPUART1 = 32,
342 #[doc = "33 - LPUART2"]
343 LPUART2 = 33,
344 #[doc = "34 - LPUART3"]
345 LPUART3 = 34,
346 #[doc = "35 - LPUART4"]
347 LPUART4 = 35,
348 #[doc = "36 - USB0"]
349 USB0 = 36,
350 #[doc = "38 - CDOG0"]
351 CDOG0 = 38,
352 #[doc = "39 - CTIMER0"]
353 CTIMER0 = 39,
354 #[doc = "40 - CTIMER1"]
355 CTIMER1 = 40,
356 #[doc = "41 - CTIMER2"]
357 CTIMER2 = 41,
358 #[doc = "42 - CTIMER3"]
359 CTIMER3 = 42,
360 #[doc = "43 - CTIMER4"]
361 CTIMER4 = 43,
362 #[doc = "44 - FLEXPWM0_RELOAD_ERROR"]
363 FLEXPWM0_RELOAD_ERROR = 44,
364 #[doc = "45 - FLEXPWM0_FAULT"]
365 FLEXPWM0_FAULT = 45,
366 #[doc = "46 - FLEXPWM0_SUBMODULE0"]
367 FLEXPWM0_SUBMODULE0 = 46,
368 #[doc = "47 - FLEXPWM0_SUBMODULE1"]
369 FLEXPWM0_SUBMODULE1 = 47,
370 #[doc = "48 - FLEXPWM0_SUBMODULE2"]
371 FLEXPWM0_SUBMODULE2 = 48,
372 #[doc = "49 - FLEXPWM0_SUBMODULE3"]
373 FLEXPWM0_SUBMODULE3 = 49,
374 #[doc = "50 - EQDC0_COMPARE"]
375 EQDC0_COMPARE = 50,
376 #[doc = "51 - EQDC0_HOME"]
377 EQDC0_HOME = 51,
378 #[doc = "52 - EQDC0_WATCHDOG"]
379 EQDC0_WATCHDOG = 52,
380 #[doc = "53 - EQDC0_INDEX"]
381 EQDC0_INDEX = 53,
382 #[doc = "54 - FREQME0"]
383 FREQME0 = 54,
384 #[doc = "55 - LPTMR0"]
385 LPTMR0 = 55,
386 #[doc = "57 - OS_EVENT"]
387 OS_EVENT = 57,
388 #[doc = "58 - WAKETIMER0"]
389 WAKETIMER0 = 58,
390 #[doc = "59 - UTICK0"]
391 UTICK0 = 59,
392 #[doc = "60 - WWDT0"]
393 WWDT0 = 60,
394 #[doc = "62 - ADC0"]
395 ADC0 = 62,
396 #[doc = "63 - ADC1"]
397 ADC1 = 63,
398 #[doc = "64 - CMP0"]
399 CMP0 = 64,
400 #[doc = "65 - CMP1"]
401 CMP1 = 65,
402 #[doc = "66 - CMP2"]
403 CMP2 = 66,
404 #[doc = "67 - DAC0"]
405 DAC0 = 67,
406 #[doc = "71 - GPIO0"]
407 GPIO0 = 71,
408 #[doc = "72 - GPIO1"]
409 GPIO1 = 72,
410 #[doc = "73 - GPIO2"]
411 GPIO2 = 73,
412 #[doc = "74 - GPIO3"]
413 GPIO3 = 74,
414 #[doc = "75 - GPIO4"]
415 GPIO4 = 75,
416 #[doc = "77 - LPI2C2"]
417 LPI2C2 = 77,
418 #[doc = "78 - LPI2C3"]
419 LPI2C3 = 78,
420 #[doc = "79 - FLEXPWM1_RELOAD_ERROR"]
421 FLEXPWM1_RELOAD_ERROR = 79,
422 #[doc = "80 - FLEXPWM1_FAULT"]
423 FLEXPWM1_FAULT = 80,
424 #[doc = "81 - FLEXPWM1_SUBMODULE0"]
425 FLEXPWM1_SUBMODULE0 = 81,
426 #[doc = "82 - FLEXPWM1_SUBMODULE1"]
427 FLEXPWM1_SUBMODULE1 = 82,
428 #[doc = "83 - FLEXPWM1_SUBMODULE2"]
429 FLEXPWM1_SUBMODULE2 = 83,
430 #[doc = "84 - FLEXPWM1_SUBMODULE3"]
431 FLEXPWM1_SUBMODULE3 = 84,
432 #[doc = "85 - EQDC1_COMPARE"]
433 EQDC1_COMPARE = 85,
434 #[doc = "86 - EQDC1_HOME"]
435 EQDC1_HOME = 86,
436 #[doc = "87 - EQDC1_WATCHDOG"]
437 EQDC1_WATCHDOG = 87,
438 #[doc = "88 - EQDC1_INDEX"]
439 EQDC1_INDEX = 88,
440 #[doc = "95 - LPUART5"]
441 LPUART5 = 95,
442 #[doc = "107 - MAU"]
443 MAU = 107,
444 #[doc = "108 - SMARTDMA"]
445 SMARTDMA = 108,
446 #[doc = "109 - CDOG1"]
447 CDOG1 = 109,
448 #[doc = "110 - PKC"]
449 PKC = 110,
450 #[doc = "111 - SGI"]
451 SGI = 111,
452 #[doc = "113 - TRNG0"]
453 TRNG0 = 113,
454 #[doc = "116 - ADC2"]
455 ADC2 = 116,
456 #[doc = "117 - ADC3"]
457 ADC3 = 117,
458 #[doc = "119 - RTC"]
459 RTC = 119,
460 #[doc = "120 - RTC_1HZ"]
461 RTC_1HZ = 120,
462 #[doc = "121 - SLCD"]
463 SLCD = 121,
464}
465unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
466 #[inline(always)]
467 fn number(self) -> u16 {
468 self as u16
469 }
470}
471#[doc = "INPUTMUX"]
472pub type Inputmux0 = crate::Periph<inputmux0::RegisterBlock, 0x4000_1000>;
473impl core::fmt::Debug for Inputmux0 {
474 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
475 f.debug_struct("Inputmux0").finish()
476 }
477}
478#[doc = "INPUTMUX"]
479pub mod inputmux0;
480#[doc = "Improved Inter-Integrated Circuit"]
481pub type I3c0 = crate::Periph<i3c0::RegisterBlock, 0x4000_2000>;
482impl core::fmt::Debug for I3c0 {
483 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
484 f.debug_struct("I3c0").finish()
485 }
486}
487#[doc = "Improved Inter-Integrated Circuit"]
488pub mod i3c0;
489#[doc = "Standard Counter or Timer"]
490pub type Ctimer0 = crate::Periph<ctimer0::RegisterBlock, 0x4000_4000>;
491impl core::fmt::Debug for Ctimer0 {
492 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
493 f.debug_struct("Ctimer0").finish()
494 }
495}
496#[doc = "Standard Counter or Timer"]
497pub mod ctimer0;
498#[doc = "Standard Counter or Timer"]
499pub type Ctimer1 = crate::Periph<ctimer0::RegisterBlock, 0x4000_5000>;
500impl core::fmt::Debug for Ctimer1 {
501 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
502 f.debug_struct("Ctimer1").finish()
503 }
504}
505#[doc = "Standard Counter or Timer"]
506pub use self::ctimer0 as ctimer1;
507#[doc = "Standard Counter or Timer"]
508pub type Ctimer2 = crate::Periph<ctimer0::RegisterBlock, 0x4000_6000>;
509impl core::fmt::Debug for Ctimer2 {
510 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
511 f.debug_struct("Ctimer2").finish()
512 }
513}
514#[doc = "Standard Counter or Timer"]
515pub use self::ctimer0 as ctimer2;
516#[doc = "Standard Counter or Timer"]
517pub type Ctimer3 = crate::Periph<ctimer0::RegisterBlock, 0x4000_7000>;
518impl core::fmt::Debug for Ctimer3 {
519 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
520 f.debug_struct("Ctimer3").finish()
521 }
522}
523#[doc = "Standard Counter or Timer"]
524pub use self::ctimer0 as ctimer3;
525#[doc = "Standard Counter or Timer"]
526pub type Ctimer4 = crate::Periph<ctimer0::RegisterBlock, 0x4000_8000>;
527impl core::fmt::Debug for Ctimer4 {
528 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
529 f.debug_struct("Ctimer4").finish()
530 }
531}
532#[doc = "Standard Counter or Timer"]
533pub use self::ctimer0 as ctimer4;
534#[doc = "FREQME"]
535pub type Freqme0 = crate::Periph<freqme0::RegisterBlock, 0x4000_9000>;
536impl core::fmt::Debug for Freqme0 {
537 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
538 f.debug_struct("Freqme0").finish()
539 }
540}
541#[doc = "FREQME"]
542pub mod freqme0;
543#[doc = "UTICK"]
544pub type Utick0 = crate::Periph<utick0::RegisterBlock, 0x4000_b000>;
545impl core::fmt::Debug for Utick0 {
546 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
547 f.debug_struct("Utick0").finish()
548 }
549}
550#[doc = "UTICK"]
551pub mod utick0;
552#[doc = "WWDT"]
553pub type Wwdt0 = crate::Periph<wwdt0::RegisterBlock, 0x4000_c000>;
554impl core::fmt::Debug for Wwdt0 {
555 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
556 f.debug_struct("Wwdt0").finish()
557 }
558}
559#[doc = "WWDT"]
560pub mod wwdt0;
561#[doc = "Smart DMA Controller"]
562pub type Smartdma0 = crate::Periph<smartdma0::RegisterBlock, 0x4000_e000>;
563impl core::fmt::Debug for Smartdma0 {
564 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
565 f.debug_struct("Smartdma0").finish()
566 }
567}
568#[doc = "Smart DMA Controller"]
569pub mod smartdma0;
570#[doc = "DMA MP"]
571pub type Dma0 = crate::Periph<dma0::RegisterBlock, 0x4008_0000>;
572impl core::fmt::Debug for Dma0 {
573 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
574 f.debug_struct("Dma0").finish()
575 }
576}
577#[doc = "DMA MP"]
578pub mod dma0;
579#[doc = "DMA TCD"]
580pub type Edma0Tcd0 = crate::Periph<edma_0_tcd0::RegisterBlock, 0x4008_1000>;
581impl core::fmt::Debug for Edma0Tcd0 {
582 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
583 f.debug_struct("Edma0Tcd0").finish()
584 }
585}
586#[doc = "DMA TCD"]
587pub mod edma_0_tcd0;
588#[doc = "AOI"]
589pub type Aoi0 = crate::Periph<aoi0::RegisterBlock, 0x4008_9000>;
590impl core::fmt::Debug for Aoi0 {
591 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
592 f.debug_struct("Aoi0").finish()
593 }
594}
595#[doc = "AOI"]
596pub mod aoi0;
597#[doc = "AOI"]
598pub type Aoi1 = crate::Periph<aoi0::RegisterBlock, 0x4009_7000>;
599impl core::fmt::Debug for Aoi1 {
600 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
601 f.debug_struct("Aoi1").finish()
602 }
603}
604#[doc = "AOI"]
605pub use self::aoi0 as aoi1;
606#[doc = "CRC"]
607pub type Crc0 = crate::Periph<crc0::RegisterBlock, 0x4008_a000>;
608impl core::fmt::Debug for Crc0 {
609 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
610 f.debug_struct("Crc0").finish()
611 }
612}
613#[doc = "CRC"]
614pub mod crc0;
615#[doc = "CMC"]
616pub type Cmc = crate::Periph<cmc::RegisterBlock, 0x4008_b000>;
617impl core::fmt::Debug for Cmc {
618 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
619 f.debug_struct("Cmc").finish()
620 }
621}
622#[doc = "CMC"]
623pub mod cmc;
624#[doc = "Error Injection Module"]
625pub type Eim0 = crate::Periph<eim0::RegisterBlock, 0x4008_c000>;
626impl core::fmt::Debug for Eim0 {
627 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
628 f.debug_struct("Eim0").finish()
629 }
630}
631#[doc = "Error Injection Module"]
632pub mod eim0;
633#[doc = "Error Reporting Module"]
634pub type Erm0 = crate::Periph<erm0::RegisterBlock, 0x4008_d000>;
635impl core::fmt::Debug for Erm0 {
636 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
637 f.debug_struct("Erm0").finish()
638 }
639}
640#[doc = "Error Reporting Module"]
641pub mod erm0;
642#[doc = "TRDC"]
643pub type Mbc0 = crate::Periph<mbc0::RegisterBlock, 0x4008_e000>;
644impl core::fmt::Debug for Mbc0 {
645 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
646 f.debug_struct("Mbc0").finish()
647 }
648}
649#[doc = "TRDC"]
650pub mod mbc0;
651#[doc = "System Clock Generator"]
652pub type Scg0 = crate::Periph<scg0::RegisterBlock, 0x4008_f000>;
653impl core::fmt::Debug for Scg0 {
654 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
655 f.debug_struct("Scg0").finish()
656 }
657}
658#[doc = "System Clock Generator"]
659pub mod scg0;
660#[doc = "SPC"]
661pub type Spc0 = crate::Periph<spc0::RegisterBlock, 0x4009_0000>;
662impl core::fmt::Debug for Spc0 {
663 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
664 f.debug_struct("Spc0").finish()
665 }
666}
667#[doc = "SPC"]
668pub mod spc0;
669#[doc = "MRCC"]
670pub type Mrcc0 = crate::Periph<mrcc0::RegisterBlock, 0x4009_1000>;
671impl core::fmt::Debug for Mrcc0 {
672 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
673 f.debug_struct("Mrcc0").finish()
674 }
675}
676#[doc = "MRCC"]
677pub mod mrcc0;
678#[doc = "SYSCON"]
679pub type Syscon = crate::Periph<syscon::RegisterBlock, 0x4009_1000>;
680impl core::fmt::Debug for Syscon {
681 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
682 f.debug_struct("Syscon").finish()
683 }
684}
685#[doc = "SYSCON"]
686pub mod syscon;
687#[doc = "GLIKEY"]
688pub type Glikey0 = crate::Periph<glikey0::RegisterBlock, 0x4009_1d00>;
689impl core::fmt::Debug for Glikey0 {
690 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
691 f.debug_struct("Glikey0").finish()
692 }
693}
694#[doc = "GLIKEY"]
695pub mod glikey0;
696#[doc = "Low-Leakage Wakeup Unit"]
697pub type Wuu0 = crate::Periph<wuu0::RegisterBlock, 0x4009_2000>;
698impl core::fmt::Debug for Wuu0 {
699 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
700 f.debug_struct("Wuu0").finish()
701 }
702}
703#[doc = "Low-Leakage Wakeup Unit"]
704pub mod wuu0;
705#[doc = "VBAT"]
706pub type Vbat0 = crate::Periph<vbat0::RegisterBlock, 0x4009_3000>;
707impl core::fmt::Debug for Vbat0 {
708 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
709 f.debug_struct("Vbat0").finish()
710 }
711}
712#[doc = "VBAT"]
713pub mod vbat0;
714#[doc = "NPX"]
715pub type Fmc0 = crate::Periph<fmc0::RegisterBlock, 0x4009_4000>;
716impl core::fmt::Debug for Fmc0 {
717 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
718 f.debug_struct("Fmc0").finish()
719 }
720}
721#[doc = "NPX"]
722pub mod fmc0;
723#[doc = "Flash"]
724pub type Fmu0 = crate::Periph<fmu0::RegisterBlock, 0x4009_5000>;
725impl core::fmt::Debug for Fmu0 {
726 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
727 f.debug_struct("Fmu0").finish()
728 }
729}
730#[doc = "Flash"]
731pub mod fmu0;
732#[doc = "Flexible I/O"]
733pub type Flexio0 = crate::Periph<flexio0::RegisterBlock, 0x4009_9000>;
734impl core::fmt::Debug for Flexio0 {
735 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
736 f.debug_struct("Flexio0").finish()
737 }
738}
739#[doc = "Flexible I/O"]
740pub mod flexio0;
741#[doc = "Low-Power Inter-Integrated Circuit"]
742pub type Lpi2c0 = crate::Periph<lpi2c0::RegisterBlock, 0x4009_a000>;
743impl core::fmt::Debug for Lpi2c0 {
744 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
745 f.debug_struct("Lpi2c0").finish()
746 }
747}
748#[doc = "Low-Power Inter-Integrated Circuit"]
749pub mod lpi2c0;
750#[doc = "Low-Power Inter-Integrated Circuit"]
751pub type Lpi2c1 = crate::Periph<lpi2c0::RegisterBlock, 0x4009_b000>;
752impl core::fmt::Debug for Lpi2c1 {
753 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
754 f.debug_struct("Lpi2c1").finish()
755 }
756}
757#[doc = "Low-Power Inter-Integrated Circuit"]
758pub use self::lpi2c0 as lpi2c1;
759#[doc = "Low-Power Inter-Integrated Circuit"]
760pub type Lpi2c2 = crate::Periph<lpi2c0::RegisterBlock, 0x400d_4000>;
761impl core::fmt::Debug for Lpi2c2 {
762 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
763 f.debug_struct("Lpi2c2").finish()
764 }
765}
766#[doc = "Low-Power Inter-Integrated Circuit"]
767pub use self::lpi2c0 as lpi2c2;
768#[doc = "Low-Power Inter-Integrated Circuit"]
769pub type Lpi2c3 = crate::Periph<lpi2c0::RegisterBlock, 0x400d_5000>;
770impl core::fmt::Debug for Lpi2c3 {
771 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
772 f.debug_struct("Lpi2c3").finish()
773 }
774}
775#[doc = "Low-Power Inter-Integrated Circuit"]
776pub use self::lpi2c0 as lpi2c3;
777#[doc = "LPUART"]
778pub type Lpuart5 = crate::Periph<lpuart0::RegisterBlock, 0x400d_a000>;
779impl core::fmt::Debug for Lpuart5 {
780 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
781 f.debug_struct("Lpuart5").finish()
782 }
783}
784#[doc = "LPUART"]
785pub use self::lpuart0 as lpuart5;
786#[doc = "Low-Power Serial Peripheral Interface"]
787pub type Lpspi0 = crate::Periph<lpspi0::RegisterBlock, 0x4009_c000>;
788impl core::fmt::Debug for Lpspi0 {
789 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
790 f.debug_struct("Lpspi0").finish()
791 }
792}
793#[doc = "Low-Power Serial Peripheral Interface"]
794pub mod lpspi0;
795#[doc = "Low-Power Serial Peripheral Interface"]
796pub type Lpspi1 = crate::Periph<lpspi0::RegisterBlock, 0x4009_d000>;
797impl core::fmt::Debug for Lpspi1 {
798 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
799 f.debug_struct("Lpspi1").finish()
800 }
801}
802#[doc = "Low-Power Serial Peripheral Interface"]
803pub use self::lpspi0 as lpspi1;
804#[doc = "LPUART"]
805pub type Lpuart0 = crate::Periph<lpuart0::RegisterBlock, 0x4009_f000>;
806impl core::fmt::Debug for Lpuart0 {
807 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
808 f.debug_struct("Lpuart0").finish()
809 }
810}
811#[doc = "LPUART"]
812pub mod lpuart0;
813#[doc = "LPUART"]
814pub type Lpuart1 = crate::Periph<lpuart0::RegisterBlock, 0x400a_0000>;
815impl core::fmt::Debug for Lpuart1 {
816 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
817 f.debug_struct("Lpuart1").finish()
818 }
819}
820#[doc = "LPUART"]
821pub use self::lpuart0 as lpuart1;
822#[doc = "LPUART"]
823pub type Lpuart2 = crate::Periph<lpuart0::RegisterBlock, 0x400a_1000>;
824impl core::fmt::Debug for Lpuart2 {
825 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
826 f.debug_struct("Lpuart2").finish()
827 }
828}
829#[doc = "LPUART"]
830pub use self::lpuart0 as lpuart2;
831#[doc = "LPUART"]
832pub type Lpuart3 = crate::Periph<lpuart0::RegisterBlock, 0x400a_2000>;
833impl core::fmt::Debug for Lpuart3 {
834 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
835 f.debug_struct("Lpuart3").finish()
836 }
837}
838#[doc = "LPUART"]
839pub use self::lpuart0 as lpuart3;
840#[doc = "LPUART"]
841pub type Lpuart4 = crate::Periph<lpuart0::RegisterBlock, 0x400a_3000>;
842impl core::fmt::Debug for Lpuart4 {
843 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
844 f.debug_struct("Lpuart4").finish()
845 }
846}
847#[doc = "LPUART"]
848pub use self::lpuart0 as lpuart4;
849#[doc = "USBFS"]
850pub type Usb0 = crate::Periph<usb0::RegisterBlock, 0x400a_4000>;
851impl core::fmt::Debug for Usb0 {
852 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
853 f.debug_struct("Usb0").finish()
854 }
855}
856#[doc = "USBFS"]
857pub mod usb0;
858#[doc = "Quadrature_Decoder"]
859pub type Eqdc0 = crate::Periph<eqdc0::RegisterBlock, 0x400a_7000>;
860impl core::fmt::Debug for Eqdc0 {
861 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
862 f.debug_struct("Eqdc0").finish()
863 }
864}
865#[doc = "Quadrature_Decoder"]
866pub mod eqdc0;
867#[doc = "Quadrature_Decoder"]
868pub type Eqdc1 = crate::Periph<eqdc0::RegisterBlock, 0x400a_8000>;
869impl core::fmt::Debug for Eqdc1 {
870 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
871 f.debug_struct("Eqdc1").finish()
872 }
873}
874#[doc = "Quadrature_Decoder"]
875pub use self::eqdc0 as eqdc1;
876#[doc = "PWM"]
877pub type Flexpwm0 = crate::Periph<flexpwm0::RegisterBlock, 0x400a_9000>;
878impl core::fmt::Debug for Flexpwm0 {
879 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
880 f.debug_struct("Flexpwm0").finish()
881 }
882}
883#[doc = "PWM"]
884pub mod flexpwm0;
885#[doc = "PWM"]
886pub type Flexpwm1 = crate::Periph<flexpwm0::RegisterBlock, 0x400a_a000>;
887impl core::fmt::Debug for Flexpwm1 {
888 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
889 f.debug_struct("Flexpwm1").finish()
890 }
891}
892#[doc = "PWM"]
893pub use self::flexpwm0 as flexpwm1;
894#[doc = "LPTMR"]
895pub type Lptmr0 = crate::Periph<lptmr0::RegisterBlock, 0x400a_b000>;
896impl core::fmt::Debug for Lptmr0 {
897 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
898 f.debug_struct("Lptmr0").finish()
899 }
900}
901#[doc = "LPTMR"]
902pub mod lptmr0;
903#[doc = "OSTIMER"]
904pub type Ostimer0 = crate::Periph<ostimer0::RegisterBlock, 0x400a_d000>;
905impl core::fmt::Debug for Ostimer0 {
906 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
907 f.debug_struct("Ostimer0").finish()
908 }
909}
910#[doc = "OSTIMER"]
911pub mod ostimer0;
912#[doc = "WAKE_TIMER"]
913pub type Waketimer0 = crate::Periph<waketimer0::RegisterBlock, 0x400a_e000>;
914impl core::fmt::Debug for Waketimer0 {
915 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
916 f.debug_struct("Waketimer0").finish()
917 }
918}
919#[doc = "WAKE_TIMER"]
920pub mod waketimer0;
921#[doc = "ADC"]
922pub type Adc0 = crate::Periph<adc0::RegisterBlock, 0x400a_f000>;
923impl core::fmt::Debug for Adc0 {
924 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
925 f.debug_struct("Adc0").finish()
926 }
927}
928#[doc = "ADC"]
929pub mod adc0;
930#[doc = "ADC"]
931pub type Adc1 = crate::Periph<adc0::RegisterBlock, 0x400b_0000>;
932impl core::fmt::Debug for Adc1 {
933 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
934 f.debug_struct("Adc1").finish()
935 }
936}
937#[doc = "ADC"]
938pub use self::adc0 as adc1;
939#[doc = "LPCMP"]
940pub type Cmp0 = crate::Periph<cmp0::RegisterBlock, 0x400b_1000>;
941impl core::fmt::Debug for Cmp0 {
942 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
943 f.debug_struct("Cmp0").finish()
944 }
945}
946#[doc = "LPCMP"]
947pub mod cmp0;
948#[doc = "LPCMP"]
949pub type Cmp1 = crate::Periph<cmp0::RegisterBlock, 0x400b_2000>;
950impl core::fmt::Debug for Cmp1 {
951 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
952 f.debug_struct("Cmp1").finish()
953 }
954}
955#[doc = "LPCMP"]
956pub use self::cmp0 as cmp1;
957#[doc = "12-bit DAC"]
958pub type Dac0 = crate::Periph<dac0::RegisterBlock, 0x400b_4000>;
959impl core::fmt::Debug for Dac0 {
960 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
961 f.debug_struct("Dac0").finish()
962 }
963}
964#[doc = "12-bit DAC"]
965pub mod dac0;
966#[doc = "OPAMP"]
967pub type Opamp0 = crate::Periph<opamp0::RegisterBlock, 0x400b_7000>;
968impl core::fmt::Debug for Opamp0 {
969 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
970 f.debug_struct("Opamp0").finish()
971 }
972}
973#[doc = "OPAMP"]
974pub mod opamp0;
975#[doc = "PORT"]
976pub type Port0 = crate::Periph<port0::RegisterBlock, 0x400b_c000>;
977impl core::fmt::Debug for Port0 {
978 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
979 f.debug_struct("Port0").finish()
980 }
981}
982#[doc = "PORT"]
983pub mod port0;
984#[doc = "PORT"]
985pub type Port1 = crate::Periph<port0::RegisterBlock, 0x400b_d000>;
986impl core::fmt::Debug for Port1 {
987 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
988 f.debug_struct("Port1").finish()
989 }
990}
991#[doc = "PORT"]
992pub use self::port0 as port1;
993#[doc = "PORT"]
994pub type Port2 = crate::Periph<port0::RegisterBlock, 0x400b_e000>;
995impl core::fmt::Debug for Port2 {
996 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
997 f.debug_struct("Port2").finish()
998 }
999}
1000#[doc = "PORT"]
1001pub use self::port0 as port2;
1002#[doc = "PORT"]
1003pub type Port3 = crate::Periph<port0::RegisterBlock, 0x400b_f000>;
1004impl core::fmt::Debug for Port3 {
1005 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1006 f.debug_struct("Port3").finish()
1007 }
1008}
1009#[doc = "PORT"]
1010pub use self::port0 as port3;
1011#[doc = "PORT"]
1012pub type Port4 = crate::Periph<port0::RegisterBlock, 0x400c_0000>;
1013impl core::fmt::Debug for Port4 {
1014 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1015 f.debug_struct("Port4").finish()
1016 }
1017}
1018#[doc = "PORT"]
1019pub use self::port0 as port4;
1020#[doc = "CAN"]
1021pub type Can0 = crate::Periph<can0::RegisterBlock, 0x400c_c000>;
1022impl core::fmt::Debug for Can0 {
1023 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1024 f.debug_struct("Can0").finish()
1025 }
1026}
1027#[doc = "CAN"]
1028pub mod can0;
1029#[doc = "CAN"]
1030pub type Can1 = crate::Periph<can0::RegisterBlock, 0x400d_0000>;
1031impl core::fmt::Debug for Can1 {
1032 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1033 f.debug_struct("Can1").finish()
1034 }
1035}
1036#[doc = "CAN"]
1037pub use self::can0 as can1;
1038#[doc = "TDET"]
1039pub type Tdet0 = crate::Periph<tdet0::RegisterBlock, 0x400e_9000>;
1040impl core::fmt::Debug for Tdet0 {
1041 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1042 f.debug_struct("Tdet0").finish()
1043 }
1044}
1045#[doc = "TDET"]
1046pub mod tdet0;
1047#[doc = "no description available"]
1048pub type Pkc0 = crate::Periph<pkc0::RegisterBlock, 0x400e_a000>;
1049impl core::fmt::Debug for Pkc0 {
1050 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1051 f.debug_struct("Pkc0").finish()
1052 }
1053}
1054#[doc = "no description available"]
1055pub mod pkc0;
1056#[doc = "no description available"]
1057pub type Sgi0 = crate::Periph<sgi0::RegisterBlock, 0x400e_b000>;
1058impl core::fmt::Debug for Sgi0 {
1059 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1060 f.debug_struct("Sgi0").finish()
1061 }
1062}
1063#[doc = "no description available"]
1064pub mod sgi0;
1065#[doc = "pd_main.trng0"]
1066pub type Trng0 = crate::Periph<trng0::RegisterBlock, 0x400e_c000>;
1067impl core::fmt::Debug for Trng0 {
1068 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1069 f.debug_struct("Trng0").finish()
1070 }
1071}
1072#[doc = "pd_main.trng0"]
1073pub mod trng0;
1074#[doc = "no description available"]
1075pub type Udf0 = crate::Periph<udf0::RegisterBlock, 0x400e_d000>;
1076impl core::fmt::Debug for Udf0 {
1077 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1078 f.debug_struct("Udf0").finish()
1079 }
1080}
1081#[doc = "no description available"]
1082pub mod udf0;
1083#[doc = "RTC"]
1084pub type Rtc0 = crate::Periph<rtc0::RegisterBlock, 0x400e_e000>;
1085impl core::fmt::Debug for Rtc0 {
1086 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1087 f.debug_struct("Rtc0").finish()
1088 }
1089}
1090#[doc = "RTC"]
1091pub mod rtc0;
1092#[doc = "ADC"]
1093pub type Adc2 = crate::Periph<adc0::RegisterBlock, 0x400f_0000>;
1094impl core::fmt::Debug for Adc2 {
1095 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1096 f.debug_struct("Adc2").finish()
1097 }
1098}
1099#[doc = "ADC"]
1100pub use self::adc0 as adc2;
1101#[doc = "ADC"]
1102pub type Adc3 = crate::Periph<adc0::RegisterBlock, 0x400f_1000>;
1103impl core::fmt::Debug for Adc3 {
1104 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1105 f.debug_struct("Adc3").finish()
1106 }
1107}
1108#[doc = "ADC"]
1109pub use self::adc0 as adc3;
1110#[doc = "CDOG"]
1111pub type Cdog0 = crate::Periph<cdog0::RegisterBlock, 0x4010_0000>;
1112impl core::fmt::Debug for Cdog0 {
1113 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1114 f.debug_struct("Cdog0").finish()
1115 }
1116}
1117#[doc = "CDOG"]
1118pub mod cdog0;
1119#[doc = "CDOG"]
1120pub type Cdog1 = crate::Periph<cdog0::RegisterBlock, 0x4010_7000>;
1121impl core::fmt::Debug for Cdog1 {
1122 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1123 f.debug_struct("Cdog1").finish()
1124 }
1125}
1126#[doc = "CDOG"]
1127pub use self::cdog0 as cdog1;
1128#[doc = "DBGMB"]
1129pub type Dbgmailbox = crate::Periph<dbgmailbox::RegisterBlock, 0x4010_1000>;
1130impl core::fmt::Debug for Dbgmailbox {
1131 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1132 f.debug_struct("Dbgmailbox").finish()
1133 }
1134}
1135#[doc = "DBGMB"]
1136pub mod dbgmailbox;
1137#[doc = "GPIO"]
1138pub type Gpio0 = crate::Periph<gpio0::RegisterBlock, 0x4010_2000>;
1139impl core::fmt::Debug for Gpio0 {
1140 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1141 f.debug_struct("Gpio0").finish()
1142 }
1143}
1144#[doc = "GPIO"]
1145pub mod gpio0;
1146#[doc = "GPIO"]
1147pub type Gpio1 = crate::Periph<gpio0::RegisterBlock, 0x4010_3000>;
1148impl core::fmt::Debug for Gpio1 {
1149 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1150 f.debug_struct("Gpio1").finish()
1151 }
1152}
1153#[doc = "GPIO"]
1154pub use self::gpio0 as gpio1;
1155#[doc = "GPIO"]
1156pub type Gpio2 = crate::Periph<gpio0::RegisterBlock, 0x4010_4000>;
1157impl core::fmt::Debug for Gpio2 {
1158 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1159 f.debug_struct("Gpio2").finish()
1160 }
1161}
1162#[doc = "GPIO"]
1163pub use self::gpio0 as gpio2;
1164#[doc = "GPIO"]
1165pub type Gpio3 = crate::Periph<gpio0::RegisterBlock, 0x4010_5000>;
1166impl core::fmt::Debug for Gpio3 {
1167 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1168 f.debug_struct("Gpio3").finish()
1169 }
1170}
1171#[doc = "GPIO"]
1172pub use self::gpio0 as gpio3;
1173#[doc = "GPIO"]
1174pub type Gpio4 = crate::Periph<gpio0::RegisterBlock, 0x4010_6000>;
1175impl core::fmt::Debug for Gpio4 {
1176 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1177 f.debug_struct("Gpio4").finish()
1178 }
1179}
1180#[doc = "GPIO"]
1181pub use self::gpio0 as gpio4;
1182#[doc = "MAUWRAP"]
1183pub type Mau0 = crate::Periph<mau0::RegisterBlock, 0x4010_8000>;
1184impl core::fmt::Debug for Mau0 {
1185 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1186 f.debug_struct("Mau0").finish()
1187 }
1188}
1189#[doc = "MAUWRAP"]
1190pub mod mau0;
1191#[doc = "System Control not in System Control Block"]
1192pub type ScnScb = crate::Periph<scn_scb::RegisterBlock, 0xe000_e000>;
1193impl core::fmt::Debug for ScnScb {
1194 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1195 f.debug_struct("ScnScb").finish()
1196 }
1197}
1198#[doc = "System Control not in System Control Block"]
1199pub mod scn_scb;
1200#[doc = "Security Attribution Unit"]
1201pub type Sau = crate::Periph<sau::RegisterBlock, 0xe000_edd0>;
1202impl core::fmt::Debug for Sau {
1203 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1204 f.debug_struct("Sau").finish()
1205 }
1206}
1207#[doc = "Security Attribution Unit"]
1208pub mod sau;
1209#[no_mangle]
1210static mut DEVICE_PERIPHERALS: bool = false;
1211#[doc = r" All the peripherals."]
1212#[allow(non_snake_case)]
1213pub struct Peripherals {
1214 #[doc = "INPUTMUX0"]
1215 pub inputmux0: Inputmux0,
1216 #[doc = "I3C0"]
1217 pub i3c0: I3c0,
1218 #[doc = "CTIMER0"]
1219 pub ctimer0: Ctimer0,
1220 #[doc = "CTIMER1"]
1221 pub ctimer1: Ctimer1,
1222 #[doc = "CTIMER2"]
1223 pub ctimer2: Ctimer2,
1224 #[doc = "CTIMER3"]
1225 pub ctimer3: Ctimer3,
1226 #[doc = "CTIMER4"]
1227 pub ctimer4: Ctimer4,
1228 #[doc = "FREQME0"]
1229 pub freqme0: Freqme0,
1230 #[doc = "UTICK0"]
1231 pub utick0: Utick0,
1232 #[doc = "WWDT0"]
1233 pub wwdt0: Wwdt0,
1234 #[doc = "SMARTDMA0"]
1235 pub smartdma0: Smartdma0,
1236 #[doc = "DMA0"]
1237 pub dma0: Dma0,
1238 #[doc = "EDMA_0_TCD0"]
1239 pub edma_0_tcd0: Edma0Tcd0,
1240 #[doc = "AOI0"]
1241 pub aoi0: Aoi0,
1242 #[doc = "AOI1"]
1243 pub aoi1: Aoi1,
1244 #[doc = "CRC0"]
1245 pub crc0: Crc0,
1246 #[doc = "CMC"]
1247 pub cmc: Cmc,
1248 #[doc = "EIM0"]
1249 pub eim0: Eim0,
1250 #[doc = "ERM0"]
1251 pub erm0: Erm0,
1252 #[doc = "MBC0"]
1253 pub mbc0: Mbc0,
1254 #[doc = "SCG0"]
1255 pub scg0: Scg0,
1256 #[doc = "SPC0"]
1257 pub spc0: Spc0,
1258 #[doc = "MRCC0"]
1259 pub mrcc0: Mrcc0,
1260 #[doc = "SYSCON"]
1261 pub syscon: Syscon,
1262 #[doc = "GLIKEY0"]
1263 pub glikey0: Glikey0,
1264 #[doc = "WUU0"]
1265 pub wuu0: Wuu0,
1266 #[doc = "VBAT0"]
1267 pub vbat0: Vbat0,
1268 #[doc = "FMC0"]
1269 pub fmc0: Fmc0,
1270 #[doc = "FMU0"]
1271 pub fmu0: Fmu0,
1272 #[doc = "FLEXIO0"]
1273 pub flexio0: Flexio0,
1274 #[doc = "LPI2C0"]
1275 pub lpi2c0: Lpi2c0,
1276 #[doc = "LPI2C1"]
1277 pub lpi2c1: Lpi2c1,
1278 #[doc = "LPI2C2"]
1279 pub lpi2c2: Lpi2c2,
1280 #[doc = "LPI2C3"]
1281 pub lpi2c3: Lpi2c3,
1282 #[doc = "LPUART5"]
1283 pub lpuart5: Lpuart5,
1284 #[doc = "LPSPI0"]
1285 pub lpspi0: Lpspi0,
1286 #[doc = "LPSPI1"]
1287 pub lpspi1: Lpspi1,
1288 #[doc = "LPUART0"]
1289 pub lpuart0: Lpuart0,
1290 #[doc = "LPUART1"]
1291 pub lpuart1: Lpuart1,
1292 #[doc = "LPUART2"]
1293 pub lpuart2: Lpuart2,
1294 #[doc = "LPUART3"]
1295 pub lpuart3: Lpuart3,
1296 #[doc = "LPUART4"]
1297 pub lpuart4: Lpuart4,
1298 #[doc = "USB0"]
1299 pub usb0: Usb0,
1300 #[doc = "EQDC0"]
1301 pub eqdc0: Eqdc0,
1302 #[doc = "EQDC1"]
1303 pub eqdc1: Eqdc1,
1304 #[doc = "FLEXPWM0"]
1305 pub flexpwm0: Flexpwm0,
1306 #[doc = "FLEXPWM1"]
1307 pub flexpwm1: Flexpwm1,
1308 #[doc = "LPTMR0"]
1309 pub lptmr0: Lptmr0,
1310 #[doc = "OSTIMER0"]
1311 pub ostimer0: Ostimer0,
1312 #[doc = "WAKETIMER0"]
1313 pub waketimer0: Waketimer0,
1314 #[doc = "ADC0"]
1315 pub adc0: Adc0,
1316 #[doc = "ADC1"]
1317 pub adc1: Adc1,
1318 #[doc = "CMP0"]
1319 pub cmp0: Cmp0,
1320 #[doc = "CMP1"]
1321 pub cmp1: Cmp1,
1322 #[doc = "DAC0"]
1323 pub dac0: Dac0,
1324 #[doc = "OPAMP0"]
1325 pub opamp0: Opamp0,
1326 #[doc = "PORT0"]
1327 pub port0: Port0,
1328 #[doc = "PORT1"]
1329 pub port1: Port1,
1330 #[doc = "PORT2"]
1331 pub port2: Port2,
1332 #[doc = "PORT3"]
1333 pub port3: Port3,
1334 #[doc = "PORT4"]
1335 pub port4: Port4,
1336 #[doc = "CAN0"]
1337 pub can0: Can0,
1338 #[doc = "CAN1"]
1339 pub can1: Can1,
1340 #[doc = "TDET0"]
1341 pub tdet0: Tdet0,
1342 #[doc = "PKC0"]
1343 pub pkc0: Pkc0,
1344 #[doc = "SGI0"]
1345 pub sgi0: Sgi0,
1346 #[doc = "TRNG0"]
1347 pub trng0: Trng0,
1348 #[doc = "UDF0"]
1349 pub udf0: Udf0,
1350 #[doc = "RTC0"]
1351 pub rtc0: Rtc0,
1352 #[doc = "ADC2"]
1353 pub adc2: Adc2,
1354 #[doc = "ADC3"]
1355 pub adc3: Adc3,
1356 #[doc = "CDOG0"]
1357 pub cdog0: Cdog0,
1358 #[doc = "CDOG1"]
1359 pub cdog1: Cdog1,
1360 #[doc = "DBGMAILBOX"]
1361 pub dbgmailbox: Dbgmailbox,
1362 #[doc = "GPIO0"]
1363 pub gpio0: Gpio0,
1364 #[doc = "GPIO1"]
1365 pub gpio1: Gpio1,
1366 #[doc = "GPIO2"]
1367 pub gpio2: Gpio2,
1368 #[doc = "GPIO3"]
1369 pub gpio3: Gpio3,
1370 #[doc = "GPIO4"]
1371 pub gpio4: Gpio4,
1372 #[doc = "MAU0"]
1373 pub mau0: Mau0,
1374 #[doc = "SCnSCB"]
1375 pub scn_scb: ScnScb,
1376 #[doc = "SAU"]
1377 pub sau: Sau,
1378}
1379impl Peripherals {
1380 #[doc = r" Returns all the peripherals *once*."]
1381 #[cfg(feature = "critical-section")]
1382 #[inline]
1383 pub fn take() -> Option<Self> {
1384 critical_section::with(|_| {
1385 if unsafe { DEVICE_PERIPHERALS } {
1386 return None;
1387 }
1388 Some(unsafe { Peripherals::steal() })
1389 })
1390 }
1391 #[doc = r" Unchecked version of `Peripherals::take`."]
1392 #[doc = r""]
1393 #[doc = r" # Safety"]
1394 #[doc = r""]
1395 #[doc = r" Each of the returned peripherals must be used at most once."]
1396 #[inline]
1397 pub unsafe fn steal() -> Self {
1398 DEVICE_PERIPHERALS = true;
1399 Peripherals {
1400 inputmux0: Inputmux0::steal(),
1401 i3c0: I3c0::steal(),
1402 ctimer0: Ctimer0::steal(),
1403 ctimer1: Ctimer1::steal(),
1404 ctimer2: Ctimer2::steal(),
1405 ctimer3: Ctimer3::steal(),
1406 ctimer4: Ctimer4::steal(),
1407 freqme0: Freqme0::steal(),
1408 utick0: Utick0::steal(),
1409 wwdt0: Wwdt0::steal(),
1410 smartdma0: Smartdma0::steal(),
1411 dma0: Dma0::steal(),
1412 edma_0_tcd0: Edma0Tcd0::steal(),
1413 aoi0: Aoi0::steal(),
1414 aoi1: Aoi1::steal(),
1415 crc0: Crc0::steal(),
1416 cmc: Cmc::steal(),
1417 eim0: Eim0::steal(),
1418 erm0: Erm0::steal(),
1419 mbc0: Mbc0::steal(),
1420 scg0: Scg0::steal(),
1421 spc0: Spc0::steal(),
1422 mrcc0: Mrcc0::steal(),
1423 syscon: Syscon::steal(),
1424 glikey0: Glikey0::steal(),
1425 wuu0: Wuu0::steal(),
1426 vbat0: Vbat0::steal(),
1427 fmc0: Fmc0::steal(),
1428 fmu0: Fmu0::steal(),
1429 flexio0: Flexio0::steal(),
1430 lpi2c0: Lpi2c0::steal(),
1431 lpi2c1: Lpi2c1::steal(),
1432 lpi2c2: Lpi2c2::steal(),
1433 lpi2c3: Lpi2c3::steal(),
1434 lpuart5: Lpuart5::steal(),
1435 lpspi0: Lpspi0::steal(),
1436 lpspi1: Lpspi1::steal(),
1437 lpuart0: Lpuart0::steal(),
1438 lpuart1: Lpuart1::steal(),
1439 lpuart2: Lpuart2::steal(),
1440 lpuart3: Lpuart3::steal(),
1441 lpuart4: Lpuart4::steal(),
1442 usb0: Usb0::steal(),
1443 eqdc0: Eqdc0::steal(),
1444 eqdc1: Eqdc1::steal(),
1445 flexpwm0: Flexpwm0::steal(),
1446 flexpwm1: Flexpwm1::steal(),
1447 lptmr0: Lptmr0::steal(),
1448 ostimer0: Ostimer0::steal(),
1449 waketimer0: Waketimer0::steal(),
1450 adc0: Adc0::steal(),
1451 adc1: Adc1::steal(),
1452 cmp0: Cmp0::steal(),
1453 cmp1: Cmp1::steal(),
1454 dac0: Dac0::steal(),
1455 opamp0: Opamp0::steal(),
1456 port0: Port0::steal(),
1457 port1: Port1::steal(),
1458 port2: Port2::steal(),
1459 port3: Port3::steal(),
1460 port4: Port4::steal(),
1461 can0: Can0::steal(),
1462 can1: Can1::steal(),
1463 tdet0: Tdet0::steal(),
1464 pkc0: Pkc0::steal(),
1465 sgi0: Sgi0::steal(),
1466 trng0: Trng0::steal(),
1467 udf0: Udf0::steal(),
1468 rtc0: Rtc0::steal(),
1469 adc2: Adc2::steal(),
1470 adc3: Adc3::steal(),
1471 cdog0: Cdog0::steal(),
1472 cdog1: Cdog1::steal(),
1473 dbgmailbox: Dbgmailbox::steal(),
1474 gpio0: Gpio0::steal(),
1475 gpio1: Gpio1::steal(),
1476 gpio2: Gpio2::steal(),
1477 gpio3: Gpio3::steal(),
1478 gpio4: Gpio4::steal(),
1479 mau0: Mau0::steal(),
1480 scn_scb: ScnScb::steal(),
1481 sau: Sau::steal(),
1482 }
1483 }
1484}