1#[doc = "Register `IR` reader"]
2pub type R = crate::R<IR_SPEC>;
3#[doc = "Register `IR` writer"]
4pub type W = crate::W<IR_SPEC>;
5#[doc = "Field `RF0N` reader - Rx FIFO 0 New Message"]
6pub type RF0N_R = crate::BitReader;
7#[doc = "Field `RF0N` writer - Rx FIFO 0 New Message"]
8pub type RF0N_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
9#[doc = "Field `RF0W` reader - Rx FIFO 0 Watermark Reached"]
10pub type RF0W_R = crate::BitReader;
11#[doc = "Field `RF0W` writer - Rx FIFO 0 Watermark Reached"]
12pub type RF0W_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
13#[doc = "Field `RF0F` reader - Rx FIFO 0 Full"]
14pub type RF0F_R = crate::BitReader;
15#[doc = "Field `RF0F` writer - Rx FIFO 0 Full"]
16pub type RF0F_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
17#[doc = "Field `RF0L` reader - Rx FIFO 0 Message Lost"]
18pub type RF0L_R = crate::BitReader;
19#[doc = "Field `RF0L` writer - Rx FIFO 0 Message Lost"]
20pub type RF0L_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
21#[doc = "Field `RF1N` reader - Rx FIFO 1 New Message"]
22pub type RF1N_R = crate::BitReader;
23#[doc = "Field `RF1N` writer - Rx FIFO 1 New Message"]
24pub type RF1N_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
25#[doc = "Field `RF1W` reader - Rx FIFO 1 Watermark Reached"]
26pub type RF1W_R = crate::BitReader;
27#[doc = "Field `RF1W` writer - Rx FIFO 1 Watermark Reached"]
28pub type RF1W_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
29#[doc = "Field `RF1F` reader - Rx FIFO 1 FIFO Full"]
30pub type RF1F_R = crate::BitReader;
31#[doc = "Field `RF1F` writer - Rx FIFO 1 FIFO Full"]
32pub type RF1F_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
33#[doc = "Field `RF1L` reader - Rx FIFO 1 Message Lost"]
34pub type RF1L_R = crate::BitReader;
35#[doc = "Field `RF1L` writer - Rx FIFO 1 Message Lost"]
36pub type RF1L_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
37#[doc = "Field `HPM` reader - High Priority Message"]
38pub type HPM_R = crate::BitReader;
39#[doc = "Field `HPM` writer - High Priority Message"]
40pub type HPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
41#[doc = "Field `TC` reader - Timestamp Completed"]
42pub type TC_R = crate::BitReader;
43#[doc = "Field `TC` writer - Timestamp Completed"]
44pub type TC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
45#[doc = "Field `TCF` reader - Transmission Cancellation Finished"]
46pub type TCF_R = crate::BitReader;
47#[doc = "Field `TCF` writer - Transmission Cancellation Finished"]
48pub type TCF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
49#[doc = "Field `TFE` reader - Tx FIFO Empty"]
50pub type TFE_R = crate::BitReader;
51#[doc = "Field `TFE` writer - Tx FIFO Empty"]
52pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
53#[doc = "Field `TEFN` reader - Tx Event FIFO New Entry"]
54pub type TEFN_R = crate::BitReader;
55#[doc = "Field `TEFN` writer - Tx Event FIFO New Entry"]
56pub type TEFN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
57#[doc = "Field `TEFW` reader - Tx Event FIFO Watermark Reached"]
58pub type TEFW_R = crate::BitReader;
59#[doc = "Field `TEFW` writer - Tx Event FIFO Watermark Reached"]
60pub type TEFW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
61#[doc = "Field `TEFF` reader - Tx Event FIFO Full"]
62pub type TEFF_R = crate::BitReader;
63#[doc = "Field `TEFF` writer - Tx Event FIFO Full"]
64pub type TEFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
65#[doc = "Field `TEFL` reader - Tx Event FIFO Element Lost"]
66pub type TEFL_R = crate::BitReader;
67#[doc = "Field `TEFL` writer - Tx Event FIFO Element Lost"]
68pub type TEFL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
69#[doc = "Field `TSW` reader - Timestamp Wraparound"]
70pub type TSW_R = crate::BitReader;
71#[doc = "Field `TSW` writer - Timestamp Wraparound"]
72pub type TSW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
73#[doc = "Field `MRAF` reader - Message RAM Access Failure"]
74pub type MRAF_R = crate::BitReader;
75#[doc = "Field `MRAF` writer - Message RAM Access Failure"]
76pub type MRAF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
77#[doc = "Field `TOO` reader - Timeout Occurred"]
78pub type TOO_R = crate::BitReader;
79#[doc = "Field `TOO` writer - Timeout Occurred"]
80pub type TOO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
81#[doc = "Field `DRX` reader - Message stored to Dedicated Rx Buffer"]
82pub type DRX_R = crate::BitReader;
83#[doc = "Field `DRX` writer - Message stored to Dedicated Rx Buffer"]
84pub type DRX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
85#[doc = "Field `BEC` reader - Bit Error Corrected"]
86pub type BEC_R = crate::BitReader;
87#[doc = "Field `BEC` writer - Bit Error Corrected"]
88pub type BEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
89#[doc = "Field `BEU` reader - Bit Error Uncorrected"]
90pub type BEU_R = crate::BitReader;
91#[doc = "Field `BEU` writer - Bit Error Uncorrected"]
92pub type BEU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
93#[doc = "Field `ELO` reader - Error Logging Overflow"]
94pub type ELO_R = crate::BitReader;
95#[doc = "Field `ELO` writer - Error Logging Overflow"]
96pub type ELO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
97#[doc = "Field `EP` reader - Error Passive"]
98pub type EP_R = crate::BitReader;
99#[doc = "Field `EP` writer - Error Passive"]
100pub type EP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
101#[doc = "Field `EW` reader - Warning Status"]
102pub type EW_R = crate::BitReader;
103#[doc = "Field `EW` writer - Warning Status"]
104pub type EW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
105#[doc = "Field `BO` reader - Bus_Off Status"]
106pub type BO_R = crate::BitReader;
107#[doc = "Field `BO` writer - Bus_Off Status"]
108pub type BO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
109#[doc = "Field `WDI` reader - Watchdog Interrupt"]
110pub type WDI_R = crate::BitReader;
111#[doc = "Field `WDI` writer - Watchdog Interrupt"]
112pub type WDI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
113#[doc = "Field `PEA` reader - Protocol Error in Arbitration Phase"]
114pub type PEA_R = crate::BitReader;
115#[doc = "Field `PEA` writer - Protocol Error in Arbitration Phase"]
116pub type PEA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
117#[doc = "Field `PED` reader - Protocol Error in Data Phase"]
118pub type PED_R = crate::BitReader;
119#[doc = "Field `PED` writer - Protocol Error in Data Phase"]
120pub type PED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
121#[doc = "Field `ARA` reader - Access to Reserved Address"]
122pub type ARA_R = crate::BitReader;
123#[doc = "Field `ARA` writer - Access to Reserved Address"]
124pub type ARA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
125impl R {
126 #[doc = "Bit 0 - Rx FIFO 0 New Message"]
127 #[inline(always)]
128 pub fn rf0n(&self) -> RF0N_R {
129 RF0N_R::new((self.bits & 1) != 0)
130 }
131 #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached"]
132 #[inline(always)]
133 pub fn rf0w(&self) -> RF0W_R {
134 RF0W_R::new(((self.bits >> 1) & 1) != 0)
135 }
136 #[doc = "Bit 2 - Rx FIFO 0 Full"]
137 #[inline(always)]
138 pub fn rf0f(&self) -> RF0F_R {
139 RF0F_R::new(((self.bits >> 2) & 1) != 0)
140 }
141 #[doc = "Bit 3 - Rx FIFO 0 Message Lost"]
142 #[inline(always)]
143 pub fn rf0l(&self) -> RF0L_R {
144 RF0L_R::new(((self.bits >> 3) & 1) != 0)
145 }
146 #[doc = "Bit 4 - Rx FIFO 1 New Message"]
147 #[inline(always)]
148 pub fn rf1n(&self) -> RF1N_R {
149 RF1N_R::new(((self.bits >> 4) & 1) != 0)
150 }
151 #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached"]
152 #[inline(always)]
153 pub fn rf1w(&self) -> RF1W_R {
154 RF1W_R::new(((self.bits >> 5) & 1) != 0)
155 }
156 #[doc = "Bit 6 - Rx FIFO 1 FIFO Full"]
157 #[inline(always)]
158 pub fn rf1f(&self) -> RF1F_R {
159 RF1F_R::new(((self.bits >> 6) & 1) != 0)
160 }
161 #[doc = "Bit 7 - Rx FIFO 1 Message Lost"]
162 #[inline(always)]
163 pub fn rf1l(&self) -> RF1L_R {
164 RF1L_R::new(((self.bits >> 7) & 1) != 0)
165 }
166 #[doc = "Bit 8 - High Priority Message"]
167 #[inline(always)]
168 pub fn hpm(&self) -> HPM_R {
169 HPM_R::new(((self.bits >> 8) & 1) != 0)
170 }
171 #[doc = "Bit 9 - Timestamp Completed"]
172 #[inline(always)]
173 pub fn tc(&self) -> TC_R {
174 TC_R::new(((self.bits >> 9) & 1) != 0)
175 }
176 #[doc = "Bit 10 - Transmission Cancellation Finished"]
177 #[inline(always)]
178 pub fn tcf(&self) -> TCF_R {
179 TCF_R::new(((self.bits >> 10) & 1) != 0)
180 }
181 #[doc = "Bit 11 - Tx FIFO Empty"]
182 #[inline(always)]
183 pub fn tfe(&self) -> TFE_R {
184 TFE_R::new(((self.bits >> 11) & 1) != 0)
185 }
186 #[doc = "Bit 12 - Tx Event FIFO New Entry"]
187 #[inline(always)]
188 pub fn tefn(&self) -> TEFN_R {
189 TEFN_R::new(((self.bits >> 12) & 1) != 0)
190 }
191 #[doc = "Bit 13 - Tx Event FIFO Watermark Reached"]
192 #[inline(always)]
193 pub fn tefw(&self) -> TEFW_R {
194 TEFW_R::new(((self.bits >> 13) & 1) != 0)
195 }
196 #[doc = "Bit 14 - Tx Event FIFO Full"]
197 #[inline(always)]
198 pub fn teff(&self) -> TEFF_R {
199 TEFF_R::new(((self.bits >> 14) & 1) != 0)
200 }
201 #[doc = "Bit 15 - Tx Event FIFO Element Lost"]
202 #[inline(always)]
203 pub fn tefl(&self) -> TEFL_R {
204 TEFL_R::new(((self.bits >> 15) & 1) != 0)
205 }
206 #[doc = "Bit 16 - Timestamp Wraparound"]
207 #[inline(always)]
208 pub fn tsw(&self) -> TSW_R {
209 TSW_R::new(((self.bits >> 16) & 1) != 0)
210 }
211 #[doc = "Bit 17 - Message RAM Access Failure"]
212 #[inline(always)]
213 pub fn mraf(&self) -> MRAF_R {
214 MRAF_R::new(((self.bits >> 17) & 1) != 0)
215 }
216 #[doc = "Bit 18 - Timeout Occurred"]
217 #[inline(always)]
218 pub fn too(&self) -> TOO_R {
219 TOO_R::new(((self.bits >> 18) & 1) != 0)
220 }
221 #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer"]
222 #[inline(always)]
223 pub fn drx(&self) -> DRX_R {
224 DRX_R::new(((self.bits >> 19) & 1) != 0)
225 }
226 #[doc = "Bit 20 - Bit Error Corrected"]
227 #[inline(always)]
228 pub fn bec(&self) -> BEC_R {
229 BEC_R::new(((self.bits >> 20) & 1) != 0)
230 }
231 #[doc = "Bit 21 - Bit Error Uncorrected"]
232 #[inline(always)]
233 pub fn beu(&self) -> BEU_R {
234 BEU_R::new(((self.bits >> 21) & 1) != 0)
235 }
236 #[doc = "Bit 22 - Error Logging Overflow"]
237 #[inline(always)]
238 pub fn elo(&self) -> ELO_R {
239 ELO_R::new(((self.bits >> 22) & 1) != 0)
240 }
241 #[doc = "Bit 23 - Error Passive"]
242 #[inline(always)]
243 pub fn ep(&self) -> EP_R {
244 EP_R::new(((self.bits >> 23) & 1) != 0)
245 }
246 #[doc = "Bit 24 - Warning Status"]
247 #[inline(always)]
248 pub fn ew(&self) -> EW_R {
249 EW_R::new(((self.bits >> 24) & 1) != 0)
250 }
251 #[doc = "Bit 25 - Bus_Off Status"]
252 #[inline(always)]
253 pub fn bo(&self) -> BO_R {
254 BO_R::new(((self.bits >> 25) & 1) != 0)
255 }
256 #[doc = "Bit 26 - Watchdog Interrupt"]
257 #[inline(always)]
258 pub fn wdi(&self) -> WDI_R {
259 WDI_R::new(((self.bits >> 26) & 1) != 0)
260 }
261 #[doc = "Bit 27 - Protocol Error in Arbitration Phase"]
262 #[inline(always)]
263 pub fn pea(&self) -> PEA_R {
264 PEA_R::new(((self.bits >> 27) & 1) != 0)
265 }
266 #[doc = "Bit 28 - Protocol Error in Data Phase"]
267 #[inline(always)]
268 pub fn ped(&self) -> PED_R {
269 PED_R::new(((self.bits >> 28) & 1) != 0)
270 }
271 #[doc = "Bit 29 - Access to Reserved Address"]
272 #[inline(always)]
273 pub fn ara(&self) -> ARA_R {
274 ARA_R::new(((self.bits >> 29) & 1) != 0)
275 }
276}
277impl W {
278 #[doc = "Bit 0 - Rx FIFO 0 New Message"]
279 #[inline(always)]
280 #[must_use]
281 pub fn rf0n(&mut self) -> RF0N_W<IR_SPEC, 0> {
282 RF0N_W::new(self)
283 }
284 #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached"]
285 #[inline(always)]
286 #[must_use]
287 pub fn rf0w(&mut self) -> RF0W_W<IR_SPEC, 1> {
288 RF0W_W::new(self)
289 }
290 #[doc = "Bit 2 - Rx FIFO 0 Full"]
291 #[inline(always)]
292 #[must_use]
293 pub fn rf0f(&mut self) -> RF0F_W<IR_SPEC, 2> {
294 RF0F_W::new(self)
295 }
296 #[doc = "Bit 3 - Rx FIFO 0 Message Lost"]
297 #[inline(always)]
298 #[must_use]
299 pub fn rf0l(&mut self) -> RF0L_W<IR_SPEC, 3> {
300 RF0L_W::new(self)
301 }
302 #[doc = "Bit 4 - Rx FIFO 1 New Message"]
303 #[inline(always)]
304 #[must_use]
305 pub fn rf1n(&mut self) -> RF1N_W<IR_SPEC, 4> {
306 RF1N_W::new(self)
307 }
308 #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached"]
309 #[inline(always)]
310 #[must_use]
311 pub fn rf1w(&mut self) -> RF1W_W<IR_SPEC, 5> {
312 RF1W_W::new(self)
313 }
314 #[doc = "Bit 6 - Rx FIFO 1 FIFO Full"]
315 #[inline(always)]
316 #[must_use]
317 pub fn rf1f(&mut self) -> RF1F_W<IR_SPEC, 6> {
318 RF1F_W::new(self)
319 }
320 #[doc = "Bit 7 - Rx FIFO 1 Message Lost"]
321 #[inline(always)]
322 #[must_use]
323 pub fn rf1l(&mut self) -> RF1L_W<IR_SPEC, 7> {
324 RF1L_W::new(self)
325 }
326 #[doc = "Bit 8 - High Priority Message"]
327 #[inline(always)]
328 #[must_use]
329 pub fn hpm(&mut self) -> HPM_W<IR_SPEC, 8> {
330 HPM_W::new(self)
331 }
332 #[doc = "Bit 9 - Timestamp Completed"]
333 #[inline(always)]
334 #[must_use]
335 pub fn tc(&mut self) -> TC_W<IR_SPEC, 9> {
336 TC_W::new(self)
337 }
338 #[doc = "Bit 10 - Transmission Cancellation Finished"]
339 #[inline(always)]
340 #[must_use]
341 pub fn tcf(&mut self) -> TCF_W<IR_SPEC, 10> {
342 TCF_W::new(self)
343 }
344 #[doc = "Bit 11 - Tx FIFO Empty"]
345 #[inline(always)]
346 #[must_use]
347 pub fn tfe(&mut self) -> TFE_W<IR_SPEC, 11> {
348 TFE_W::new(self)
349 }
350 #[doc = "Bit 12 - Tx Event FIFO New Entry"]
351 #[inline(always)]
352 #[must_use]
353 pub fn tefn(&mut self) -> TEFN_W<IR_SPEC, 12> {
354 TEFN_W::new(self)
355 }
356 #[doc = "Bit 13 - Tx Event FIFO Watermark Reached"]
357 #[inline(always)]
358 #[must_use]
359 pub fn tefw(&mut self) -> TEFW_W<IR_SPEC, 13> {
360 TEFW_W::new(self)
361 }
362 #[doc = "Bit 14 - Tx Event FIFO Full"]
363 #[inline(always)]
364 #[must_use]
365 pub fn teff(&mut self) -> TEFF_W<IR_SPEC, 14> {
366 TEFF_W::new(self)
367 }
368 #[doc = "Bit 15 - Tx Event FIFO Element Lost"]
369 #[inline(always)]
370 #[must_use]
371 pub fn tefl(&mut self) -> TEFL_W<IR_SPEC, 15> {
372 TEFL_W::new(self)
373 }
374 #[doc = "Bit 16 - Timestamp Wraparound"]
375 #[inline(always)]
376 #[must_use]
377 pub fn tsw(&mut self) -> TSW_W<IR_SPEC, 16> {
378 TSW_W::new(self)
379 }
380 #[doc = "Bit 17 - Message RAM Access Failure"]
381 #[inline(always)]
382 #[must_use]
383 pub fn mraf(&mut self) -> MRAF_W<IR_SPEC, 17> {
384 MRAF_W::new(self)
385 }
386 #[doc = "Bit 18 - Timeout Occurred"]
387 #[inline(always)]
388 #[must_use]
389 pub fn too(&mut self) -> TOO_W<IR_SPEC, 18> {
390 TOO_W::new(self)
391 }
392 #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer"]
393 #[inline(always)]
394 #[must_use]
395 pub fn drx(&mut self) -> DRX_W<IR_SPEC, 19> {
396 DRX_W::new(self)
397 }
398 #[doc = "Bit 20 - Bit Error Corrected"]
399 #[inline(always)]
400 #[must_use]
401 pub fn bec(&mut self) -> BEC_W<IR_SPEC, 20> {
402 BEC_W::new(self)
403 }
404 #[doc = "Bit 21 - Bit Error Uncorrected"]
405 #[inline(always)]
406 #[must_use]
407 pub fn beu(&mut self) -> BEU_W<IR_SPEC, 21> {
408 BEU_W::new(self)
409 }
410 #[doc = "Bit 22 - Error Logging Overflow"]
411 #[inline(always)]
412 #[must_use]
413 pub fn elo(&mut self) -> ELO_W<IR_SPEC, 22> {
414 ELO_W::new(self)
415 }
416 #[doc = "Bit 23 - Error Passive"]
417 #[inline(always)]
418 #[must_use]
419 pub fn ep(&mut self) -> EP_W<IR_SPEC, 23> {
420 EP_W::new(self)
421 }
422 #[doc = "Bit 24 - Warning Status"]
423 #[inline(always)]
424 #[must_use]
425 pub fn ew(&mut self) -> EW_W<IR_SPEC, 24> {
426 EW_W::new(self)
427 }
428 #[doc = "Bit 25 - Bus_Off Status"]
429 #[inline(always)]
430 #[must_use]
431 pub fn bo(&mut self) -> BO_W<IR_SPEC, 25> {
432 BO_W::new(self)
433 }
434 #[doc = "Bit 26 - Watchdog Interrupt"]
435 #[inline(always)]
436 #[must_use]
437 pub fn wdi(&mut self) -> WDI_W<IR_SPEC, 26> {
438 WDI_W::new(self)
439 }
440 #[doc = "Bit 27 - Protocol Error in Arbitration Phase"]
441 #[inline(always)]
442 #[must_use]
443 pub fn pea(&mut self) -> PEA_W<IR_SPEC, 27> {
444 PEA_W::new(self)
445 }
446 #[doc = "Bit 28 - Protocol Error in Data Phase"]
447 #[inline(always)]
448 #[must_use]
449 pub fn ped(&mut self) -> PED_W<IR_SPEC, 28> {
450 PED_W::new(self)
451 }
452 #[doc = "Bit 29 - Access to Reserved Address"]
453 #[inline(always)]
454 #[must_use]
455 pub fn ara(&mut self) -> ARA_W<IR_SPEC, 29> {
456 ARA_W::new(self)
457 }
458 #[doc = r" Writes raw bits to the register."]
459 #[doc = r""]
460 #[doc = r" # Safety"]
461 #[doc = r""]
462 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
463 #[inline(always)]
464 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
465 self.bits = bits;
466 self
467 }
468}
469#[doc = "Interrupt\n\nYou can [`read`](crate::reg::generic::Reg::read) this register and get [`ir::R`](R). You can [`reset`](crate::reg::generic::Reg::reset), [`write`](crate::reg::generic::Reg::write), [`write_with_zero`](crate::reg::generic::Reg::write_with_zero) this register using [`ir::W`](W). You can also [`modify`](crate::reg::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
470pub struct IR_SPEC;
471impl crate::RegisterSpec for IR_SPEC {
472 type Ux = u32;
473}
474#[doc = "`read()` method returns [`ir::R`](R) reader structure"]
475impl crate::Readable for IR_SPEC {}
476#[doc = "`write(|w| ..)` method takes [`ir::W`](W) writer structure"]
477impl crate::Writable for IR_SPEC {
478 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
479 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
480}
481#[doc = "`reset()` method sets IR to value 0"]
482impl crate::Resettable for IR_SPEC {
483 const RESET_VALUE: Self::Ux = 0;
484}